#define CONFIG_MII 1 /* MII PHY management */
#ifndef CONFIG_EXT_PHY
#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
-#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
+#define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */
#else
#define CONFIG_PHY_ADDR 2 /* PHY address */
#endif
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_NAND | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
*/
#define CFG_NAND0_BASE 0xFF400000
#define CFG_NAND1_BASE 0xFF000000
+#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
+#define NAND_BIG_DELAY_US 25
/* For CATcenter there is only NAND on the module */
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
-#define NAND_DISABLE_CE(nand) do \
+#define MACRO_NAND_DISABLE_CE(nandptr) do \
{ \
- switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+ switch((unsigned long)nandptr) \
{ \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
} \
} while(0)
-#define NAND_ENABLE_CE(nand) do \
+#define MACRO_NAND_ENABLE_CE(nandptr) do \
{ \
- switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+ switch((unsigned long)nandptr) \
{ \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
} \
} while(0)
-
-#define NAND_CTL_CLRALE(nandptr) do \
+#define MACRO_NAND_CTL_CLRALE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
} \
} while(0)
-#define NAND_CTL_SETALE(nandptr) do \
+#define MACRO_NAND_CTL_SETALE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
} \
} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do \
+#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
} \
} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { \
+#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
switch((unsigned long)nandptr) { \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-#endif
-
/*-----------------------------------------------------------------------
* Environment Variable setup
*/
-#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#define CFG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
-#define CFG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
-#define CFG_ENV_ADDR_REDUND 0xFFFFA000
-#define CFG_ENV_SIZE_REDUND 0x2000
+#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
+#define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
+#define CONFIG_ENV_ADDR_REDUND 0xFFFFA000
+#define CONFIG_ENV_SIZE_REDUND 0x2000
+
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CFG_NVRAM_SIZE 242 /* NVRAM size */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
#define CONFIG_VGA_AS_SINGLE_DEVICE
/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
#define CFG_ISA_IO 0xE8000000
-/* see also drivers/videomodes.c */
+/* see also drivers/video/videomodes.c */
#define CFG_DEFAULT_VIDEO_MODE 0x303
#endif
#endif /* CONFIG_NO_SERIAL_EEPROM */
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */
-#define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */
-#define CONFIG_JFFS2_NAND_SIZE 2*1024*1024 /* size of jffs2 partition */
#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nand"
+#define CONFIG_JFFS2_PART_SIZE 0x00200000
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support
+ *
+ * Note: fake mtd_id used, no linux mtd map file
+ */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nand0=catcenter"
+#define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)"
+*/
+
#endif /* __CONFIG_H */
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