ppc4xx: Remove cache definition from 4xx board config files
[platform/kernel/u-boot.git] / include / configs / CANBT.h
index 21bc441..7029dbd 100644 (file)
 
 #define CONFIG_PHY_ADDR                0       /* PHY address                  */
 
-#define CONFIG_COMMANDS             (( CONFIG_CMD_DFL  |       \
-                               CFG_CMD_IRQ     |       \
-                               CFG_CMD_EEPROM      ) & \
-                              ~CFG_CMD_NET)
 
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_EEPROM
+
+#undef CONFIG_CMD_NET
+
 
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 
@@ -73,7 +86,7 @@
  */
 #define CFG_LONGHELP                   /* undef to save memory         */
 #define CFG_PROMPT     "=> "           /* Monitor Command Prompt       */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CBSIZE     1024            /* Console I/O Buffer Size      */
 #else
 #define CFG_CBSIZE     256             /* Console I/O Buffer Size      */
 /* mask of address bits that overflow into the "EEPROM chip address"   */
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW   0x07
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE                8192    /* For IBM 405 CPUs                     */
-#define CFG_CACHELINE_SIZE     32      /* ...                  */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
-#endif
-
 /*
  * Init Memory Controller:
  *