Merge tag 'video-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-video into...

[platform/kernel/u-boot.git] / include / configs / C29XPCIE.h

diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 1771104..9a8cba6 100644 (file)
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -10,20 +10,21 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <linux/stringify.h>
+
 #ifdef CONFIG_SPIFLASH
 #define CONFIG_RAMBOOT_SPIFLASH
 #define CONFIG_RESET_VECTOR_ADDRESS    0x110bfffc
 #endif
 
-#ifdef CONFIG_NAND
+#ifdef CONFIG_MTD_RAW_NAND
 #ifdef CONFIG_TPL_BUILD
-#define CONFIG_SPL_NAND_BOOT
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_NAND_INIT
 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SPL_MAX_SIZE            (128 << 10)
-#define CONFIG_SPL_TEXT_BASE           0xf8f81000
+#define CONFIG_TPL_TEXT_BASE           0xf8f81000
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (832 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST     (0x11000000)
@@ -33,7 +34,6 @@
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_NAND_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TEXT_BASE           0xff800000
 #define CONFIG_SPL_MAX_SIZE            8192
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (128 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST     0xf8f80000
@@ -43,14 +43,15 @@
 #define CONFIG_SPL_PAD_TO              0x20000
 #define CONFIG_TPL_PAD_TO              0x20000
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
-#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #endif
 
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
 #endif
 
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE        CONFIG_TPL_TEXT_BASE
+#elif defined(CONFIG_SPL_BUILD)
 #define CONFIG_SYS_MONITOR_BASE        CONFIG_SPL_TEXT_BASE
 #else
 #define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE    /* start of monitor */
@@ -67,7 +68,6 @@
 #define CONFIG_PCIE1                   /* PCIE controller 1 (slot 1) */
 #define CONFIG_FSL_PCI_INIT            /* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_PCIE_RESET          /* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT           /* enable 64-bit PCI resources */
 
 /*
@@ -107,9 +107,6 @@
 #define CONFIG_ADDR_MAP                        1
 #define CONFIG_SYS_NUM_ADDR_MAP                16      /* number of TLB1 entries */
 
-#define CONFIG_SYS_MEMTEST_START       0x00200000
-#define CONFIG_SYS_MEMTEST_END         0x00400000
-
 /* DDR Setup */
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM         0
@@ -175,10 +172,7 @@
 #define CONFIG_SYS_NOR_FTIM3   0x0
 
 /* CFI for NOR Flash */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 /* NAND Flash on IFC */
 #define CONFIG_NAND_FSL_IFC
@@ -220,7 +214,7 @@
 #define CONFIG_SYS_NAND_DDR_LAW                11
 
 /* Set up IFC registers for boot location NOR/NAND */
-#ifdef CONFIG_NAND
+#ifdef CONFIG_MTD_RAW_NAND
 #define CONFIG_SYS_CSPR0               CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK0              CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR0               CONFIG_SYS_NAND_CSOR
@@ -278,7 +272,6 @@
 
 #if defined(CONFIG_RAMBOOT_SPIFLASH)
 #define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
 #endif
 
 #define CONFIG_SYS_INIT_RAM_LOCK
@@ -306,7 +299,7 @@
 #define CONFIG_SPL_RELOC_MALLOC_ADDR   (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE   (96 << 10)
 #define CONFIG_SPL_GD_ADDR             (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
-#elif defined(CONFIG_NAND)
+#elif defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_SYS_INIT_L2_ADDR                0xf8f80000
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS   CONFIG_SYS_INIT_L2_ADDR
@@ -359,8 +352,6 @@
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 
 /* eSPI - Enhanced SPI */
-#define CONFIG_SF_DEFAULT_SPEED                10000000
-#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
 
 #ifdef CONFIG_TSEC_ENET
 #define CONFIG_MII_DEFAULT_TSEC        1       /* Allow unregistered phys */
@@ -383,28 +374,12 @@
  * Environment
  */
 #if defined(CONFIG_SYS_RAMBOOT)
-#if defined(CONFIG_RAMBOOT_SPIFLASH)
-#define CONFIG_ENV_SPI_BUS     0
-#define CONFIG_ENV_SPI_CS      0
-#define CONFIG_ENV_SPI_MAX_HZ  10000000
-#define CONFIG_ENV_SPI_MODE    0
-#define CONFIG_ENV_OFFSET      0x100000        /* 1MB */
-#define CONFIG_ENV_SECT_SIZE   0x10000
-#define CONFIG_ENV_SIZE                0x2000
-#endif
-#elif defined(CONFIG_NAND)
+#elif defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
-#define CONFIG_ENV_SIZE                0x2000
-#define CONFIG_ENV_ADDR                (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#define SPL_ENV_ADDR           (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 #else
-#define CONFIG_ENV_SIZE                CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_RANGE       CONFIG_ENV_SIZE
 #endif
-#define CONFIG_ENV_OFFSET      CONFIG_SYS_NAND_BLOCK_SIZE
-#else
-#define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE                0x2000
-#define CONFIG_ENV_SECT_SIZE   0x20000
 #endif
 
 #define CONFIG_LOADS_ECHO