/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
/*
#define CONFIG_PANIC_HANG
/* DDR Setup */
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x50
CSPR_V)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
+
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
FTIM0_NOR_TEADC(0x5) | \
FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1e) | \
- FTIM1_NOR_TRAD_NOR(0x0f) | \
- FTIM1_NOR_TSEQRAD_NOR(0x0f))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1A) |\
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0x0E) | \
FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3 0x0
| CSPR_MSEL_NAND \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2k */ \
- | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
+ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
+ | CSOR_NAND_PGS_8K /* Page Size = 8K */ \
+ | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
+ | CSOR_NAND_PB(128)) /*128 Pages Per Block*/
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
FTIM0_NAND_TWP(0x0c) | \
FTIM0_NAND_TWCHT(0x08) | \
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
#define CONFIG_BAUDRATE 115200
+#define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
"netdev=eth0\0" \