configs: Migrate CMD_NAND*

[platform/kernel/u-boot.git] / include / configs / C29XPCIE.h

diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index a7a5e8e..050847b 100644 (file)
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -11,13 +11,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_PHYS_64BIT
-#define CONFIG_DISPLAY_BOARDINFO
-
-#ifdef CONFIG_C29XPCIE
-#define CONFIG_PPC_C29X
-#endif
-
 #ifdef CONFIG_SPIFLASH
 #define CONFIG_RAMBOOT_SPIFLASH
 #define CONFIG_SYS_TEXT_BASE           0x11000000
@@ -28,15 +21,8 @@
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_SPL_NAND_BOOT
 #define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SPL_NAND_INIT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_TPL_DRIVERS_MISC_SUPPORT
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SPL_MAX_SIZE            (128 << 10)
 #define CONFIG_SPL_TEXT_BASE           0xf8f81000
@@ -47,8 +33,6 @@
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    ((128 + 128) << 10)
 #elif defined(CONFIG_SPL_BUILD)
 #define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_NAND_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TEXT_BASE           0xff800000
@@ -84,15 +68,10 @@
 #endif
 
 /* High Level Configuration Options */
-#define CONFIG_BOOKE                   /* BOOKE */
-#define CONFIG_E500                    /* BOOKE e500 family */
-#define CONFIG_FSL_IFC                 /* Enable IFC Support */
-#define CONFIG_FSL_CAAM                        /* Enable SEC/CAAM */
 #define CONFIG_SYS_HAS_SERDES          /* common SERDES init code */
 
-#define CONFIG_PCI                     /* Enable PCI/PCIE */
 #ifdef CONFIG_PCI
-#define CONFIG_PCIE1                   /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE1                   /* PCIE controller 1 (slot 1) */
 #define CONFIG_FSL_PCI_INIT            /* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_FSL_PCIE_RESET          /* need PCIe reset errata */
@@ -100,7 +79,6 @@
 
 #define CONFIG_CMD_PCI
 
-
 /*
  * PCI Windows
  * Memory space is mapped 1-1, but I/O space must start from 0.
@@ -116,13 +94,9 @@
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xfffc00000ull
 
-#define CONFIG_PCI_PNP                 /* do pci plug-and-play */
-
 #define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
 #endif
 
-#define CONFIG_FSL_LAW                 /* Use common FSL init code */
 #define CONFIG_TSEC_ENET
 #define CONFIG_ENV_OVERWRITE
 
@@ -149,7 +123,6 @@
 #define CONFIG_PANIC_HANG
 
 /* DDR Setup */
-#define CONFIG_SYS_FSL_DDR3
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM         0
 #define SPD_EEPROM_ADDRESS             0x50
@@ -176,10 +149,6 @@
                        (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
 #define CONFIG_SYS_PLATFORM_SRAM_SIZE  (512 << 10)
 
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_NO_FLASH
-#endif
-
 /*
  * IFC Definitions
  */
@@ -231,7 +200,6 @@
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
 
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BLOCK_SIZE     (1024 * 1024)
 
 /* 8Bit NAND Flash - K9F1G08U0B */
@@ -385,17 +353,12 @@
 #define CONFIG_NS16550_MIN_FUNCTIONS
 #endif
 
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
 #define CONFIG_SYS_BAUDRATE_TABLE      \
        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED       400000
@@ -407,15 +370,11 @@
 
 /* I2C EEPROM */
 /* enable read and write access to EEPROM */
-#define CONFIG_CMD_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 
-#define CONFIG_CMD_I2C
-
 /* eSPI - Enhanced SPI */
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED                10000000
 #define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
 
@@ -444,7 +403,6 @@
  */
 #if defined(CONFIG_SYS_RAMBOOT)
 #if defined(CONFIG_RAMBOOT_SPIFLASH)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SPI_BUS     0
 #define CONFIG_ENV_SPI_CS      0
 #define CONFIG_ENV_SPI_MAX_HZ  10000000
@@ -454,7 +412,6 @@
 #define CONFIG_ENV_SIZE                0x2000
 #endif
 #elif defined(CONFIG_NAND)
-#define CONFIG_ENV_IS_IN_NAND
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_ENV_SIZE                0x2000
 #define CONFIG_ENV_ADDR                (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
@@ -464,7 +421,6 @@
 #endif
 #define CONFIG_ENV_OFFSET      CONFIG_SYS_NAND_BLOCK_SIZE
 #else
-#define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE                0x2000
 #define CONFIG_ENV_SECT_SIZE   0x20000
@@ -476,18 +432,8 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
 /*
  * Miscellaneous configurable options
  */
@@ -526,10 +472,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR                1000000
 
-#define CONFIG_BOOTDELAY       -1      /* -1 disables auto-boot */
-
-#define CONFIG_BAUDRATE                115200
-
 #define CONFIG_DEF_HWCONFIG    fsl_ddr:ecc=on
 
 #define        CONFIG_EXTRA_ENV_SETTINGS                               \
@@ -540,7 +482,7 @@
        "consoledev=ttyS0\0"                            \
        "ramdiskaddr=2000000\0"                         \
        "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
-       "fdtaddr=c00000\0"                              \
+       "fdtaddr=1e00000\0"                             \
        "fdtfile=name/of/device-tree.dtb\0"                     \
        "othbootargs=ramdisk_size=600000\0"             \