#define CONFIG_AMIGAONEG3SE 1
-#define CONFIG_BOARD_PRE_INIT 1
+#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R 1
#define CONFIG_VERY_BIG_RAM 1
/* Size in bytes reserved for initial data
*/
/* HJF: used to be 0x400000 */
-#define CFG_INIT_RAM_ADDR 0x40000000
+#define CFG_INIT_RAM_ADDR 0x40000000
#define CFG_INIT_RAM_END 0x8000
#define CFG_GBL_DATA_SIZE 128
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_IBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
/* HJF:
-#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW)
+#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW)
#define CFG_IBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW )
+#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW )
#define CFG_DBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP)
*/
#define CFG_DBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CFG_DBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
/* This used to be commented out */
-#define CFG_IBAT2L CFG_DBAT2L
+#define CFG_IBAT2L CFG_DBAT2L
/* This here too */
-#define CFG_IBAT2U CFG_DBAT2U
+#define CFG_IBAT2U CFG_DBAT2U
/* I/O and PCI memory at 0xf0000000