* (easy to change)
*/
-#undef DEBUG
-
#define CONFIG_405 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_FLASH_USE_BUFFER_WRITE
-#ifdef CFG_ENV_IS_IN_NVRAM
+#ifdef CONFIG_ENV_IS_IN_NVRAM
#undef CFG_ENV_IS_IN_FLASH
#else
#ifdef CFG_ENV_IS_IN_FLASH
-#undef CFG_ENV_IS_IN_NVRAM
+#undef CONFIG_ENV_IS_IN_NVRAM
#endif
#endif
#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
-#ifdef CFG_ENV_IS_IN_NVRAM
+#ifdef CONFIG_ENV_IS_IN_NVRAM
#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
#define CFG_ENV_ADDR \
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
/*
* Init Memory Controller: