common: Move pcie_setup_hoses() to PPC header

[platform/kernel/u-boot.git] / include / common.h

diff --git a/include/common.h b/include/common.h
index dd8b25f..6dd0d2f 100644 (file)
--- a/include/common.h
+++ b/include/common.h
@@ -30,9 +30,6 @@ typedef volatile unsigned char        vu_char;
 #include <asm/ptrace.h>
 #include <stdarg.h>
 #include <linux/kernel.h>
-#if defined(CONFIG_PCI) && defined(CONFIG_4xx)
-#include <pci.h>
-#endif
 #if defined(CONFIG_8xx)
 #include <asm/8xx_immap.h>
 #if defined(CONFIG_MPC859)     || defined(CONFIG_MPC859T)      || \
@@ -203,14 +200,28 @@ typedef void (interrupt_handler_t)(void *);
  */
 int dram_init(void);
 
+/**
+ * dram_init_banksize() - Set up DRAM bank sizes
+ *
+ * This can be implemented by boards to set up the DRAM bank information in
+ * gd->bd->bi_dram(). It is called just before relocation, after dram_init()
+ * is called.
+ *
+ * If this is not provided, a default implementation will try to set up a
+ * single bank. It will do this if CONFIG_NR_DRAM_BANKS and
+ * CONFIG_SYS_SDRAM_BASE are set. The bank will have a start address of
+ * CONFIG_SYS_SDRAM_BASE and the size will be determined by a call to
+ * get_effective_memsize().
+ *
+ * @return 0 if OK, -ve on error
+ */
+int dram_init_banksize(void);
+
 void   hang            (void) __attribute__ ((noreturn));
 
 int    timer_init(void);
 int    cpu_init(void);
 
-/* */
-int initdram(void);
-
 #include <display_options.h>
 
 /* common/main.c */
@@ -285,6 +296,13 @@ int print_cpuinfo(void);
 int update_flash_size(int flash_size);
 int arch_early_init_r(void);
 
+/*
+ * setup_board_extra() - Fill in extra details in the bd_t structure
+ *
+ * @return 0 if OK, -ve on error
+ */
+int setup_board_extra(void);
+
 /**
  * arch_fsp_init() - perform firmware support package init
  *
@@ -438,25 +456,6 @@ int get_env_id (void);
 void   pci_init      (void);
 void   pci_init_board(void);
 
-#if defined(CONFIG_PCI) && defined(CONFIG_4xx)
-    int           pci_pre_init        (struct pci_controller *);
-    int           is_pci_host         (struct pci_controller *);
-#endif
-
-#if defined(CONFIG_PCI) && (defined(CONFIG_440) || defined(CONFIG_405EX))
-#   if defined(CONFIG_SYS_PCI_TARGET_INIT)
-       void    pci_target_init      (struct pci_controller *);
-#   endif
-#   if defined(CONFIG_SYS_PCI_MASTER_INIT)
-       void    pci_master_init      (struct pci_controller *);
-#   endif
-#if defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_405EX)
-   void pcie_setup_hoses(int busno);
-#endif
-#endif
-
 int    misc_init_f   (void);
 int    misc_init_r   (void);
 
@@ -478,9 +477,19 @@ void       reset_phy     (void);
 void   fdc_hw_init   (void);
 
 /* $(BOARD)/eeprom.c */
+#ifdef CONFIG_CMD_EEPROM
 void eeprom_init  (int bus);
 int  eeprom_read  (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
 int  eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
+#else
+/*
+ * Some EEPROM code is depecated because it used the legacy I2C interface. Add
+ * some macros here so we don't have to touch every one of those uses
+ */
+#define eeprom_init(bus)
+#define eeprom_read(dev_addr, offset, buffer, cnt) ((void)-ENOSYS)
+#define eeprom_write(dev_addr, offset, buffer, cnt) ((void)-ENOSYS)
+#endif
 
 /*
  * Set this up regardless of board