Merge: Add support for AMCC 440SPe CPU based eval board (Yucca).

[platform/kernel/u-boot.git] / include / asm-ppc / processor.h

diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 551da35..ea5b0d2 100644 (file)
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -310,10 +310,10 @@
 #define SPRN_TBHU      0x3CC   /* Time Base High User-mode */
 #define SPRN_TBLO      0x3DD   /* Time Base Low */
 #define SPRN_TBLU      0x3CD   /* Time Base Low User-mode */
-#define SPRN_TBRL      0x10D   /* Time Base Read Lower Register */
-#define SPRN_TBRU      0x10C   /* Time Base Read Upper Register */
-#define SPRN_TBWL      0x11D   /* Time Base Write Lower Register */
-#define SPRN_TBWU      0x11C   /* Time Base Write Upper Register */
+#define SPRN_TBRL      0x10C   /* Time Base Read Lower Register */
+#define SPRN_TBRU      0x10D   /* Time Base Read Upper Register */
+#define SPRN_TBWL      0x11C   /* Time Base Write Lower Register */
+#define SPRN_TBWU      0x11D   /* Time Base Write Upper Register */
 #ifndef CONFIG_BOOKE
 #define SPRN_TCR       0x3DA   /* Timer Control Register */
 #else
@@ -725,12 +725,18 @@
 #define PVR_440GP_RC   0x40120481
 #define PVR_440EP_RA   0x42221850
 #define PVR_440EP_RB   0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
+#define PVR_440EP_RC   0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
 #define PVR_440GR_RA   0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
+#define PVR_440GR_RB   0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
 #define PVR_440GX_RA   0x51B21850
 #define PVR_440GX_RB   0x51B21851
 #define PVR_440GX_RC   0x51B21892
 #define PVR_440GX_RF   0x51B21894
 #define PVR_405EP_RB   0x51210950
+#define PVR_440SP_RA   0x53221850
+#define PVR_440SP_RB   0x53221891
+#define PVR_440SPe_RA  0x53421890
+#define PVR_440SPe_RB  0x53521891
 #define PVR_601                0x00010000
 #define PVR_602                0x00050000
 #define PVR_603                0x00030000