Replace "#include <asm-$ARCH/$FILE>" with "#include <asm/$FILE>"

[platform/kernel/u-boot.git] / include / asm-ppc / processor.h

diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index d009957..9ec319a 100644 (file)
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -265,6 +265,7 @@
 #define          HID1_RFXE     (1<<17)         /* Read Fault Exception Enable */
 #define          HID1_ASTME    (1<<13)         /* Address bus streaming mode */
 #define          HID1_ABE      (1<<12)         /* Address broadcast enable */
+#define          HID1_MBDD     (1<<6)          /* optimized sync instruction */
 #define SPRN_IABR      0x3F2   /* Instruction Address Breakpoint Register */
 #ifndef CONFIG_BOOKE
 #define SPRN_IAC1      0x3F4   /* Instruction Address Compare 1 */
@@ -485,10 +486,12 @@
 #define SPRN_L2CFG0    0x207   /* L2 Cache Configuration Register 0 */
 #define SPRN_L1CSR0    0x3f2   /* L1 Data Cache Control and Status Register 0 */
 #define   L1CSR0_CPE           0x00010000      /* Data Cache Parity Enable */
+#define   L1CSR0_DCLFR         0x00000100      /* D-Cache Lock Flash Reset */
 #define   L1CSR0_DCFI          0x00000002      /* Data Cache Flash Invalidate */
 #define   L1CSR0_DCE           0x00000001      /* Data Cache Enable */
 #define SPRN_L1CSR1    0x3f3   /* L1 Instruction Cache Control and Status Register 1 */
 #define   L1CSR1_CPE           0x00010000      /* Instruction Cache Parity Enable */
+#define   L1CSR1_ICLFR         0x00000100      /* I-Cache Lock Flash Reset */
 #define   L1CSR1_ICFI          0x00000002      /* Instruction Cache Flash Invalidate */
 #define   L1CSR1_ICE           0x00000001      /* Instruction Cache Enable */
 #define SPRN_L1CSR2    0x25e   /* L1 Data Cache Control and Status Register 2 */
@@ -531,6 +534,9 @@
 #define SPRN_MCSRR0    0x23a   /* Machine Check Save and Restore Register 0 */
 #define SPRN_MCSRR1    0x23b   /* Machine Check Save and Restore Register 1 */
 #define SPRN_BUCSR     0x3f5   /* Branch Control and Status Register */
+#define          BUCSR_BBFI    0x00000200      /* Branch buffer flash invalidate */
+#define          BUCSR_BPEN    0x00000001      /* Branch prediction enable */
+#define   BUCSR_ENABLE (BUCSR_BBFI|BUCSR_BPEN)
 #define SPRN_BBEAR     0x201   /* Branch Buffer Entry Address Register */
 #define SPRN_BBTAR     0x202   /* Branch Buffer Target Address Register */
 #define SPRN_PID1      0x279   /* Process ID Register 1 */
@@ -863,14 +869,16 @@
 #define PVR_405EP_RA   0x51210950
 #define PVR_405GPR_RB  0x50910951
 #define PVR_405EZ_RA   0x41511460
-#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A/B with Security */
 #define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */
 #define PVR_405EX1_RA  0x12911477 /* 405EX rev A/B with Security */
-#define PVR_405EX2_RA  0x12911475 /* 405EX rev A/B without Security */
 #define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */
 #define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */
 #define PVR_405EX1_RC  0x1291147F /* 405EX rev C with Security */
 #define PVR_405EX2_RC  0x1291147D /* 405EX rev C without Security */
+#define PVR_405EXR1_RD 0x12911472 /* 405EXr rev D with Security */
+#define PVR_405EXR2_RD 0x12911470 /* 405EXr rev D without Security */
+#define PVR_405EX1_RD  0x12911475 /* 405EX rev D with Security */
+#define PVR_405EX2_RD  0x12911473 /* 405EX rev D without Security */
 #define PVR_440GP_RB   0x40120440
 #define PVR_440GP_RC   0x40120481
 #define PVR_440EP_RA   0x42221850
@@ -990,6 +998,9 @@
 #endif
 #endif
 
+#define IS_SVR_REV(svr, maj, min) \
+       ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
+
 /*
  * SVR_SOC_VER() Version Values
  */
@@ -1025,8 +1036,16 @@
 #define SVR_8572_E     0x80E800
 #define SVR_P1011      0x80E500
 #define SVR_P1011_E    0x80ED00
+#define SVR_P1012      0x80E501
+#define SVR_P1012_E    0x80ED01
+#define SVR_P1013      0x80E700
+#define SVR_P1013_E    0x80EF00
 #define SVR_P1020      0x80E400
 #define SVR_P1020_E    0x80EC00
+#define SVR_P1021      0x80E401
+#define SVR_P1021_E    0x80EC01
+#define SVR_P1022      0x80E600
+#define SVR_P1022_E    0x80EE00
 #define SVR_P2010      0x80E300
 #define SVR_P2010_E    0x80EB00
 #define SVR_P2020      0x80E200