typedef struct law512x {
u32 bar; /* Base Addr Register */
u32 ar; /* Attributes Register */
-} law521x_t;
+} law512x_t;
/*
* System configuration registers
u32 lpcs6aw; /* LP CS6 Access Window */
u32 lpcs7aw; /* LP CS7 Access Window */
u8 res1[0x1c];
- law521x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */
+ law512x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */
u8 res2[0x28];
- law521x_t ddrlaw; /* DDR Local Access Window */
+ law512x_t ddrlaw; /* DDR Local Access Window */
u8 res3[0x18];
u32 mbxbar; /* MBX Base Address */
u32 srambar; /* SRAM Base Address */
* PCI Software Configuration Registers
*/
typedef struct pciconf512x {
- u8 fixme[0x80];
+ u32 config_address;
+ u32 config_data;
+ u32 int_ack;
+ u8 res[116];
} pciconf512x_t;
/*
+ * PCI Outbound Translation Register
+ */
+typedef struct pci_outbound_window {
+ u32 potar;
+ u8 res0[4];
+ u32 pobar;
+ u8 res1[4];
+ u32 pocmr;
+ u8 res2[4];
+} pot512x_t;
+
+/*
* Sequencer
*/
typedef struct ios512x {
- u8 fixme[0x100];
+ pot512x_t pot[6];
+ u8 res0[0x60];
+ u32 pmcr;
+ u8 res1[4];
+ u32 dtcr;
+ u8 res2[4];
} ios512x_t;
/*
* PCI Controller
*/
typedef struct pcictrl512x {
- u8 fixme[0x100];
+ u32 esr;
+ u32 ecdr;
+ u32 eer;
+ u32 eatcr;
+ u32 eacr;
+ u32 eeacr;
+ u32 edlcr;
+ u32 edhcr;
+ u32 gcr;
+ u32 ecr;
+ u32 gsr;
+ u8 res0[12];
+ u32 pitar2;
+ u8 res1[4];
+ u32 pibar2;
+ u32 piebar2;
+ u32 piwar2;
+ u8 res2[4];
+ u32 pitar1;
+ u8 res3[4];
+ u32 pibar1;
+ u32 piebar1;
+ u32 piwar1;
+ u8 res4[4];
+ u32 pitar0;
+ u8 res5[4];
+ u32 pibar0;
+ u8 res6[4];
+ u32 piwar0;
+ u8 res7[132];
} pcictrl512x_t;
* IIM
*/
typedef struct iim512x {
- u8 fixme[0x1000];
+ u32 stat; /* IIM status register */
+ u32 statm; /* IIM status IRQ mask */
+ u32 err; /* IIM errors register */
+ u32 emask; /* IIM error IRQ mask */
+ u32 fctl; /* IIM fuse control register */
+ u32 ua; /* IIM upper address register */
+ u32 la; /* IIM lower address register */
+ u32 sdat; /* IIM explicit sense data */
+ u8 res0[0x08];
+ u32 prg_p; /* IIM program protection register */
+ u8 res1[0x10];
+ u32 divide; /* IIM divide factor register */
+ u8 res2[0x7c0];
+ u32 fbac0; /* IIM fuse bank 0 prot (for Freescale use) */
+ u32 fb0w0[0x1f]; /* IIM fuse bank 0 data (for Freescale use) */
+ u8 res3[0x380];
+ u32 fbac1; /* IIM fuse bank 1 protection */
+ u32 fb1w1[0x01f]; /* IIM fuse bank 1 data */
+ u8 res4[0x380];
} iim512x_t;
/*
* PATA
*/
typedef struct pata512x {
- u8 fixme[0x100];
+ /* LOCAL Registers */
+ u32 pata_time1; /* Time register 1: PIO and tx timing parameter */
+ u32 pata_time2; /* Time register 2: PIO timing parameter */
+ u32 pata_time3; /* Time register 3: PIO and MDMA timing parameter */
+ u32 pata_time4; /* Time register 4: MDMA and UDMA timing parameter */
+ u32 pata_time5; /* Time register 5: UDMA timing parameter */
+ u32 pata_time6; /* Time register 6: UDMA timing parameter */
+ u32 pata_fifo_data32; /* 32bit wide dataport to/from FIFO */
+ u32 pata_fifo_data16; /* 16bit wide dataport to/from FIFO */
+ u32 pata_fifo_fill; /* FIFO filling in halfwords (READONLY)*/
+ u32 pata_ata_control; /* ATA Interface control register */
+ u32 pata_irq_pending; /* Interrupt pending register (READONLY) */
+ u32 pata_irq_enable; /* Interrupt enable register */
+ u32 pata_irq_clear; /* Interrupt clear register (WRITEONLY)*/
+ u32 pata_fifo_alarm; /* fifo alarm threshold */
+ u32 res1[0x1A];
+ /* DRIVE Registers */
+ u32 pata_drive_data; /* drive data register*/
+ u32 pata_drive_features;/* drive features register */
+ u32 pata_drive_sectcnt; /* drive sector count register */
+ u32 pata_drive_sectnum; /* drive sector number register */
+ u32 pata_drive_cyllow; /* drive cylinder low register */
+ u32 pata_drive_cylhigh; /* drive cylinder high register */
+ u32 pata_drive_dev_head;/* drive device head register */
+ u32 pata_drive_command; /* write = drive command, read = drive status reg */
+ u32 res2[0x06];
+ u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */
+ u32 res3[0x09];
} pata512x_t;
/*