Replace "#include <asm-$ARCH/$FILE>" with "#include <asm/$FILE>"

[platform/kernel/u-boot.git] / include / asm-ppc / fsl_lbc.h

diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index e492c62..5723de6 100644 (file)
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -28,6 +28,8 @@
 
 #define BR_BA                          0xFFFF8000
 #define BR_BA_SHIFT                    15
+#define BR_XBA                         0x00006000
+#define BR_XBA_SHIFT                   13
 #define BR_PS                          0x00001800
 #define BR_PS_SHIFT                    11
 #define BR_PS_8                                0x00000800      /* Port Size 8 bit */
@@ -52,7 +54,7 @@
 #define BR_MS_UPMA                     0x00000080      /* UPMA */
 #define BR_MS_UPMB                     0x000000A0      /* UPMB */
 #define BR_MS_UPMC                     0x000000C0      /* UPMC */
-#if !defined(CONFIG_MPC834X)
+#if !defined(CONFIG_MPC834x)
 #define BR_ATOM                                0x0000000C
 #define BR_ATOM_SHIFT                  2
 #endif
@@ -63,14 +65,14 @@
 #define UPMB                   1
 #define UPMC                   2
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 #define BR_RES                         ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
 #else
 #define BR_RES                         ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
 #endif
 
 /* Convert an address into the right format for the BR registers */
-#ifdef CONFIG_PHYS_64BIT
+#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
 #define BR_PHYS_ADDR(x)        ((unsigned long)((x & 0x0ffff8000ULL) | \
                                         ((x & 0x300000000ULL) >> 19)))
 #else
@@ -90,6 +92,8 @@
 
 #define OR_GPCM_AM                     0xFFFF8000
 #define OR_GPCM_AM_SHIFT               15
+#define OR_GPCM_XAM                    0x00006000
+#define OR_GPCM_XAM_SHIFT              13
 #define OR_GPCM_BCTLD                  0x00001000
 #define OR_GPCM_BCTLD_SHIFT            12
 #define OR_GPCM_CSNT                   0x00000800
@@ -132,6 +136,8 @@
 
 #define OR_FCM_AM                      0xFFFF8000
 #define OR_FCM_AM_SHIFT                                15
+#define OR_FCM_XAM                     0x00006000
+#define OR_FCM_XAM_SHIFT               13
 #define OR_FCM_BCTLD                   0x00001000
 #define OR_FCM_BCTLD_SHIFT                     12
 #define OR_FCM_PGS                     0x00000400
@@ -305,9 +311,21 @@
  */
 #define LCRR_CLKDIV                    0x0000001F
 #define LCRR_CLKDIV_SHIFT              0
+#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \
+    defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \
+    defined(CONFIG_MPC8560)
 #define LCRR_CLKDIV_2                  0x00000002
 #define LCRR_CLKDIV_4                  0x00000004
 #define LCRR_CLKDIV_8                  0x00000008
+#elif defined(CONFIG_FSL_CORENET)
+#define LCRR_CLKDIV_8                  0x00000002
+#define LCRR_CLKDIV_16                 0x00000004
+#define LCRR_CLKDIV_32                 0x00000008
+#else
+#define LCRR_CLKDIV_4                  0x00000002
+#define LCRR_CLKDIV_8                  0x00000004
+#define LCRR_CLKDIV_16                 0x00000008
+#endif
 
 /* LTEDR - Transfer Error Check Disable Register
  */
@@ -391,6 +409,33 @@
 #define FPAR_LP_CI             0x000007FF
 #define FPAR_LP_CI_SHIFT       0
 
+/* LSDMR - SDRAM Machine Mode Register
+ */
+#define LSDMR_RFEN     (1 << (31 -  1))
+#define LSDMR_BSMA1516 (3 << (31 - 10))
+#define LSDMR_BSMA1617 (4 << (31 - 10))
+#define LSDMR_RFCR5    (3 << (31 - 16))
+#define LSDMR_RFCR16   (7 << (31 - 16))
+#define LSDMR_PRETOACT3 (3 << (31 - 19))
+#define LSDMR_PRETOACT7        (7 << (31 - 19))
+#define LSDMR_ACTTORW3 (3 << (31 - 22))
+#define LSDMR_ACTTORW7 (7 << (31 - 22))
+#define LSDMR_ACTTORW6 (6 << (31 - 22))
+#define LSDMR_BL8      (1 << (31 - 23))
+#define LSDMR_WRC2     (2 << (31 - 27))
+#define LSDMR_WRC4     (0 << (31 - 27))
+#define LSDMR_BUFCMD   (1 << (31 - 29))
+#define LSDMR_CL3      (3 << (31 - 31))
+
+#define LSDMR_OP_NORMAL        (0 << (31 - 4))
+#define LSDMR_OP_ARFRSH        (1 << (31 - 4))
+#define LSDMR_OP_SRFRSH        (2 << (31 - 4))
+#define LSDMR_OP_MRW   (3 << (31 - 4))
+#define LSDMR_OP_PRECH (4 << (31 - 4))
+#define LSDMR_OP_PCHALL        (5 << (31 - 4))
+#define LSDMR_OP_ACTBNK        (6 << (31 - 4))
+#define LSDMR_OP_RWINV (7 << (31 - 4))
+
 /* LTESR - Transfer Error Status Register
  */
 #define LTESR_BM               0x80000000