* Modified for further R[236]000 support by Paul M. Antoine, 1996.
* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
+ * Copyright (C) 2003 Maciej W. Rozycki
*/
#ifndef _ASM_MIPSREGS_H
#define _ASM_MIPSREGS_H
#define CP0_IWATCH $18
#define CP0_DWATCH $19
-/*
+/*
* Coprocessor 0 Set 1 register names
*/
#define CP0_S1_DERRADDR0 $26
*/
#define read_32bit_cp0_register(source) \
({ int __res; \
- __asm__ __volatile__( \
+ __asm__ __volatile__( \
".set\tpush\n\t" \
".set\treorder\n\t" \
- "mfc0\t%0,"STR(source)"\n\t" \
+ "mfc0\t%0,"STR(source)"\n\t" \
".set\tpop" \
- : "=r" (__res)); \
- __res;})
+ : "=r" (__res)); \
+ __res;})
#define read_32bit_cp0_set1_register(source) \
({ int __res; \
- __asm__ __volatile__( \
+ __asm__ __volatile__( \
".set\tpush\n\t" \
".set\treorder\n\t" \
- "cfc0\t%0,"STR(source)"\n\t" \
+ "cfc0\t%0,"STR(source)"\n\t" \
".set\tpop" \
- : "=r" (__res)); \
- __res;})
+ : "=r" (__res)); \
+ __res;})
/*
* For now use this only with interrupts disabled!
*/
#define read_64bit_cp0_register(source) \
({ int __res; \
- __asm__ __volatile__( \
- ".set\tmips3\n\t" \
- "dmfc0\t%0,"STR(source)"\n\t" \
- ".set\tmips0" \
- : "=r" (__res)); \
- __res;})
+ __asm__ __volatile__( \
+ ".set\tmips3\n\t" \
+ "dmfc0\t%0,"STR(source)"\n\t" \
+ ".set\tmips0" \
+ : "=r" (__res)); \
+ __res;})
#define write_32bit_cp0_register(register,value) \
- __asm__ __volatile__( \
- "mtc0\t%0,"STR(register)"\n\t" \
+ __asm__ __volatile__( \
+ "mtc0\t%0,"STR(register)"\n\t" \
"nop" \
- : : "r" (value));
+ : : "r" (value));
#define write_32bit_cp0_set1_register(register,value) \
- __asm__ __volatile__( \
- "ctc0\t%0,"STR(register)"\n\t" \
+ __asm__ __volatile__( \
+ "ctc0\t%0,"STR(register)"\n\t" \
"nop" \
- : : "r" (value));
+ : : "r" (value));
#define write_64bit_cp0_register(register,value) \
- __asm__ __volatile__( \
- ".set\tmips3\n\t" \
- "dmtc0\t%0,"STR(register)"\n\t" \
- ".set\tmips0" \
- : : "r" (value))
-
-/*
- * This should be changed when we get a compiler that support the MIPS32 ISA.
+ __asm__ __volatile__( \
+ ".set\tmips3\n\t" \
+ "dmtc0\t%0,"STR(register)"\n\t" \
+ ".set\tmips0" \
+ : : "r" (value))
+
+/*
+ * This should be changed when we get a compiler that support the MIPS32 ISA.
*/
#define read_mips32_cp0_config1() \
({ int __res; \
- __asm__ __volatile__( \
+ __asm__ __volatile__( \
".set\tnoreorder\n\t" \
".set\tnoat\n\t" \
- ".word\t0x40018001\n\t" \
+ ".word\t0x40018001\n\t" \
"move\t%0,$1\n\t" \
".set\tat\n\t" \
".set\treorder" \
:"=r" (__res)); \
- __res;})
+ __res;})
+
+#define tlb_write_indexed() \
+ __asm__ __volatile__( \
+ ".set noreorder\n\t" \
+ "tlbwi\n\t" \
+".set reorder")
/*
* R4x00 interrupt enable / cause bits
set_cp0_##name(unsigned int set) \
{ \
unsigned int res; \
- \
+ \
res = read_32bit_cp0_register(register); \
res |= set; \
- write_32bit_cp0_register(register, res); \
- \
+ write_32bit_cp0_register(register, res); \
+ \
return res; \
} \
\
clear_cp0_##name(unsigned int clear) \
{ \
unsigned int res; \
- \
+ \
res = read_32bit_cp0_register(register); \
res &= ~clear; \
write_32bit_cp0_register(register, res); \
- \
+ \
return res; \
} \
\
change_cp0_##name(unsigned int change, unsigned int new) \
{ \
unsigned int res; \
- \
+ \
res = read_32bit_cp0_register(register); \
res &= ~change; \
res |= (new & change); \
if(change) \
write_32bit_cp0_register(register, res); \
- \
+ \
return res; \
}
# define KSU_KERNEL 0x00000000
#define ST0_UX 0x00000020
#define ST0_SX 0x00000040
-#define ST0_KX 0x00000080
+#define ST0_KX 0x00000080
#define ST0_DE 0x00010000
#define ST0_CE 0x00020000
*/
#define TX39_CONF_ICS_SHIFT 19
#define TX39_CONF_ICS_MASK 0x00380000
-#define TX39_CONF_ICS_1KB 0x00000000
-#define TX39_CONF_ICS_2KB 0x00080000
-#define TX39_CONF_ICS_4KB 0x00100000
-#define TX39_CONF_ICS_8KB 0x00180000
-#define TX39_CONF_ICS_16KB 0x00200000
+#define TX39_CONF_ICS_1KB 0x00000000
+#define TX39_CONF_ICS_2KB 0x00080000
+#define TX39_CONF_ICS_4KB 0x00100000
+#define TX39_CONF_ICS_8KB 0x00180000
+#define TX39_CONF_ICS_16KB 0x00200000
#define TX39_CONF_DCS_SHIFT 16
#define TX39_CONF_DCS_MASK 0x00070000
-#define TX39_CONF_DCS_1KB 0x00000000
-#define TX39_CONF_DCS_2KB 0x00010000
-#define TX39_CONF_DCS_4KB 0x00020000
-#define TX39_CONF_DCS_8KB 0x00030000
-#define TX39_CONF_DCS_16KB 0x00040000
-
-#define TX39_CONF_CWFON 0x00004000
-#define TX39_CONF_WBON 0x00002000
+#define TX39_CONF_DCS_1KB 0x00000000
+#define TX39_CONF_DCS_2KB 0x00010000
+#define TX39_CONF_DCS_4KB 0x00020000
+#define TX39_CONF_DCS_8KB 0x00030000
+#define TX39_CONF_DCS_16KB 0x00040000
+
+#define TX39_CONF_CWFON 0x00004000
+#define TX39_CONF_WBON 0x00002000
#define TX39_CONF_RF_SHIFT 10
#define TX39_CONF_RF_MASK 0x00000c00
#define TX39_CONF_DOZE 0x00000200
projects / platform / kernel / u-boot.git / blobdiff