Merge git://www.denx.de/git/u-boot into uboot

[platform/kernel/u-boot.git] / include / asm-m68k / immap.h

diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h
index bf7b51b..916bf96 100644 (file)
--- a/include/asm-m68k/immap.h
+++ b/include/asm-m68k/immap.h
@@ -26,6 +26,69 @@
 #ifndef __IMMAP_H
 #define __IMMAP_H
 
+#ifdef CONFIG_M52277
+#include <asm/immap_5227x.h>
+#include <asm/m5227x.h>
+
+#define CFG_UART_BASE          (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
+
+#define CFG_MCFRTC_BASE                (MMAP_RTC)
+
+#ifdef CONFIG_LCD
+#define        CFG_LCD_BASE            (MMAP_LCD)
+#endif
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE                (MMAP_DTMR0)
+#define CFG_TMR_BASE           (MMAP_DTMR1)
+#define CFG_TMRPND_REG         (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
+#define CFG_TMRINTR_NO         (INT0_HI_DTMR1)
+#define CFG_TMRINTR_MASK       (INTC_IPRH_INT33)
+#define CFG_TMRINTR_PEND       (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI                (6)
+#define CFG_TIMER_PRESCALER    (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CFG_UDELAY_BASE                (MMAP_PIT0)
+#define CFG_PIT_BASE           (MMAP_PIT1)
+#define CFG_PIT_PRESCALE       (6)
+#endif
+
+#define CFG_INTR_BASE          (MMAP_INTC0)
+#define CFG_NUM_IRQS           (128)
+#endif                         /* CONFIG_M52277 */
+
+#ifdef CONFIG_M5235
+#include <asm/immap_5235.h>
+#include <asm/m5235.h>
+
+#define CFG_FEC0_IOBASE                (MMAP_FEC)
+#define CFG_UART_BASE          (MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE                (MMAP_DTMR0)
+#define CFG_TMR_BASE           (MMAP_DTMR3)
+#define CFG_TMRPND_REG         (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
+#define CFG_TMRINTR_NO         (INT0_LO_DTMR3)
+#define CFG_TMRINTR_MASK       (INTC_IPRL_INT22)
+#define CFG_TMRINTR_PEND       (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI                (0x1E)          /* Level must include inorder to work */
+#define CFG_TIMER_PRESCALER    (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CFG_UDELAY_BASE                (MMAP_PIT0)
+#define CFG_PIT_BASE           (MMAP_PIT1)
+#define CFG_PIT_PRESCALE       (6)
+#endif
+
+#define CFG_INTR_BASE          (MMAP_INTC0)
+#define CFG_NUM_IRQS           (128)
+#endif                         /* CONFIG_M5235 */
+
 #ifdef CONFIG_M5249
 #include <asm/immap_5249.h>
 #include <asm/m5249.h>
@@ -140,7 +203,7 @@
 #endif
 #endif                         /* CONFIG_M5282 */
 
-#ifdef CONFIG_M5329
+#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
 #include <asm/immap_5329.h>
 #include <asm/m5329.h>
 
@@ -168,6 +231,139 @@
 
 #define CFG_INTR_BASE          (MMAP_INTC0)
 #define CFG_NUM_IRQS           (128)
-#endif                         /* CONFIG_M5329 */
+#endif                         /* CONFIG_M5329 && CONFIG_M5373 */
+
+#ifdef CONFIG_M54455
+#include <asm/immap_5445x.h>
+#include <asm/m5445x.h>
+
+#define CFG_FEC0_IOBASE                (MMAP_FEC0)
+#define CFG_FEC1_IOBASE                (MMAP_FEC1)
+
+#define CFG_UART_BASE          (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
+
+#define CFG_MCFRTC_BASE                (MMAP_RTC)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE                (MMAP_DTMR0)
+#define CFG_TMR_BASE           (MMAP_DTMR1)
+#define CFG_TMRPND_REG         (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
+#define CFG_TMRINTR_NO         (INT0_HI_DTMR1)
+#define CFG_TMRINTR_MASK       (INTC_IPRH_INT33)
+#define CFG_TMRINTR_PEND       (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI                (6)
+#define CFG_TIMER_PRESCALER    (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CFG_UDELAY_BASE                (MMAP_PIT0)
+#define CFG_PIT_BASE           (MMAP_PIT1)
+#define CFG_PIT_PRESCALE       (6)
+#endif
+
+#define CFG_INTR_BASE          (MMAP_INTC0)
+#define CFG_NUM_IRQS           (128)
+
+#ifdef CONFIG_PCI
+#define CFG_PCI_BAR0           (CFG_MBAR)
+#define CFG_PCI_BAR5           (CFG_SDRAM_BASE)
+#define CFG_PCI_TBATR0         (CFG_MBAR)
+#define CFG_PCI_TBATR5         (CFG_SDRAM_BASE)
+#endif
+#endif                         /* CONFIG_M54455 */
+
+#ifdef CONFIG_M547x
+#include <asm/immap_547x_8x.h>
+#include <asm/m547x_8x.h>
+
+#ifdef CONFIG_FSLDMAFEC
+#define CFG_FEC0_IOBASE                (MMAP_FEC0)
+#define CFG_FEC1_IOBASE                (MMAP_FEC1)
+
+#define FEC0_RX_TASK           0
+#define FEC0_TX_TASK           1
+#define FEC0_RX_PRIORITY       6
+#define FEC0_TX_PRIORITY       7
+#define FEC0_RX_INIT           16
+#define FEC0_TX_INIT           17
+#define FEC1_RX_TASK           2
+#define FEC1_TX_TASK           3
+#define FEC1_RX_PRIORITY       6
+#define FEC1_TX_PRIORITY       7
+#define FEC1_RX_INIT           30
+#define FEC1_TX_INIT           31
+#endif
+
+#define CFG_UART_BASE          (MMAP_UART0 + (CFG_UART_PORT * 0x100))
+
+#ifdef CONFIG_SLTTMR
+#define CFG_UDELAY_BASE                (MMAP_SLT1)
+#define CFG_TMR_BASE           (MMAP_SLT0)
+#define CFG_TMRPND_REG         (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
+#define CFG_TMRINTR_NO         (INT0_HI_SLT0)
+#define CFG_TMRINTR_MASK       (INTC_IPRH_INT54)
+#define CFG_TMRINTR_PEND       (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI                (0x1E)
+#define CFG_TIMER_PRESCALER    (gd->bus_clk / 1000000)
+#endif
+
+#define CFG_INTR_BASE          (MMAP_INTC0)
+#define CFG_NUM_IRQS           (128)
+
+#ifdef CONFIG_PCI
+#define CFG_PCI_BAR0           (0x40000000)
+#define CFG_PCI_BAR1           (CFG_SDRAM_BASE)
+#define CFG_PCI_TBATR0         (CFG_MBAR)
+#define CFG_PCI_TBATR1         (CFG_SDRAM_BASE)
+#endif
+#endif                         /* CONFIG_M547x */
+
+#ifdef CONFIG_M548x
+#include <asm/immap_547x_8x.h>
+#include <asm/m547x_8x.h>
+
+#ifdef CONFIG_FSLDMAFEC
+#define CFG_FEC0_IOBASE                (MMAP_FEC0)
+#define CFG_FEC1_IOBASE                (MMAP_FEC1)
+
+#define FEC0_RX_TASK           0
+#define FEC0_TX_TASK           1
+#define FEC0_RX_PRIORITY       6
+#define FEC0_TX_PRIORITY       7
+#define FEC0_RX_INIT           16
+#define FEC0_TX_INIT           17
+#define FEC1_RX_TASK           2
+#define FEC1_TX_TASK           3
+#define FEC1_RX_PRIORITY       6
+#define FEC1_TX_PRIORITY       7
+#define FEC1_RX_INIT           30
+#define FEC1_TX_INIT           31
+#endif
+
+#define CFG_UART_BASE          (MMAP_UART0 + (CFG_UART_PORT * 0x100))
+
+/* Timer */
+#ifdef CONFIG_SLTTMR
+#define CFG_UDELAY_BASE                (MMAP_SLT1)
+#define CFG_TMR_BASE           (MMAP_SLT0)
+#define CFG_TMRPND_REG         (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
+#define CFG_TMRINTR_NO         (INT0_HI_SLT0)
+#define CFG_TMRINTR_MASK       (INTC_IPRH_INT54)
+#define CFG_TMRINTR_PEND       (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI                (0x1E)
+#define CFG_TIMER_PRESCALER    (gd->bus_clk / 1000000)
+#endif
+
+#define CFG_INTR_BASE          (MMAP_INTC0)
+#define CFG_NUM_IRQS           (128)
+
+#ifdef CONFIG_PCI
+#define CFG_PCI_BAR0           (CFG_MBAR)
+#define CFG_PCI_BAR1           (CFG_SDRAM_BASE)
+#define CFG_PCI_TBATR0         (CFG_MBAR)
+#define CFG_PCI_TBATR1         (CFG_SDRAM_BASE)
+#endif
+#endif                         /* CONFIG_M548x */
 
 #endif                         /* __IMMAP_H */