#ifndef __ASM_ARM_IO_H
#define __ASM_ARM_IO_H
+#ifdef __KERNEL__
+
#include <linux/types.h>
#include <asm/byteorder.h>
#include <asm/memory.h>
+#if 0 /* XXX###XXX */
#include <asm/arch/hardware.h>
+#endif /* XXX###XXX */
+
+static inline void sync(void)
+{
+}
/*
* Generic virtual read/write. Note that we don't support half-word
* to the architecture specific code.
*/
#define __arch_getb(a) (*(volatile unsigned char *)(a))
-#define __arch_getl(a) (*(volatile unsigned int *)(a))
+#define __arch_getw(a) (*(volatile unsigned short *)(a))
+#define __arch_getl(a) (*(volatile unsigned int *)(a))
#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
-#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
+#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
#define __raw_readw(a) __arch_getw(a)
#define __raw_readl(a) __arch_getl(a)
+#define writeb(v,a) __arch_putb(v,a)
+#define writew(v,a) __arch_putw(v,a)
+#define writel(v,a) __arch_putl(v,a)
+
+#define readb(a) __arch_getb(a)
+#define readw(a) __arch_getw(a)
+#define readl(a) __arch_getl(a)
+
/*
* The compiler seems to be incapable of optimising constants
* properly. Spell it out to the compiler in some cases.
/*
* Now, pick up the machine-defined IO definitions
*/
+#if 0 /* XXX###XXX */
#include <asm/arch/io.h>
+#endif /* XXX###XXX */
/*
- * IO definitions. We define {out,in,outs,ins}[bwl] if __io is defined
- * by the machine. Otherwise, these definitions are left for the machine
- * specific header files to pick up.
+ * IO port access primitives
+ * -------------------------
+ *
+ * The ARM doesn't have special IO access instructions; all IO is memory
+ * mapped. Note that these are defined to perform little endian accesses
+ * only. Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ * PCI: D0-D7 D8-D15 D16-D23 D24-D31
+ * ARM: D24-D31 D16-D23 D8-D15 D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
*
* Note that we prevent GCC re-ordering or caching values in expressions
* by introducing sequence points into the in*() definitions. Note that
* __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
*/
#ifdef __io
#define outb(v,p) __raw_writeb(v,__io(p))
-#define outw(v,p) __raw_writew(v,__io(p))
-#define outl(v,p) __raw_writel(v,__io(p))
+#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p))
+#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p))
-#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; })
-#define inw(p) ({ unsigned int __v = __raw_readw(__io(p)); __v; })
-#define inl(p) ({ unsigned int __v = __raw_readl(__io(p)); __v; })
+#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
#define outsb(p,d,l) __raw_writesb(__io(p),d,l)
#define outsw(p,d,l) __raw_writesw(__io(p),d,l)
*/
#ifdef __mem_pci
-#define readb(addr) ({ unsigned int __v = __raw_readb(__mem_pci(addr)); __v; })
-#define readw(addr) ({ unsigned int __v = __raw_readw(__mem_pci(addr)); __v; })
-#define readl(addr) ({ unsigned int __v = __raw_readl(__mem_pci(addr)); __v; })
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
-#define writeb(val,addr) __raw_writeb(val,__mem_pci(addr))
-#define writew(val,addr) __raw_writew(val,__mem_pci(addr))
-#define writel(val,addr) __raw_writel(val,__mem_pci(addr))
+#define writeb(v,c) __raw_writeb(v,__mem_pci(c))
+#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c))
+#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c))
-#define memset_io(a,b,c) _memset_io(__mem_pci(a),(b),(c))
-#define memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_pci(b),(c))
-#define memcpy_toio(a,b,c) _memcpy_toio(__mem_pci(a),(b),(c))
+#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l))
+#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l))
+#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l))
-#define eth_io_copy_and_sum(a,b,c,d) \
- eth_copy_and_sum((a),__mem_pci(b),(c),(d))
+#define eth_io_copy_and_sum(s,c,l,b) \
+ eth_copy_and_sum((s),__mem_pci(c),(l),(b))
static inline int
check_signature(unsigned long io_addr, const unsigned char *signature,
#endif /* __mem_pci */
/*
- * remap a physical address `phys' of size `size' with page protection `prot'
- * into virtual address `from'
- */
-#define io_remap_page_range(from,phys,size,prot) \
- remap_page_range(from,phys,size,prot)
-
-
-/*
* If this architecture has ISA IO, then define the isa_read/isa_write
* macros.
*/
#define isa_check_signature(io,sig,len) (0)
#endif /* __mem_isa */
-
+#endif /* __KERNEL__ */
#endif /* __ASM_ARM_IO_H */
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