[binutils][aarch64] New SVE_ADDR_ZX operand.

[external/binutils.git] / include / ChangeLog

diff --git a/include/ChangeLog b/include/ChangeLog
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@@ -1,3 +1,108 @@
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand.
+
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand.
+
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass.
+
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.
+
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * opcode/aarch64.h (AARCH64_FEATURE_SVE2
+       AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
+       AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
+       feature macros.
+
+2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
+           Faraz Shahbazker  <fshahbazker@wavecomp.com>
+
+       * opcode/mips.h (ASE_EVA_R6): New macro.
+       (M_LLWPE_AB, M_SCWPE_AB): New enum values.
+
+2019-05-01  Sudakshina Das  <sudi.das@arm.com>
+
+       * opcode/aarch64.h (AARCH64_FEATURE_TME): New.
+       (enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16.
+
+2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
+           Faraz Shahbazker  <fshahbazker@wavecomp.com>
+
+       * opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values.
+       (M_SCWP_AB, M_SCDP_AB): Likewise.
+
+2019-04-25  Maciej W. Rozycki  <macro@linux-mips.org>
+
+       * opcode/mips.h: Update comment for MIPS32 CODE20 operand.
+
+2019-04-15  Sudakshina Das  <sudi.das@arm.com>
+
+       * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12.
+
+2019-04-15  Sudakshina Das  <sudi.das@arm.com>
+
+       * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18.
+
+2019-04-15  Sudakshina Das  <sudi.das@arm.com>
+
+       * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.
+
+2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+       * elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro.
+       (MAX_TAG_CPU_ARCH): Set value to above macro.
+       * opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro.
+       (ARM_AEXT_V8_1M_MAIN): Likewise.
+       (ARM_AEXT2_V8_1M_MAIN): Likewise.
+       (ARM_ARCH_V8_1M_MAIN): Likewise.
+
+2019-04-11  Sudakshina Das  <sudi.das@arm.com>
+
+       * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
+
+2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * elf/common.h (GNU_PROPERTY_X86_ISA_1_AVX512_BF16): New.
+
+2019-04-07  Alan Modra  <amodra@gmail.com>
+
+       Merge from gcc.
+       2019-04-03  Vineet Gupta  <vgupta@synopsys.com>
+       PR89877
+       * longlong.h [__arc__] (add_ssaaaa): Add cc clobber.
+       (sub_ddmmss): Likewise.
+
+2019-04-06  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * bfdlink.h (bfd_link_info): Remove x86-specific linker options.
+
+2019-04-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+       * opcode/arm.h (FPU_NEON_ARMV8_1): New.
+       (FPU_ARCH_NEON_VFP_ARMV8_1): Use FPU_NEON_ARMV8_1.
+       (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): Likewise.
+       (FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): Likewise.
+       (FPU_ARCH_NEON_VFP_ARMV8_2_FP16): New.
+       (FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML): New.
+       (FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML): New.
+       (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4): New.
+
+2019-03-28  Alan Modra  <amodra@gmail.com>
+
+       PR 24390
+       * opcode/ppc.h (PPC_OPERAND_CR_REG): Comment.
+
+2019-03-25  Tamar Christina  <tamar.christina@arm.com>
+
+       * dis-asm.h (struct disassemble_info): Add stop_offset.
+
 2019-03-13  Sudakshina Das  <sudi.das@arm.com>
 
        * elf/aarch64.h (DT_AARCH64_PAC_PLT): New.