#ifndef RISCV_TDEP_H
#define RISCV_TDEP_H
+#include "arch/riscv.h"
+
/* RiscV register numbers. */
enum
{
/* RISC-V specific per-architecture information. */
struct gdbarch_tdep
{
- union
- {
- /* Provide access to the whole ABI in one value. */
- unsigned value;
-
- struct
- {
- /* Encode the base machine length following the same rules as in the
- MISA register. */
- unsigned base_len : 2;
-
- /* Encode which floating point ABI is in use following the same rules
- as the ELF e_flags field. */
- unsigned float_abi : 2;
- } fields;
- } abi;
-
- /* Only the least significant 26 bits are (possibly) valid, and indicate
- features that are supported on the target. These could be cached from
- the target, or read from the executable when available. */
- unsigned core_features;
+ /* Features about the target that impact how the gdbarch is configured.
+ Two gdbarch instances are compatible only if this field matches. */
+ struct riscv_gdbarch_features features;
+
+ /* ISA-specific data types. */
+ struct type *riscv_fpreg_d_type = nullptr;
};
-/* Return the width in bytes of the general purpose registers for GDBARCH. */
+
+/* Return the width in bytes of the general purpose registers for GDBARCH.
+ Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
+ RV128. */
extern int riscv_isa_xlen (struct gdbarch *gdbarch);
+/* Return the width in bytes of the floating point registers for GDBARCH.
+ If this architecture has no floating point registers, then return 0.
+ Possible values are 4, 8, or 16 for depending on which of single, double
+ or quad floating point support is available. */
+extern int riscv_isa_flen (struct gdbarch *gdbarch);
+
/* Single step based on where the current instruction will take us. */
extern std::vector<CORE_ADDR> riscv_software_single_step
(struct regcache *regcache);