Change TUI source window iteration
[external/binutils.git] / gdb / configure.tgt
index 9b646fa..7c0215e 100644 (file)
@@ -48,8 +48,9 @@ amd64_tobjs="amd64-tdep.o arch/amd64.o ${x86_tobjs}"
 
 case "${targ}" in
 aarch64*-*-*)
-       cpu_obs="aarch64-tdep.o arch/aarch64-insn.o arch/aarch64.o \
-                ravenscar-thread.o aarch64-ravenscar-thread.o";;
+       cpu_obs="aarch32-tdep.o aarch64-tdep.o arch/aarch32.o \
+                arch/aarch64-insn.o arch/aarch64.o  ravenscar-thread.o \
+                aarch64-ravenscar-thread.o";;
 
 alpha*-*-*)
        # Target: Alpha
@@ -62,7 +63,8 @@ arc*-*-*)
        ;;
 
 arm*-*-*)
-       cpu_obs="arch/arm.o arch/arm-get-next-pcs.o arm-tdep.o";;
+       cpu_obs="aarch32-tdep.o arch/aarch32.o arch/arm.o \
+                arch/arm-get-next-pcs.o arm-tdep.o";;
 
 hppa*-*-*)
        # Target: HP PA-RISC
@@ -471,6 +473,14 @@ nios2*-*-*)
        gdb_target_obs="nios2-tdep.o"
        ;;
 
+or1k*-*-linux*)
+       # Target: OpenCores OpenRISC 1000 32-bit running Linux
+       gdb_target_obs="or1k-tdep.o or1k-linux-tdep.o solib-svr4.o \
+                       symfile-mem.o glibc-tdep.o linux-tdep.o"
+       gdb_sim=../sim/or1k/libsim.a
+       build_gdbserver=yes
+       ;;
+
 or1k-*-* | or1knd-*-*)
        # Target: OpenCores OpenRISC 1000 32-bit implementation bare metal
        gdb_target_obs="or1k-tdep.o"