Refactor arm_stack_frame_destroyed_p

[external/binutils.git] / gdb / arm-tdep.c

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 605f09b..6ede3a9 100644 (file)
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -3124,19 +3124,14 @@ thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
   return found_stack_adjust;
 }
 
-/* Implement the stack_frame_destroyed_p gdbarch method.  */
-
 static int
-arm_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
+arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, CORE_ADDR pc)
 {
   enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
   unsigned int insn;
   int found_return;
   CORE_ADDR func_start, func_end;
 
-  if (arm_pc_is_thumb (gdbarch, pc))
-    return thumb_stack_frame_destroyed_p (gdbarch, pc);
-
   if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
     return 0;
 
@@ -3178,6 +3173,16 @@ arm_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
   return 0;
 }
 
+/* Implement the stack_frame_destroyed_p gdbarch method.  */
+
+static int
+arm_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
+{
+  if (arm_pc_is_thumb (gdbarch, pc))
+    return thumb_stack_frame_destroyed_p (gdbarch, pc);
+  else
+    return arm_stack_frame_destroyed_p_1 (gdbarch, pc);
+}
 
 /* When arguments must be pushed onto the stack, they go on in reverse
    order.  The code below implements a FILO (stack) to do this.  */
@@ -10288,6 +10293,88 @@ arm_record_data_proc_imm (insn_decode_record *arm_insn_r)
   return 0;
 }
 
+static int
+arm_record_media (insn_decode_record *arm_insn_r)
+{
+  uint32_t record_buf[8];
+
+  switch (bits (arm_insn_r->arm_insn, 22, 24))
+    {
+    case 0:
+      /* Parallel addition and subtraction, signed */
+    case 1:
+      /* Parallel addition and subtraction, unsigned */
+    case 2:
+    case 3:
+      /* Packing, unpacking, saturation and reversal */
+      {
+       int rd = bits (arm_insn_r->arm_insn, 12, 15);
+
+       record_buf[arm_insn_r->reg_rec_count++] = rd;
+      }
+      break;
+
+    case 4:
+    case 5:
+      /* Signed multiplies */
+      {
+       int rd = bits (arm_insn_r->arm_insn, 16, 19);
+       unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 22);
+
+       record_buf[arm_insn_r->reg_rec_count++] = rd;
+       if (op1 == 0x0)
+         record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM;
+       else if (op1 == 0x4)
+         record_buf[arm_insn_r->reg_rec_count++]
+           = bits (arm_insn_r->arm_insn, 12, 15);
+      }
+      break;
+
+    case 6:
+      {
+       if (bit (arm_insn_r->arm_insn, 21)
+           && bits (arm_insn_r->arm_insn, 5, 6) == 0x2)
+         {
+           /* SBFX */
+           record_buf[arm_insn_r->reg_rec_count++]
+             = bits (arm_insn_r->arm_insn, 12, 15);
+         }
+       else if (bits (arm_insn_r->arm_insn, 20, 21) == 0x0
+                && bits (arm_insn_r->arm_insn, 5, 7) == 0x0)
+         {
+           /* USAD8 and USADA8 */
+           record_buf[arm_insn_r->reg_rec_count++]
+             = bits (arm_insn_r->arm_insn, 16, 19);
+         }
+      }
+      break;
+
+    case 7:
+      {
+       if (bits (arm_insn_r->arm_insn, 20, 21) == 0x3
+           && bits (arm_insn_r->arm_insn, 5, 7) == 0x7)
+         {
+           /* Permanently UNDEFINED */
+           return -1;
+         }
+       else
+         {
+           /* BFC, BFI and UBFX */
+           record_buf[arm_insn_r->reg_rec_count++]
+             = bits (arm_insn_r->arm_insn, 12, 15);
+         }
+      }
+      break;
+
+    default:
+      return -1;
+    }
+
+  REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
+
+  return 0;
+}
+
 /* Handle ARM mode instructions with opcode 010.  */
 
 static int
@@ -10394,6 +10481,9 @@ arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r)
   LONGEST s_word;
   ULONGEST u_regval[2];
 
+  if (bit (arm_insn_r->arm_insn, 4))
+    return arm_record_media (arm_insn_r);
+
   arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
   arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
 
@@ -10800,12 +10890,7 @@ arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
       /* Handle VMOV instruction.  */
       if (bits_a == 0x00)
         {
-          if (bit (arm_insn_r->arm_insn, 20))
-            record_buf[0] = reg_t;
-          else
-            record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
-                            (reg_v << 1));
-
+         record_buf[0] = reg_t;
           arm_insn_r->reg_rec_count = 1;
         }
       /* Handle VMRS instruction.  */
@@ -10823,11 +10908,7 @@ arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
       /* Handle VMOV instruction.  */
       if (bits_a == 0x00)
         {
-          if (bit (arm_insn_r->arm_insn, 20))
-            record_buf[0] = reg_t;
-          else
-            record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
-                            (reg_v << 1));
+         record_buf[0] = ARM_D0_REGNUM + reg_v;
 
           arm_insn_r->reg_rec_count = 1;
         }