/* Add our register access methods. */
void fetch_registers (struct regcache *, int) override;
void store_registers (struct regcache *, int) override;
+
+ bool low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction)
+ override;
};
static amd64_linux_nat_target the_amd64_linux_nat_target;
int tid;
/* GNU/Linux LWP ID's are process ID's. */
- tid = ptid_get_lwp (regcache_get_ptid (regcache));
+ tid = ptid_get_lwp (regcache->ptid ());
if (tid == 0)
- tid = ptid_get_pid (regcache_get_ptid (regcache)); /* Not a threaded program. */
+ tid = ptid_get_pid (regcache->ptid ()); /* Not a threaded program. */
if (regnum == -1 || amd64_native_gregset_supplies_p (gdbarch, regnum))
{
if (ptrace (PTRACE_ARCH_PRCTL, tid, &base, ARCH_GET_FS) < 0)
perror_with_name (_("Couldn't get segment register fs_base"));
- regcache_raw_supply (regcache, AMD64_FSBASE_REGNUM, &base);
+ regcache->raw_supply (AMD64_FSBASE_REGNUM, &base);
}
if (regnum == -1 || regnum == AMD64_GSBASE_REGNUM)
if (ptrace (PTRACE_ARCH_PRCTL, tid, &base, ARCH_GET_GS) < 0)
perror_with_name (_("Couldn't get segment register gs_base"));
- regcache_raw_supply (regcache, AMD64_GSBASE_REGNUM, &base);
+ regcache->raw_supply (AMD64_GSBASE_REGNUM, &base);
}
}
#endif
int tid;
/* GNU/Linux LWP ID's are process ID's. */
- tid = ptid_get_lwp (regcache_get_ptid (regcache));
+ tid = ptid_get_lwp (regcache->ptid ());
if (tid == 0)
- tid = ptid_get_pid (regcache_get_ptid (regcache)); /* Not a threaded program. */
+ tid = ptid_get_pid (regcache->ptid ()); /* Not a threaded program. */
if (regnum == -1 || amd64_native_gregset_supplies_p (gdbarch, regnum))
{
if (regnum == -1 || regnum == AMD64_FSBASE_REGNUM)
{
- regcache_raw_collect (regcache, AMD64_FSBASE_REGNUM, &base);
+ regcache->raw_collect (AMD64_FSBASE_REGNUM, &base);
if (ptrace (PTRACE_ARCH_PRCTL, tid, base, ARCH_SET_FS) < 0)
perror_with_name (_("Couldn't write segment register fs_base"));
if (regnum == -1 || regnum == AMD64_GSBASE_REGNUM)
{
- regcache_raw_collect (regcache, AMD64_GSBASE_REGNUM, &base);
+ regcache->raw_collect (AMD64_GSBASE_REGNUM, &base);
if (ptrace (PTRACE_ARCH_PRCTL, tid, base, ARCH_SET_GS) < 0)
perror_with_name (_("Couldn't write segment register gs_base"));
}
from INF to PTRACE. If DIRECTION is 0, copy from PTRACE to
INF. */
-static int
-amd64_linux_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction)
+bool
+amd64_linux_nat_target::low_siginfo_fixup (siginfo_t *ptrace,
+ gdb_byte *inf,
+ int direction)
{
struct gdbarch *gdbarch = get_frame_arch (get_current_frame ());
/* Is the inferior 32-bit? If so, then do fixup the siginfo
object. */
if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
- return amd64_linux_siginfo_fixup_common (ptrace, inf, direction,
- FIXUP_32);
+ return amd64_linux_siginfo_fixup_common (ptrace, inf, direction,
+ FIXUP_32);
/* No fixup for native x32 GDB. */
else if (gdbarch_addr_bit (gdbarch) == 32 && sizeof (void *) == 8)
- return amd64_linux_siginfo_fixup_common (ptrace, inf, direction,
- FIXUP_X32);
+ return amd64_linux_siginfo_fixup_common (ptrace, inf, direction,
+ FIXUP_X32);
else
- return 0;
+ return false;
}
void
linux_target = &the_amd64_linux_nat_target;
/* Add the target. */
- x86_linux_add_target (linux_target);
-
- /* Add our siginfo layout converter. */
- linux_nat_set_siginfo_fixup (linux_target, amd64_linux_siginfo_fixup);
+ add_inf_child_target (linux_target);
}