/* Analyze RTL for GNU compiler.
- Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
- 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
- 2011 Free Software Foundation, Inc.
+ Copyright (C) 1987-2013 Free Software Foundation, Inc.
This file is part of GCC.
#include "df.h"
#include "tree.h"
#include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
+#include "addresses.h"
/* Forward declarations */
static void set_of_1 (rtx, const_rtx, void *);
return !MEM_READONLY_P (x) || rtx_unstable_p (XEXP (x, 0));
case CONST:
- case CONST_INT:
- case CONST_DOUBLE:
- case CONST_FIXED:
- case CONST_VECTOR:
+ CASE_CONST_ANY:
case SYMBOL_REF:
case LABEL_REF:
return 0;
return !MEM_READONLY_P (x) || rtx_varies_p (XEXP (x, 0), for_alias);
case CONST:
- case CONST_INT:
- case CONST_DOUBLE:
- case CONST_FIXED:
- case CONST_VECTOR:
+ CASE_CONST_ANY:
case SYMBOL_REF:
case LABEL_REF:
return 0;
return nonzero_address_p (XEXP (x, 0));
case PLUS:
- if (CONST_INT_P (XEXP (x, 1)))
- return nonzero_address_p (XEXP (x, 0));
/* Handle PIC references. */
- else if (XEXP (x, 0) == pic_offset_table_rtx
+ if (XEXP (x, 0) == pic_offset_table_rtx
&& CONSTANT_P (XEXP (x, 1)))
return true;
return false;
return 0;
}
\f
+/* Return the CALL in X if there is one. */
+
+rtx
+get_call_rtx_from (rtx x)
+{
+ if (INSN_P (x))
+ x = PATTERN (x);
+ if (GET_CODE (x) == PARALLEL)
+ x = XVECEXP (x, 0, 0);
+ if (GET_CODE (x) == SET)
+ x = SET_SRC (x);
+ if (GET_CODE (x) == CALL && MEM_P (XEXP (x, 0)))
+ return x;
+ return NULL_RTX;
+}
+\f
/* Return the value of the integer term in X, if one is apparent;
otherwise return 0.
Only obvious integer terms are detected.
switch (code)
{
case REG:
- case CONST_INT:
- case CONST_DOUBLE:
- case CONST_FIXED:
- case CONST_VECTOR:
+ CASE_CONST_ANY:
case SYMBOL_REF:
case CODE_LABEL:
case PC:
}
\f
+/* Return TRUE if OP is a register or subreg of a register that
+ holds an unsigned quantity. Otherwise, return FALSE. */
+
+bool
+unsigned_reg_p (rtx op)
+{
+ if (REG_P (op)
+ && REG_EXPR (op)
+ && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op))))
+ return true;
+
+ if (GET_CODE (op) == SUBREG
+ && SUBREG_PROMOTED_UNSIGNED_P (op))
+ return true;
+
+ return false;
+}
+
+\f
/* Nonzero if register REG appears somewhere within IN.
Also works if REG is not a register; in this case it checks
for a subexpression of IN that is Lisp "equal" to REG. */
case PC:
return 0;
- case CONST_INT:
- case CONST_VECTOR:
- case CONST_DOUBLE:
- case CONST_FIXED:
+ CASE_CONST_ANY:
/* These are kept unique for a given value. */
return 0;
switch (code)
{
- case CONST_INT:
- case CONST_DOUBLE:
- case CONST_FIXED:
- case CONST_VECTOR:
+ CASE_CONST_ANY:
case CONST:
case SYMBOL_REF:
case LABEL_REF:
switch (code)
{
- case CONST_INT:
- case CONST_DOUBLE:
- case CONST_FIXED:
- case CONST_VECTOR:
+ CASE_CONST_ANY:
case CONST:
case SYMBOL_REF:
case LABEL_REF:
pattern = PATTERN (insn);
+ /* If a COND_EXEC is not executed, the value survives. */
if (GET_CODE (pattern) == COND_EXEC)
- pattern = COND_EXEC_CODE (pattern);
+ return 0;
if (GET_CODE (pattern) == SET)
return covers_regno_p (SET_DEST (pattern), test_regno);
\f
/* Nonzero if X contains any volatile instructions. These are instructions
which may cause unpredictable machine state instructions, and thus no
- instructions should be moved or combined across them. This includes
- only volatile asms and UNSPEC_VOLATILE instructions. */
+ instructions or register uses should be moved or combined across them.
+ This includes only volatile asms and UNSPEC_VOLATILE instructions. */
int
volatile_insn_p (const_rtx x)
{
case LABEL_REF:
case SYMBOL_REF:
- case CONST_INT:
case CONST:
- case CONST_DOUBLE:
- case CONST_FIXED:
- case CONST_VECTOR:
+ CASE_CONST_ANY:
case CC0:
case PC:
case REG:
return 0;
case UNSPEC_VOLATILE:
- /* case TRAP_IF: This isn't clear yet. */
return 1;
case ASM_INPUT:
{
case LABEL_REF:
case SYMBOL_REF:
- case CONST_INT:
case CONST:
- case CONST_DOUBLE:
- case CONST_FIXED:
- case CONST_VECTOR:
+ CASE_CONST_ANY:
case CC0:
case PC:
case REG:
{
case LABEL_REF:
case SYMBOL_REF:
- case CONST_INT:
case CONST:
- case CONST_DOUBLE:
- case CONST_FIXED:
- case CONST_VECTOR:
+ CASE_CONST_ANY:
case CC0:
case PC:
case REG:
case POST_MODIFY:
case CALL:
case UNSPEC_VOLATILE:
- /* case TRAP_IF: This isn't clear yet. */
return 1;
case MEM:
switch (code)
{
/* Handle these cases quickly. */
- case CONST_INT:
- case CONST_DOUBLE:
- case CONST_FIXED:
- case CONST_VECTOR:
+ CASE_CONST_ANY:
case SYMBOL_REF:
case LABEL_REF:
case CONST:
return 0;
case UNSPEC:
- case UNSPEC_VOLATILE:
return targetm.unspec_may_trap_p (x, flags);
+ case UNSPEC_VOLATILE:
case ASM_INPUT:
case TRAP_IF:
return 1;
default:
/* Any floating arithmetic may trap. */
- if (SCALAR_FLOAT_MODE_P (GET_MODE (x))
- && flag_trapping_math)
+ if (SCALAR_FLOAT_MODE_P (GET_MODE (x)) && flag_trapping_math)
return 1;
}
case SCRATCH:
case PC:
case CC0:
- case CONST_INT:
- case CONST_DOUBLE:
- case CONST_FIXED:
- case CONST_VECTOR:
+ CASE_CONST_ANY:
case CONST:
case LABEL_REF:
case SYMBOL_REF:
int i, j;
const char *fmt;
- /* The following prevents loops occurrence when we change MEM in
- CONST_DOUBLE onto the same CONST_DOUBLE. */
- if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
- return x;
-
if (x == from)
return to;
return 0;
case CONST:
- case CONST_INT:
- case CONST_DOUBLE:
- case CONST_FIXED:
- case CONST_VECTOR:
+ CASE_CONST_ANY:
case SYMBOL_REF:
case REG:
return 1;
/* Give the backend a chance to disallow the mode change. */
if (GET_MODE_CLASS (xmode) != MODE_COMPLEX_INT
&& GET_MODE_CLASS (xmode) != MODE_COMPLEX_FLOAT
- && REG_CANNOT_CHANGE_MODE_P (xregno, xmode, ymode))
+ && REG_CANNOT_CHANGE_MODE_P (xregno, xmode, ymode)
+ /* We can use mode change in LRA for some transformations. */
+ && ! lra_in_progress)
return -1;
#endif
&& xregno == ARG_POINTER_REGNUM)
return -1;
- if (xregno == STACK_POINTER_REGNUM)
+ if (xregno == STACK_POINTER_REGNUM
+ /* We should convert hard stack register in LRA if it is
+ possible. */
+ && ! lra_in_progress)
return -1;
/* Try to get the register offset. */
enum rtx_code code;
const char *fmt;
int total;
+ int factor;
if (x == 0)
return 0;
+ /* A size N times larger than UNITS_PER_WORD likely needs N times as
+ many insns, taking N times as long. */
+ factor = GET_MODE_SIZE (GET_MODE (x)) / UNITS_PER_WORD;
+ if (factor == 0)
+ factor = 1;
+
/* Compute the default costs of certain things.
Note that targetm.rtx_costs can override the defaults. */
switch (code)
{
case MULT:
- total = COSTS_N_INSNS (5);
+ /* Multiplication has time-complexity O(N*N), where N is the
+ number of units (translated from digits) when using
+ schoolbook long multiplication. */
+ total = factor * factor * COSTS_N_INSNS (5);
break;
case DIV:
case UDIV:
case MOD:
case UMOD:
- total = COSTS_N_INSNS (7);
+ /* Similarly, complexity for schoolbook long division. */
+ total = factor * factor * COSTS_N_INSNS (7);
break;
case USE:
/* Used in combine.c as a marker. */
total = 0;
break;
+ case SET:
+ /* A SET doesn't have a mode, so let's look at the SET_DEST to get
+ the mode for the factor. */
+ factor = GET_MODE_SIZE (GET_MODE (SET_DEST (x))) / UNITS_PER_WORD;
+ if (factor == 0)
+ factor = 1;
+ /* Pass through. */
default:
- total = COSTS_N_INSNS (1);
+ total = factor * COSTS_N_INSNS (1);
}
switch (code)
/* If we can't tie these modes, make this expensive. The larger
the mode, the more expensive it is. */
if (! MODES_TIEABLE_P (GET_MODE (x), GET_MODE (SUBREG_REG (x))))
- return COSTS_N_INSNS (2
- + GET_MODE_SIZE (GET_MODE (x)) / UNITS_PER_WORD);
+ return COSTS_N_INSNS (2 + factor);
break;
default:
if (!memory_address_addr_space_p (mode, x, as))
return 1000;
- return targetm.address_cost (x, speed);
+ return targetm.address_cost (x, mode, as, speed);
}
/* If the target doesn't override, compute the cost as with arithmetic. */
int
-default_address_cost (rtx x, bool speed)
+default_address_cost (rtx x, enum machine_mode, addr_space_t, bool speed)
{
return rtx_cost (x, MEM, 0, speed);
}
#if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
/* If pointers extend unsigned and this is a pointer in Pmode, say that
all the bits above ptr_mode are known to be zero. */
- /* As we do not know which address space the pointer is refering to,
+ /* As we do not know which address space the pointer is referring to,
we can do this only if the target does not support different pointer
or address modes depending on the address space. */
if (target_default_pointer_address_modes_p ()
#if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
/* If pointers extend signed and this is a pointer in Pmode, say that
all the bits above ptr_mode are known to be sign bit copies. */
- /* As we do not know which address space the pointer is refering to,
+ /* As we do not know which address space the pointer is referring to,
we can do this only if the target does not support different pointer
or address modes depending on the address space. */
if (target_default_pointer_address_modes_p ()
constant_pool_constant_p (rtx x)
{
x = avoid_constant_pool_reference (x);
- return GET_CODE (x) == CONST_DOUBLE;
+ return CONST_DOUBLE_P (x);
}
\f
/* If M is a bitmask that selects a field of low-order bits within an item but
return exact_log2 (m + 1);
}
+
+/* Return the mode of MEM's address. */
+
+enum machine_mode
+get_address_mode (rtx mem)
+{
+ enum machine_mode mode;
+
+ gcc_assert (MEM_P (mem));
+ mode = GET_MODE (XEXP (mem, 0));
+ if (mode != VOIDmode)
+ return mode;
+ return targetm.addr_space.address_mode (MEM_ADDR_SPACE (mem));
+}
+\f
+/* Split up a CONST_DOUBLE or integer constant rtx
+ into two rtx's for single words,
+ storing in *FIRST the word that comes first in memory in the target
+ and in *SECOND the other. */
+
+void
+split_double (rtx value, rtx *first, rtx *second)
+{
+ if (CONST_INT_P (value))
+ {
+ if (HOST_BITS_PER_WIDE_INT >= (2 * BITS_PER_WORD))
+ {
+ /* In this case the CONST_INT holds both target words.
+ Extract the bits from it into two word-sized pieces.
+ Sign extend each half to HOST_WIDE_INT. */
+ unsigned HOST_WIDE_INT low, high;
+ unsigned HOST_WIDE_INT mask, sign_bit, sign_extend;
+ unsigned bits_per_word = BITS_PER_WORD;
+
+ /* Set sign_bit to the most significant bit of a word. */
+ sign_bit = 1;
+ sign_bit <<= bits_per_word - 1;
+
+ /* Set mask so that all bits of the word are set. We could
+ have used 1 << BITS_PER_WORD instead of basing the
+ calculation on sign_bit. However, on machines where
+ HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
+ compiler warning, even though the code would never be
+ executed. */
+ mask = sign_bit << 1;
+ mask--;
+
+ /* Set sign_extend as any remaining bits. */
+ sign_extend = ~mask;
+
+ /* Pick the lower word and sign-extend it. */
+ low = INTVAL (value);
+ low &= mask;
+ if (low & sign_bit)
+ low |= sign_extend;
+
+ /* Pick the higher word, shifted to the least significant
+ bits, and sign-extend it. */
+ high = INTVAL (value);
+ high >>= bits_per_word - 1;
+ high >>= 1;
+ high &= mask;
+ if (high & sign_bit)
+ high |= sign_extend;
+
+ /* Store the words in the target machine order. */
+ if (WORDS_BIG_ENDIAN)
+ {
+ *first = GEN_INT (high);
+ *second = GEN_INT (low);
+ }
+ else
+ {
+ *first = GEN_INT (low);
+ *second = GEN_INT (high);
+ }
+ }
+ else
+ {
+ /* The rule for using CONST_INT for a wider mode
+ is that we regard the value as signed.
+ So sign-extend it. */
+ rtx high = (INTVAL (value) < 0 ? constm1_rtx : const0_rtx);
+ if (WORDS_BIG_ENDIAN)
+ {
+ *first = high;
+ *second = value;
+ }
+ else
+ {
+ *first = value;
+ *second = high;
+ }
+ }
+ }
+ else if (!CONST_DOUBLE_P (value))
+ {
+ if (WORDS_BIG_ENDIAN)
+ {
+ *first = const0_rtx;
+ *second = value;
+ }
+ else
+ {
+ *first = value;
+ *second = const0_rtx;
+ }
+ }
+ else if (GET_MODE (value) == VOIDmode
+ /* This is the old way we did CONST_DOUBLE integers. */
+ || GET_MODE_CLASS (GET_MODE (value)) == MODE_INT)
+ {
+ /* In an integer, the words are defined as most and least significant.
+ So order them by the target's convention. */
+ if (WORDS_BIG_ENDIAN)
+ {
+ *first = GEN_INT (CONST_DOUBLE_HIGH (value));
+ *second = GEN_INT (CONST_DOUBLE_LOW (value));
+ }
+ else
+ {
+ *first = GEN_INT (CONST_DOUBLE_LOW (value));
+ *second = GEN_INT (CONST_DOUBLE_HIGH (value));
+ }
+ }
+ else
+ {
+ REAL_VALUE_TYPE r;
+ long l[2];
+ REAL_VALUE_FROM_CONST_DOUBLE (r, value);
+
+ /* Note, this converts the REAL_VALUE_TYPE to the target's
+ format, splits up the floating point double and outputs
+ exactly 32 bits of it into each of l[0] and l[1] --
+ not necessarily BITS_PER_WORD bits. */
+ REAL_VALUE_TO_TARGET_DOUBLE (r, l);
+
+ /* If 32 bits is an entire word for the target, but not for the host,
+ then sign-extend on the host so that the number will look the same
+ way on the host that it would on the target. See for instance
+ simplify_unary_operation. The #if is needed to avoid compiler
+ warnings. */
+
+#if HOST_BITS_PER_LONG > 32
+ if (BITS_PER_WORD < HOST_BITS_PER_LONG && BITS_PER_WORD == 32)
+ {
+ if (l[0] & ((long) 1 << 31))
+ l[0] |= ((long) (-1) << 32);
+ if (l[1] & ((long) 1 << 31))
+ l[1] |= ((long) (-1) << 32);
+ }
+#endif
+
+ *first = GEN_INT (l[0]);
+ *second = GEN_INT (l[1]);
+ }
+}
+
+/* Strip outer address "mutations" from LOC and return a pointer to the
+ inner value. If OUTER_CODE is nonnull, store the code of the innermost
+ stripped expression there.
+
+ "Mutations" either convert between modes or apply some kind of
+ alignment. */
+
+rtx *
+strip_address_mutations (rtx *loc, enum rtx_code *outer_code)
+{
+ for (;;)
+ {
+ enum rtx_code code = GET_CODE (*loc);
+ if (GET_RTX_CLASS (code) == RTX_UNARY)
+ /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be
+ used to convert between pointer sizes. */
+ loc = &XEXP (*loc, 0);
+ else if (code == AND && CONST_INT_P (XEXP (*loc, 1)))
+ /* (and ... (const_int -X)) is used to align to X bytes. */
+ loc = &XEXP (*loc, 0);
+ else if (code == SUBREG
+ && !OBJECT_P (SUBREG_REG (*loc))
+ && subreg_lowpart_p (*loc))
+ /* (subreg (operator ...) ...) inside and is used for mode
+ conversion too. */
+ loc = &SUBREG_REG (*loc);
+ else
+ return loc;
+ if (outer_code)
+ *outer_code = code;
+ }
+}
+
+/* Return true if X must be a base rather than an index. */
+
+static bool
+must_be_base_p (rtx x)
+{
+ return GET_CODE (x) == LO_SUM;
+}
+
+/* Return true if X must be an index rather than a base. */
+
+static bool
+must_be_index_p (rtx x)
+{
+ return GET_CODE (x) == MULT || GET_CODE (x) == ASHIFT;
+}
+
+/* Set the segment part of address INFO to LOC, given that INNER is the
+ unmutated value. */
+
+static void
+set_address_segment (struct address_info *info, rtx *loc, rtx *inner)
+{
+ gcc_checking_assert (GET_CODE (*inner) == UNSPEC);
+
+ gcc_assert (!info->segment);
+ info->segment = loc;
+ info->segment_term = inner;
+}
+
+/* Set the base part of address INFO to LOC, given that INNER is the
+ unmutated value. */
+
+static void
+set_address_base (struct address_info *info, rtx *loc, rtx *inner)
+{
+ if (GET_CODE (*inner) == LO_SUM)
+ inner = strip_address_mutations (&XEXP (*inner, 0));
+ gcc_checking_assert (REG_P (*inner)
+ || MEM_P (*inner)
+ || GET_CODE (*inner) == SUBREG);
+
+ gcc_assert (!info->base);
+ info->base = loc;
+ info->base_term = inner;
+}
+
+/* Set the index part of address INFO to LOC, given that INNER is the
+ unmutated value. */
+
+static void
+set_address_index (struct address_info *info, rtx *loc, rtx *inner)
+{
+ if ((GET_CODE (*inner) == MULT || GET_CODE (*inner) == ASHIFT)
+ && CONSTANT_P (XEXP (*inner, 1)))
+ inner = strip_address_mutations (&XEXP (*inner, 0));
+ gcc_checking_assert (REG_P (*inner)
+ || MEM_P (*inner)
+ || GET_CODE (*inner) == SUBREG);
+
+ gcc_assert (!info->index);
+ info->index = loc;
+ info->index_term = inner;
+}
+
+/* Set the displacement part of address INFO to LOC, given that INNER
+ is the constant term. */
+
+static void
+set_address_disp (struct address_info *info, rtx *loc, rtx *inner)
+{
+ gcc_checking_assert (CONSTANT_P (*inner));
+
+ gcc_assert (!info->disp);
+ info->disp = loc;
+ info->disp_term = inner;
+}
+
+/* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the
+ rest of INFO accordingly. */
+
+static void
+decompose_incdec_address (struct address_info *info)
+{
+ info->autoinc_p = true;
+
+ rtx *base = &XEXP (*info->inner, 0);
+ set_address_base (info, base, base);
+ gcc_checking_assert (info->base == info->base_term);
+
+ /* These addresses are only valid when the size of the addressed
+ value is known. */
+ gcc_checking_assert (info->mode != VOIDmode);
+}
+
+/* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest
+ of INFO accordingly. */
+
+static void
+decompose_automod_address (struct address_info *info)
+{
+ info->autoinc_p = true;
+
+ rtx *base = &XEXP (*info->inner, 0);
+ set_address_base (info, base, base);
+ gcc_checking_assert (info->base == info->base_term);
+
+ rtx plus = XEXP (*info->inner, 1);
+ gcc_assert (GET_CODE (plus) == PLUS);
+
+ info->base_term2 = &XEXP (plus, 0);
+ gcc_checking_assert (rtx_equal_p (*info->base_term, *info->base_term2));
+
+ rtx *step = &XEXP (plus, 1);
+ rtx *inner_step = strip_address_mutations (step);
+ if (CONSTANT_P (*inner_step))
+ set_address_disp (info, step, inner_step);
+ else
+ set_address_index (info, step, inner_step);
+}
+
+/* Treat *LOC as a tree of PLUS operands and store pointers to the summed
+ values in [PTR, END). Return a pointer to the end of the used array. */
+
+static rtx **
+extract_plus_operands (rtx *loc, rtx **ptr, rtx **end)
+{
+ rtx x = *loc;
+ if (GET_CODE (x) == PLUS)
+ {
+ ptr = extract_plus_operands (&XEXP (x, 0), ptr, end);
+ ptr = extract_plus_operands (&XEXP (x, 1), ptr, end);
+ }
+ else
+ {
+ gcc_assert (ptr != end);
+ *ptr++ = loc;
+ }
+ return ptr;
+}
+
+/* Evaluate the likelihood of X being a base or index value, returning
+ positive if it is likely to be a base, negative if it is likely to be
+ an index, and 0 if we can't tell. Make the magnitude of the return
+ value reflect the amount of confidence we have in the answer.
+
+ MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */
+
+static int
+baseness (rtx x, enum machine_mode mode, addr_space_t as,
+ enum rtx_code outer_code, enum rtx_code index_code)
+{
+ /* See whether we can be certain. */
+ if (must_be_base_p (x))
+ return 3;
+ if (must_be_index_p (x))
+ return -3;
+
+ /* Believe *_POINTER unless the address shape requires otherwise. */
+ if (REG_P (x) && REG_POINTER (x))
+ return 2;
+ if (MEM_P (x) && MEM_POINTER (x))
+ return 2;
+
+ if (REG_P (x) && HARD_REGISTER_P (x))
+ {
+ /* X is a hard register. If it only fits one of the base
+ or index classes, choose that interpretation. */
+ int regno = REGNO (x);
+ bool base_p = ok_for_base_p_1 (regno, mode, as, outer_code, index_code);
+ bool index_p = REGNO_OK_FOR_INDEX_P (regno);
+ if (base_p != index_p)
+ return base_p ? 1 : -1;
+ }
+ return 0;
+}
+
+/* INFO->INNER describes a normal, non-automodified address.
+ Fill in the rest of INFO accordingly. */
+
+static void
+decompose_normal_address (struct address_info *info)
+{
+ /* Treat the address as the sum of up to four values. */
+ rtx *ops[4];
+ size_t n_ops = extract_plus_operands (info->inner, ops,
+ ops + ARRAY_SIZE (ops)) - ops;
+
+ /* If there is more than one component, any base component is in a PLUS. */
+ if (n_ops > 1)
+ info->base_outer_code = PLUS;
+
+ /* Separate the parts that contain a REG or MEM from those that don't.
+ Record the latter in INFO and leave the former in OPS. */
+ rtx *inner_ops[4];
+ size_t out = 0;
+ for (size_t in = 0; in < n_ops; ++in)
+ {
+ rtx *loc = ops[in];
+ rtx *inner = strip_address_mutations (loc);
+ if (CONSTANT_P (*inner))
+ set_address_disp (info, loc, inner);
+ else if (GET_CODE (*inner) == UNSPEC)
+ set_address_segment (info, loc, inner);
+ else
+ {
+ ops[out] = loc;
+ inner_ops[out] = inner;
+ ++out;
+ }
+ }
+
+ /* Classify the remaining OPS members as bases and indexes. */
+ if (out == 1)
+ {
+ /* Assume that the remaining value is a base unless the shape
+ requires otherwise. */
+ if (!must_be_index_p (*inner_ops[0]))
+ set_address_base (info, ops[0], inner_ops[0]);
+ else
+ set_address_index (info, ops[0], inner_ops[0]);
+ }
+ else if (out == 2)
+ {
+ /* In the event of a tie, assume the base comes first. */
+ if (baseness (*inner_ops[0], info->mode, info->as, PLUS,
+ GET_CODE (*ops[1]))
+ >= baseness (*inner_ops[1], info->mode, info->as, PLUS,
+ GET_CODE (*ops[0])))
+ {
+ set_address_base (info, ops[0], inner_ops[0]);
+ set_address_index (info, ops[1], inner_ops[1]);
+ }
+ else
+ {
+ set_address_base (info, ops[1], inner_ops[1]);
+ set_address_index (info, ops[0], inner_ops[0]);
+ }
+ }
+ else
+ gcc_assert (out == 0);
+}
+
+/* Describe address *LOC in *INFO. MODE is the mode of the addressed value,
+ or VOIDmode if not known. AS is the address space associated with LOC.
+ OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */
+
+void
+decompose_address (struct address_info *info, rtx *loc, enum machine_mode mode,
+ addr_space_t as, enum rtx_code outer_code)
+{
+ memset (info, 0, sizeof (*info));
+ info->mode = mode;
+ info->as = as;
+ info->addr_outer_code = outer_code;
+ info->outer = loc;
+ info->inner = strip_address_mutations (loc, &outer_code);
+ info->base_outer_code = outer_code;
+ switch (GET_CODE (*info->inner))
+ {
+ case PRE_DEC:
+ case PRE_INC:
+ case POST_DEC:
+ case POST_INC:
+ decompose_incdec_address (info);
+ break;
+
+ case PRE_MODIFY:
+ case POST_MODIFY:
+ decompose_automod_address (info);
+ break;
+
+ default:
+ decompose_normal_address (info);
+ break;
+ }
+}
+
+/* Describe address operand LOC in INFO. */
+
+void
+decompose_lea_address (struct address_info *info, rtx *loc)
+{
+ decompose_address (info, loc, VOIDmode, ADDR_SPACE_GENERIC, ADDRESS);
+}
+
+/* Describe the address of MEM X in INFO. */
+
+void
+decompose_mem_address (struct address_info *info, rtx x)
+{
+ gcc_assert (MEM_P (x));
+ decompose_address (info, &XEXP (x, 0), GET_MODE (x),
+ MEM_ADDR_SPACE (x), MEM);
+}
+
+/* Update INFO after a change to the address it describes. */
+
+void
+update_address (struct address_info *info)
+{
+ decompose_address (info, info->outer, info->mode, info->as,
+ info->addr_outer_code);
+}
+
+/* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is
+ more complicated than that. */
+
+HOST_WIDE_INT
+get_index_scale (const struct address_info *info)
+{
+ rtx index = *info->index;
+ if (GET_CODE (index) == MULT
+ && CONST_INT_P (XEXP (index, 1))
+ && info->index_term == &XEXP (index, 0))
+ return INTVAL (XEXP (index, 1));
+
+ if (GET_CODE (index) == ASHIFT
+ && CONST_INT_P (XEXP (index, 1))
+ && info->index_term == &XEXP (index, 0))
+ return (HOST_WIDE_INT) 1 << INTVAL (XEXP (index, 1));
+
+ if (info->index == info->index_term)
+ return 1;
+
+ return 0;
+}
+
+/* Return the "index code" of INFO, in the form required by
+ ok_for_base_p_1. */
+
+enum rtx_code
+get_index_code (const struct address_info *info)
+{
+ if (info->index)
+ return GET_CODE (*info->index);
+
+ if (info->disp)
+ return GET_CODE (*info->disp);
+
+ return SCRATCH;
+}
projects / platform / upstream / gcc48.git / blobdiff