-.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05)
+.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16)
.\"
.\" Standard preamble:
.\" ========================================================================
-.de Sh \" Subsection heading
-.br
-.if t .Sp
-.ne 5
-.PP
-\fB\\$1\fR
-.PP
-..
.de Sp \" Vertical space (when we can't use .PP)
.if t .sp .5v
.if n .sp
.el .ds Aq '
.\"
.\" If the F register is turned on, we'll generate index entries on stderr for
-.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index
+.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index
.\" entries marked with X<> in POD. Of course, you'll have to process the
.\" output yourself in some meaningful fashion.
.ie \nF \{\
.\" ========================================================================
.\"
.IX Title "GCC 1"
-.TH GCC 1 "2013-04-11" "gcc-4.7.3" "GNU"
+.TH GCC 1 "2013-05-31" "gcc-4.8.1" "GNU"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
.if n .ad l
.IX Header "SYNOPSIS"
gcc [\fB\-c\fR|\fB\-S\fR|\fB\-E\fR] [\fB\-std=\fR\fIstandard\fR]
[\fB\-g\fR] [\fB\-pg\fR] [\fB\-O\fR\fIlevel\fR]
- [\fB\-W\fR\fIwarn\fR...] [\fB\-pedantic\fR]
+ [\fB\-W\fR\fIwarn\fR...] [\fB\-Wpedantic\fR]
[\fB\-I\fR\fIdir\fR...] [\fB\-L\fR\fIdir\fR...]
[\fB\-D\fR\fImacro\fR[=\fIdefn\fR]...] [\fB\-U\fR\fImacro\fR]
[\fB\-f\fR\fIoption\fR...] [\fB\-m\fR\fImachine-option\fR...]
\&\fB\-W\fR\-\-\-for example,
\&\fB\-fmove\-loop\-invariants\fR, \fB\-Wformat\fR and so on. Most of
these have both positive and negative forms; the negative form of
-\&\fB\-ffoo\fR would be \fB\-fno\-foo\fR. This manual documents
+\&\fB\-ffoo\fR is \fB\-fno\-foo\fR. This manual documents
only one of these two forms, whichever one is not the default.
.SH "OPTIONS"
.IX Header "OPTIONS"
-.Sh "Option Summary"
+.SS "Option Summary"
.IX Subsection "Option Summary"
Here is a summary of all the options, grouped by type. Explanations are
in the following sections.
\&\-pipe \-pass\-exit\-codes
\&\-x\fR \fIlanguage\fR \fB\-v \-### \-\-help\fR[\fB=\fR\fIclass\fR[\fB,...\fR]] \fB\-\-target\-help
\&\-\-version \-wrapper @\fR\fIfile\fR \fB\-fplugin=\fR\fIfile\fR \fB\-fplugin\-arg\-\fR\fIname\fR\fB=\fR\fIarg\fR
-\&\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] \fB\-fdump\-go\-spec=\fR\fIfile\fR
+\&\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] \fB\-fada\-spec\-parent=\fR\fIarg\fR \fB\-fdump\-go\-spec=\fR\fIfile\fR
.IP "\fIC Language Options\fR" 4
.IX Item "C Language Options"
\&\fB\-ansi \-std=\fR\fIstandard\fR \fB\-fgnu89\-inline
\&\-aux\-info\fR \fIfilename\fR \fB\-fallow\-parameterless\-variadic\-functions
\&\-fno\-asm \-fno\-builtin \-fno\-builtin\-\fR\fIfunction\fR
\&\fB\-fhosted \-ffreestanding \-fopenmp \-fms\-extensions \-fplan9\-extensions
-\&\-trigraphs \-no\-integrated\-cpp \-traditional \-traditional\-cpp
+\&\-trigraphs \-traditional \-traditional\-cpp
\&\-fallow\-single\-precision \-fcond\-mismatch \-flax\-vector\-conversions
\&\-fsigned\-bitfields \-fsigned\-char
\&\-funsigned\-bitfields \-funsigned\-char\fR
.IP "\fI\*(C+ Language Options\fR" 4
.IX Item " Language Options"
\&\fB\-fabi\-version=\fR\fIn\fR \fB\-fno\-access\-control \-fcheck\-new
-\&\-fconserve\-space \-fconstexpr\-depth=\fR\fIn\fR \fB\-ffriend\-injection
+\&\-fconstexpr\-depth=\fR\fIn\fR \fB\-ffriend\-injection
\&\-fno\-elide\-constructors
\&\-fno\-enforce\-eh\-specs
\&\-ffor\-scope \-fno\-for\-scope \-fno\-gnu\-keywords
\&\-fno\-nonansi\-builtins \-fnothrow\-opt \-fno\-operator\-names
\&\-fno\-optional\-diags \-fpermissive
\&\-fno\-pretty\-templates
-\&\-frepo \-fno\-rtti \-fstats \-ftemplate\-depth=\fR\fIn\fR
+\&\-frepo \-fno\-rtti \-fstats \-ftemplate\-backtrace\-limit=\fR\fIn\fR
+\&\fB\-ftemplate\-depth=\fR\fIn\fR
\&\fB\-fno\-threadsafe\-statics \-fuse\-cxa\-atexit \-fno\-weak \-nostdinc++
\&\-fno\-default\-inline \-fvisibility\-inlines\-hidden
\&\-fvisibility\-ms\-compat
+\&\-fext\-numeric\-literals
\&\-Wabi \-Wconversion\-null \-Wctor\-dtor\-privacy
-\&\-Wdelete\-non\-virtual\-dtor \-Wnarrowing \-Wnoexcept
-\&\-Wnon\-virtual\-dtor \-Wreorder
+\&\-Wdelete\-non\-virtual\-dtor \-Wliteral\-suffix \-Wnarrowing
+\&\-Wnoexcept \-Wnon\-virtual\-dtor \-Wreorder
\&\-Weffc++ \-Wstrict\-null\-sentinel
\&\-Wno\-non\-template\-friend \-Wold\-style\-cast
\&\-Woverloaded\-virtual \-Wno\-pmf\-conversions
.IX Item "Language Independent Options"
\&\fB\-fmessage\-length=\fR\fIn\fR
\&\fB\-fdiagnostics\-show\-location=\fR[\fBonce\fR|\fBevery-line\fR]
-\&\fB\-fno\-diagnostics\-show\-option\fR
+\&\fB\-fno\-diagnostics\-show\-option \-fno\-diagnostics\-show\-caret\fR
.IP "\fIWarning Options\fR" 4
.IX Item "Warning Options"
-\&\fB\-fsyntax\-only \-fmax\-errors=\fR\fIn\fR \fB\-pedantic
+\&\fB\-fsyntax\-only \-fmax\-errors=\fR\fIn\fR \fB\-Wpedantic
\&\-pedantic\-errors
-\&\-w \-Wextra \-Wall \-Waddress \-Waggregate\-return \-Warray\-bounds
+\&\-w \-Wextra \-Wall \-Waddress \-Waggregate\-return
+\&\-Waggressive\-loop\-optimizations \-Warray\-bounds
\&\-Wno\-attributes \-Wno\-builtin\-macro\-redefined
\&\-Wc++\-compat \-Wc++11\-compat \-Wcast\-align \-Wcast\-qual
\&\-Wchar\-subscripts \-Wclobbered \-Wcomment
\&\-Winvalid\-pch \-Wlarger\-than=\fR\fIlen\fR \fB\-Wunsafe\-loop\-optimizations
\&\-Wlogical\-op \-Wlong\-long
\&\-Wmain \-Wmaybe\-uninitialized \-Wmissing\-braces \-Wmissing\-field\-initializers
-\&\-Wmissing\-format\-attribute \-Wmissing\-include\-dirs
+\&\-Wmissing\-include\-dirs
\&\-Wno\-mudflap
\&\-Wno\-multichar \-Wnonnull \-Wno\-overflow
\&\-Woverlength\-strings \-Wpacked \-Wpacked\-bitfield\-compat \-Wpadded
\&\-Wparentheses \-Wpedantic\-ms\-format \-Wno\-pedantic\-ms\-format
\&\-Wpointer\-arith \-Wno\-pointer\-to\-int\-cast
-\&\-Wredundant\-decls
+\&\-Wredundant\-decls \-Wno\-return\-local\-addr
\&\-Wreturn\-type \-Wsequence\-point \-Wshadow
-\&\-Wsign\-compare \-Wsign\-conversion \-Wstack\-protector
-\&\-Wstack\-usage=\fR\fIlen\fR \fB\-Wstrict\-aliasing \-Wstrict\-aliasing=n
-\&\-Wstrict\-overflow \-Wstrict\-overflow=\fR\fIn\fR
-\&\fB\-Wsuggest\-attribute=\fR[\fBpure\fR|\fBconst\fR|\fBnoreturn\fR]
-\&\fB\-Wswitch \-Wswitch\-default \-Wswitch\-enum \-Wsync\-nand
+\&\-Wsign\-compare \-Wsign\-conversion \-Wsizeof\-pointer\-memaccess
+\&\-Wstack\-protector \-Wstack\-usage=\fR\fIlen\fR \fB\-Wstrict\-aliasing
+\&\-Wstrict\-aliasing=n \-Wstrict\-overflow \-Wstrict\-overflow=\fR\fIn\fR
+\&\fB\-Wsuggest\-attribute=\fR[\fBpure\fR|\fBconst\fR|\fBnoreturn\fR|\fBformat\fR]
+\&\fB\-Wmissing\-format\-attribute
+\&\-Wswitch \-Wswitch\-default \-Wswitch\-enum \-Wsync\-nand
\&\-Wsystem\-headers \-Wtrampolines \-Wtrigraphs \-Wtype\-limits \-Wundef
\&\-Wuninitialized \-Wunknown\-pragmas \-Wno\-pragmas
\&\-Wunsuffixed\-float\-constants \-Wunused \-Wunused\-function
\&\-Wunused\-label \-Wunused\-local\-typedefs \-Wunused\-parameter
\&\-Wno\-unused\-result \-Wunused\-value \-Wunused\-variable
\&\-Wunused\-but\-set\-parameter \-Wunused\-but\-set\-variable
-\&\-Wvariadic\-macros \-Wvector\-operation\-performance \-Wvla
-\&\-Wvolatile\-register\-var \-Wwrite\-strings \-Wzero\-as\-null\-pointer\-constant\fR
+\&\-Wuseless\-cast \-Wvariadic\-macros \-Wvector\-operation\-performance
+\&\-Wvla \-Wvolatile\-register\-var \-Wwrite\-strings \-Wzero\-as\-null\-pointer\-constant\fR
.IP "\fIC and Objective-C-only Warning Options\fR" 4
.IX Item "C and Objective-C-only Warning Options"
\&\fB\-Wbad\-function\-cast \-Wmissing\-declarations
.IP "\fIDebugging Options\fR" 4
.IX Item "Debugging Options"
\&\fB\-d\fR\fIletters\fR \fB\-dumpspecs \-dumpmachine \-dumpversion
-\&\-fdbg\-cnt\-list \-fdbg\-cnt=\fR\fIcounter-value-list\fR
+\&\-fsanitize=\fR\fIstyle\fR
+\&\fB\-fdbg\-cnt\-list \-fdbg\-cnt=\fR\fIcounter-value-list\fR
\&\fB\-fdisable\-ipa\-\fR\fIpass_name\fR
\&\fB\-fdisable\-rtl\-\fR\fIpass_name\fR
\&\fB\-fdisable\-rtl\-\fR\fIpass-name\fR\fB=\fR\fIrange-list\fR
\&\-fdump\-tree\-all
\&\-fdump\-tree\-original\fR[\fB\-\fR\fIn\fR]
\&\fB\-fdump\-tree\-optimized\fR[\fB\-\fR\fIn\fR]
-\&\fB\-fdump\-tree\-cfg \-fdump\-tree\-vcg \-fdump\-tree\-alias
+\&\fB\-fdump\-tree\-cfg \-fdump\-tree\-alias
\&\-fdump\-tree\-ch
\&\-fdump\-tree\-ssa\fR[\fB\-\fR\fIn\fR] \fB\-fdump\-tree\-pre\fR[\fB\-\fR\fIn\fR]
\&\fB\-fdump\-tree\-ccp\fR[\fB\-\fR\fIn\fR] \fB\-fdump\-tree\-dce\fR[\fB\-\fR\fIn\fR]
\&\fB\-fdump\-tree\-storeccp\fR[\fB\-\fR\fIn\fR]
\&\fB\-fdump\-final\-insns=\fR\fIfile\fR
\&\fB\-fcompare\-debug\fR[\fB=\fR\fIopts\fR] \fB\-fcompare\-debug\-second
-\&\-feliminate\-dwarf2\-dups \-feliminate\-unused\-debug\-types
+\&\-feliminate\-dwarf2\-dups \-fno\-eliminate\-unused\-debug\-types
\&\-feliminate\-unused\-debug\-symbols \-femit\-class\-debug\-always
\&\-fenable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR
\&\fB\-fenable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR
-\&\fB\-fdebug\-types\-section
+\&\fB\-fdebug\-types\-section \-fmem\-report\-wpa
\&\-fmem\-report \-fpre\-ipa\-mem\-report \-fpost\-ipa\-mem\-report \-fprofile\-arcs
-\&\-frandom\-seed=\fR\fIstring\fR \fB\-fsched\-verbose=\fR\fIn\fR
+\&\-fopt\-info
+\&\-fopt\-info\-\fR\fIoptions\fR[\fB=\fR\fIfile\fR]
+\&\fB\-frandom\-seed=\fR\fIstring\fR \fB\-fsched\-verbose=\fR\fIn\fR
\&\fB\-fsel\-sched\-verbose \-fsel\-sched\-dump\-cfg \-fsel\-sched\-pipelining\-verbose
\&\-fstack\-usage \-ftest\-coverage \-ftime\-report \-fvar\-tracking
\&\-fvar\-tracking\-assignments \-fvar\-tracking\-assignments\-toggle
\&\-save\-temps \-save\-temps=cwd \-save\-temps=obj \-time\fR[\fB=\fR\fIfile\fR]
.IP "\fIOptimization Options\fR" 4
.IX Item "Optimization Options"
-\&\fB\-falign\-functions[=\fR\fIn\fR\fB] \-falign\-jumps[=\fR\fIn\fR\fB]
-\&\-falign\-labels[=\fR\fIn\fR\fB] \-falign\-loops[=\fR\fIn\fR\fB] \-fassociative\-math
-\&\-fauto\-inc\-dec \-fbranch\-probabilities \-fbranch\-target\-load\-optimize
-\&\-fbranch\-target\-load\-optimize2 \-fbtr\-bb\-exclusive \-fcaller\-saves
+\&\fB\-faggressive\-loop\-optimizations \-falign\-functions[=\fR\fIn\fR\fB]
+\&\-falign\-jumps[=\fR\fIn\fR\fB]
+\&\-falign\-labels[=\fR\fIn\fR\fB] \-falign\-loops[=\fR\fIn\fR\fB]
+\&\-fassociative\-math \-fauto\-inc\-dec \-fbranch\-probabilities
+\&\-fbranch\-target\-load\-optimize \-fbranch\-target\-load\-optimize2
+\&\-fbtr\-bb\-exclusive \-fcaller\-saves
\&\-fcheck\-data\-deps \-fcombine\-stack\-adjustments \-fconserve\-stack
\&\-fcompare\-elim \-fcprop\-registers \-fcrossjumping
\&\-fcse\-follow\-jumps \-fcse\-skip\-blocks \-fcx\-fortran\-rules
\&\-ffast\-math \-ffinite\-math\-only \-ffloat\-store \-fexcess\-precision=\fR\fIstyle\fR
\&\fB\-fforward\-propagate \-ffp\-contract=\fR\fIstyle\fR \fB\-ffunction\-sections
\&\-fgcse \-fgcse\-after\-reload \-fgcse\-las \-fgcse\-lm \-fgraphite\-identity
-\&\-fgcse\-sm \-fif\-conversion \-fif\-conversion2 \-findirect\-inlining
+\&\-fgcse\-sm \-fhoist\-adjacent\-loads \-fif\-conversion
+\&\-fif\-conversion2 \-findirect\-inlining
\&\-finline\-functions \-finline\-functions\-called\-once \-finline\-limit=\fR\fIn\fR
-\&\fB\-finline\-small\-functions \-fipa\-cp \-fipa\-cp\-clone \-fipa\-matrix\-reorg
+\&\fB\-finline\-small\-functions \-fipa\-cp \-fipa\-cp\-clone
\&\-fipa\-pta \-fipa\-profile \-fipa\-pure\-const \-fipa\-reference
\&\-fira\-algorithm=\fR\fIalgorithm\fR
-\&\fB\-fira\-region=\fR\fIregion\fR
-\&\fB\-fira\-loop\-pressure \-fno\-ira\-share\-save\-slots
+\&\fB\-fira\-region=\fR\fIregion\fR \fB\-fira\-hoist\-pressure
+\&\-fira\-loop\-pressure \-fno\-ira\-share\-save\-slots
\&\-fno\-ira\-share\-spill\-slots \-fira\-verbose=\fR\fIn\fR
\&\fB\-fivopts \-fkeep\-inline\-functions \-fkeep\-static\-consts
-\&\-floop\-block \-floop\-flatten \-floop\-interchange \-floop\-strip\-mine
+\&\-floop\-block \-floop\-interchange \-floop\-strip\-mine \-floop\-nest\-optimize
\&\-floop\-parallelize\-all \-flto \-flto\-compression\-level
\&\-flto\-partition=\fR\fIalg\fR \fB\-flto\-report \-fmerge\-all\-constants
\&\-fmerge\-constants \-fmodulo\-sched \-fmodulo\-sched\-allow\-regmoves
\&\-fno\-toplevel\-reorder \-fno\-trapping\-math \-fno\-zero\-initialized\-in\-bss
\&\-fomit\-frame\-pointer \-foptimize\-register\-move \-foptimize\-sibling\-calls
\&\-fpartial\-inlining \-fpeel\-loops \-fpredictive\-commoning
-\&\-fprefetch\-loop\-arrays
+\&\-fprefetch\-loop\-arrays \-fprofile\-report
\&\-fprofile\-correction \-fprofile\-dir=\fR\fIpath\fR \fB\-fprofile\-generate
\&\-fprofile\-generate=\fR\fIpath\fR
\&\fB\-fprofile\-use \-fprofile\-use=\fR\fIpath\fR \fB\-fprofile\-values
\&\-fsplit\-ivs\-in\-unroller \-fsplit\-wide\-types \-fstack\-protector
\&\-fstack\-protector\-all \-fstrict\-aliasing \-fstrict\-overflow
\&\-fthread\-jumps \-ftracer \-ftree\-bit\-ccp
-\&\-ftree\-builtin\-call\-dce \-ftree\-ccp \-ftree\-ch \-ftree\-copy\-prop
+\&\-ftree\-builtin\-call\-dce \-ftree\-ccp \-ftree\-ch
+\&\-ftree\-coalesce\-inline\-vars \-ftree\-coalesce\-vars \-ftree\-copy\-prop
\&\-ftree\-copyrename \-ftree\-dce \-ftree\-dominator\-opts \-ftree\-dse
\&\-ftree\-forwprop \-ftree\-fre \-ftree\-loop\-if\-convert
\&\-ftree\-loop\-if\-convert\-stores \-ftree\-loop\-im
\&\-ftree\-phiprop \-ftree\-loop\-distribution \-ftree\-loop\-distribute\-patterns
\&\-ftree\-loop\-ivcanon \-ftree\-loop\-linear \-ftree\-loop\-optimize
-\&\-ftree\-parallelize\-loops=\fR\fIn\fR \fB\-ftree\-pre \-ftree\-pta \-ftree\-reassoc
-\&\-ftree\-sink \-ftree\-sra \-ftree\-switch\-conversion \-ftree\-tail\-merge
+\&\-ftree\-parallelize\-loops=\fR\fIn\fR \fB\-ftree\-pre \-ftree\-partial\-pre \-ftree\-pta
+\&\-ftree\-reassoc \-ftree\-sink \-ftree\-slsr \-ftree\-sra
+\&\-ftree\-switch\-conversion \-ftree\-tail\-merge
\&\-ftree\-ter \-ftree\-vect\-loop\-version \-ftree\-vectorize \-ftree\-vrp
\&\-funit\-at\-a\-time \-funroll\-all\-loops \-funroll\-loops
\&\-funsafe\-loop\-optimizations \-funsafe\-math\-optimizations \-funswitch\-loops
\&\-fvariable\-expansion\-in\-unroller \-fvect\-cost\-model \-fvpt \-fweb
-\&\-fwhole\-program \-fwpa \-fuse\-linker\-plugin
+\&\-fwhole\-program \-fwpa \-fuse\-ld=\fR\fIlinker\fR \fB\-fuse\-linker\-plugin
\&\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR
-\&\fB\-O \-O0 \-O1 \-O2 \-O3 \-Os \-Ofast\fR
+\&\fB\-O \-O0 \-O1 \-O2 \-O3 \-Os \-Ofast \-Og\fR
.IP "\fIPreprocessor Options\fR" 4
.IX Item "Preprocessor Options"
\&\fB\-A\fR\fIquestion\fR\fB=\fR\fIanswer\fR
\&\fB\-M \-MM \-MF \-MG \-MP \-MQ \-MT \-nostdinc
\&\-P \-fdebug\-cpp \-ftrack\-macro\-expansion \-fworking\-directory
\&\-remap \-trigraphs \-undef \-U\fR\fImacro\fR
-\&\fB\-Wp,\fR\fIoption\fR \fB\-Xpreprocessor\fR \fIoption\fR
+\&\fB\-Wp,\fR\fIoption\fR \fB\-Xpreprocessor\fR \fIoption\fR \fB\-no\-integrated\-cpp\fR
.IP "\fIAssembler Option\fR" 4
.IX Item "Assembler Option"
\&\fB\-Wa,\fR\fIoption\fR \fB\-Xassembler\fR \fIoption\fR
.IX Item "Linker Options"
\&\fIobject-file-name\fR \fB\-l\fR\fIlibrary\fR
\&\fB\-nostartfiles \-nodefaultlibs \-nostdlib \-pie \-rdynamic
-\&\-s \-static \-static\-libgcc \-static\-libstdc++ \-shared
-\&\-shared\-libgcc \-symbolic
+\&\-s \-static \-static\-libgcc \-static\-libstdc++
+\&\-static\-libasan \-static\-libtsan
+\&\-shared \-shared\-libgcc \-symbolic
\&\-T\fR \fIscript\fR \fB\-Wl,\fR\fIoption\fR \fB\-Xlinker\fR \fIoption\fR
\&\fB\-u\fR \fIsymbol\fR
.IP "\fIDirectory Options\fR" 4
.IX Item "Directory Options"
\&\fB\-B\fR\fIprefix\fR \fB\-I\fR\fIdir\fR \fB\-iplugindir=\fR\fIdir\fR
\&\fB\-iquote\fR\fIdir\fR \fB\-L\fR\fIdir\fR \fB\-specs=\fR\fIfile\fR \fB\-I\-
-\&\-\-sysroot=\fR\fIdir\fR
+\&\-\-sysroot=\fR\fIdir\fR \fB\-\-no\-sysroot\-suffix\fR
.IP "\fIMachine Dependent Options\fR" 4
.IX Item "Machine Dependent Options"
+\&\fIAArch64 Options\fR
+\&\fB\-mbig\-endian \-mlittle\-endian
+\&\-mgeneral\-regs\-only
+\&\-mcmodel=tiny \-mcmodel=small \-mcmodel=large
+\&\-mstrict\-align
+\&\-momit\-leaf\-frame\-pointer \-mno\-omit\-leaf\-frame\-pointer
+\&\-mtls\-dialect=desc \-mtls\-dialect=traditional
+\&\-march=\fR\fIname\fR \fB\-mcpu=\fR\fIname\fR \fB\-mtune=\fR\fIname\fR
+.Sp
\&\fIAdapteva Epiphany Options\fR
\&\fB\-mhalf\-reg\-file \-mprefer\-short\-insn\-regs
\&\-mbranch\-cost=\fR\fInum\fR \fB\-mcmove \-mnops=\fR\fInum\fR \fB\-msoft\-cmpsf
\&\-mapcs\-reentrant \-mno\-apcs\-reentrant
\&\-msched\-prolog \-mno\-sched\-prolog
\&\-mlittle\-endian \-mbig\-endian \-mwords\-little\-endian
-\&\-mfloat\-abi=\fR\fIname\fR \fB\-mfpe
-\&\-mfp16\-format=\fR\fIname\fR
+\&\-mfloat\-abi=\fR\fIname\fR
+\&\fB\-mfp16\-format=\fR\fIname\fR
\&\fB\-mthumb\-interwork \-mno\-thumb\-interwork
\&\-mcpu=\fR\fIname\fR \fB\-march=\fR\fIname\fR \fB\-mfpu=\fR\fIname\fR
\&\fB\-mstructure\-size\-boundary=\fR\fIn\fR
\&\-msingle\-pic\-base \-mno\-single\-pic\-base
\&\-mpic\-register=\fR\fIreg\fR
\&\fB\-mnop\-fun\-dllimport
-\&\-mcirrus\-fix\-invalid\-insns \-mno\-cirrus\-fix\-invalid\-insns
\&\-mpoke\-function\-name
\&\-mthumb \-marm
\&\-mtpcs\-frame \-mtpcs\-leaf\-frame
.Sp
\&\fI\s-1AVR\s0 Options\fR
\&\fB\-mmcu=\fR\fImcu\fR \fB\-maccumulate\-args \-mbranch\-cost=\fR\fIcost\fR
-\&\fB\-mcall\-prologues \-mint8 \-mno\-interrupts \-mrelax \-mshort\-calls
-\&\-mstrict\-X \-mtiny\-stack\fR
+\&\fB\-mcall\-prologues \-mint8 \-mno\-interrupts \-mrelax
+\&\-mstrict\-X \-mtiny\-stack \-Waddr\-space\-convert\fR
.Sp
\&\fIBlackfin Options\fR
\&\fB\-mcpu=\fR\fIcpu\fR[\fB\-\fR\fIsirevision\fR]
\&\fB\-mkernel \-mone\-byte\-bool\fR
.Sp
\&\fI\s-1DEC\s0 Alpha Options\fR
-\&\fB\-mno\-fp\-regs \-msoft\-float \-malpha\-as \-mgas
+\&\fB\-mno\-fp\-regs \-msoft\-float
\&\-mieee \-mieee\-with\-inexact \-mieee\-conformant
\&\-mfp\-trap\-mode=\fR\fImode\fR \fB\-mfp\-rounding\-mode=\fR\fImode\fR
\&\fB\-mtrap\-precision=\fR\fImode\fR \fB\-mbuild\-constants
\&\-msmall\-text \-mlarge\-text
\&\-mmemory\-latency=\fR\fItime\fR
.Sp
-\&\fI\s-1DEC\s0 Alpha/VMS Options\fR
-\&\fB\-mvms\-return\-codes \-mdebug\-main=\fR\fIprefix\fR \fB\-mmalloc64\fR
-.Sp
\&\fI\s-1FR30\s0 Options\fR
\&\fB\-msmall\-model \-mno\-lsim\fR
.Sp
\&\-tno\-android\-cc \-tno\-android\-ld\fR
.Sp
\&\fIH8/300 Options\fR
-\&\fB\-mrelax \-mh \-ms \-mn \-mint32 \-malign\-300\fR
+\&\fB\-mrelax \-mh \-ms \-mn \-mexr \-mno\-exr \-mint32 \-malign\-300\fR
.Sp
\&\fI\s-1HPPA\s0 Options\fR
\&\fB\-march=\fR\fIarchitecture-type\fR
\&\-mmmx \-msse \-msse2 \-msse3 \-mssse3 \-msse4.1 \-msse4.2 \-msse4 \-mavx
\&\-mavx2 \-maes \-mpclmul \-mfsgsbase \-mrdrnd \-mf16c \-mfma
\&\-msse4a \-m3dnow \-mpopcnt \-mabm \-mbmi \-mtbm \-mfma4 \-mxop \-mlzcnt
-\&\-mbmi2 \-mlwp \-mthreads \-mno\-align\-stringops \-minline\-all\-stringops
+\&\-mbmi2 \-mrtm \-mlwp \-mthreads
+\&\-mno\-align\-stringops \-minline\-all\-stringops
\&\-minline\-stringops\-dynamically \-mstringop\-strategy=\fR\fIalg\fR
\&\fB\-mpush\-args \-maccumulate\-outgoing\-args \-m128bit\-long\-double
-\&\-m96bit\-long\-double \-mregparm=\fR\fInum\fR \fB\-msseregparm
+\&\-m96bit\-long\-double \-mlong\-double\-64 \-mlong\-double\-80
+\&\-mregparm=\fR\fInum\fR \fB\-msseregparm
\&\-mveclibabi=\fR\fItype\fR \fB\-mvect8\-ret\-in\-mem
\&\-mpc32 \-mpc64 \-mpc80 \-mstackrealign
\&\-momit\-leaf\-frame\-pointer \-mno\-red\-zone \-mno\-tls\-direct\-seg\-refs
-\&\-mcmodel=\fR\fIcode-model\fR \fB\-mabi=\fR\fIname\fR
+\&\-mcmodel=\fR\fIcode-model\fR \fB\-mabi=\fR\fIname\fR \fB\-maddress\-mode=\fR\fImode\fR
\&\fB\-m32 \-m64 \-mx32 \-mlarge\-data\-threshold=\fR\fInum\fR
\&\fB\-msse2avx \-mfentry \-m8bit\-idiv
\&\-mavx256\-split\-unaligned\-load \-mavx256\-split\-unaligned\-store\fR
\&\-msel\-sched\-dont\-check\-control\-spec \-msched\-fp\-mem\-deps\-zero\-cost
\&\-msched\-max\-memory\-insns\-hard\-limit \-msched\-max\-memory\-insns=\fR\fImax-insns\fR
.Sp
-\&\fI\s-1IA\-64/VMS\s0 Options\fR
-\&\fB\-mvms\-return\-codes \-mdebug\-main=\fR\fIprefix\fR \fB\-mmalloc64\fR
-.Sp
\&\fI\s-1LM32\s0 Options\fR
\&\fB\-mbarrel\-shift\-enabled \-mdivide\-enabled \-mmultiply\-enabled
\&\-msign\-extend\-enabled \-muser\-enabled\fR
\&\fB\-mmemcpy \-mxl\-soft\-mul \-mxl\-soft\-div \-mxl\-barrel\-shift
\&\-mxl\-pattern\-compare \-mxl\-stack\-check \-mxl\-gp\-opt \-mno\-clearbss
\&\-mxl\-multiply\-high \-mxl\-float\-convert \-mxl\-float\-sqrt
-\&\-mxl\-mode\-\fR\fIapp-model\fR
+\&\-mbig\-endian \-mlittle\-endian \-mxl\-reorder \-mxl\-mode\-\fR\fIapp-model\fR
.Sp
\&\fI\s-1MIPS\s0 Options\fR
\&\fB\-EL \-EB \-march=\fR\fIarch\fR \fB\-mtune=\fR\fIarch\fR
\&\-mabi=\fR\fIabi\fR \fB\-mabicalls \-mno\-abicalls
\&\-mshared \-mno\-shared \-mplt \-mno\-plt \-mxgot \-mno\-xgot
\&\-mgp32 \-mgp64 \-mfp32 \-mfp64 \-mhard\-float \-msoft\-float
-\&\-msingle\-float \-mdouble\-float \-mdsp \-mno\-dsp \-mdspr2 \-mno\-dspr2
+\&\-mno\-float \-msingle\-float \-mdouble\-float
+\&\-mdsp \-mno\-dsp \-mdspr2 \-mno\-dspr2
+\&\-mmcu \-mmno\-mcu
\&\-mfpu=\fR\fIfpu-type\fR
\&\fB\-msmartmips \-mno\-smartmips
\&\-mpaired\-single \-mno\-paired\-single \-mdmx \-mno\-mdmx
\&\fB\-mreturn\-pointer\-on\-d0
\&\-mno\-crt0 \-mrelax \-mliw \-msetlb\fR
.Sp
+\&\fIMoxie Options\fR
+\&\fB\-meb \-mel \-mno\-crt0\fR
+.Sp
\&\fI\s-1PDP\-11\s0 Options\fR
\&\fB\-mfpu \-msoft\-float \-mac0 \-mno\-ac0 \-m40 \-m45 \-m10
\&\-mbcopy \-mbcopy\-builtin \-mint32 \-mno\-int16
\&\fB\-mcpu=\fR\fIcpu-type\fR
\&\fB\-mtune=\fR\fIcpu-type\fR
\&\fB\-mcmodel=\fR\fIcode-model\fR
-\&\fB\-mpower \-mno\-power \-mpower2 \-mno\-power2
-\&\-mpowerpc \-mpowerpc64 \-mno\-powerpc
+\&\fB\-mpowerpc64
\&\-maltivec \-mno\-altivec
\&\-mpowerpc\-gpopt \-mno\-powerpc\-gpopt
\&\-mpowerpc\-gfxopt \-mno\-powerpc\-gfxopt
\&\-mmfcrf \-mno\-mfcrf \-mpopcntb \-mno\-popcntb \-mpopcntd \-mno\-popcntd
\&\-mfprnd \-mno\-fprnd
\&\-mcmpb \-mno\-cmpb \-mmfpgpr \-mno\-mfpgpr \-mhard\-dfp \-mno\-hard\-dfp
-\&\-mnew\-mnemonics \-mold\-mnemonics
\&\-mfull\-toc \-mminimal\-toc \-mno\-fp\-in\-toc \-mno\-sum\-in\-toc
\&\-m64 \-m32 \-mxl\-compat \-mno\-xl\-compat \-mpe
\&\-malign\-power \-malign\-natural
\&\-mmax\-constant\-size=
\&\-mint\-register=
\&\-mpid
+\&\-mno\-warn\-multiple\-fast\-interrupts
\&\-msave\-acc\-in\-interrupts\fR
.Sp
\&\fIS/390 and zSeries Options\fR
\&\-mieee \-mno\-ieee \-mbitops \-misize \-minline\-ic_invalidate \-mpadstruct
\&\-mspace \-mprefergot \-musermode \-multcost=\fR\fInumber\fR \fB\-mdiv=\fR\fIstrategy\fR
\&\fB\-mdivsi3_libfunc=\fR\fIname\fR \fB\-mfixed\-range=\fR\fIregister-range\fR
-\&\fB\-madjust\-unroll \-mindexed\-addressing \-mgettrcost=\fR\fInumber\fR \fB\-mpt\-fixed
-\&\-maccumulate\-outgoing\-args \-minvalid\-symbols \-msoft\-atomic
-\&\-mbranch\-cost=\fR\fInum\fR \fB\-mcbranchdi \-mcmpeqdi \-mfused\-madd \-mpretend\-cmove\fR
+\&\fB\-mindexed\-addressing \-mgettrcost=\fR\fInumber\fR \fB\-mpt\-fixed
+\&\-maccumulate\-outgoing\-args \-minvalid\-symbols
+\&\-matomic\-model=\fR\fIatomic-model\fR
+\&\fB\-mbranch\-cost=\fR\fInum\fR \fB\-mzdcbranch \-mno\-zdcbranch \-mcbranchdi \-mcmpeqdi
+\&\-mfused\-madd \-mno\-fused\-madd \-mfsca \-mno\-fsca \-mfsrra \-mno\-fsrra
+\&\-mpretend\-cmove \-mtas\fR
.Sp
\&\fISolaris 2 Options\fR
\&\fB\-mimpure\-text \-mno\-impure\-text
\&\-munaligned\-doubles \-mno\-unaligned\-doubles
\&\-mv8plus \-mno\-v8plus \-mvis \-mno\-vis
\&\-mvis2 \-mno\-vis2 \-mvis3 \-mno\-vis3
+\&\-mcbcond \-mno\-cbcond
\&\-mfmaf \-mno\-fmaf \-mpopc \-mno\-popc
\&\-mfix\-at697f\fR
.Sp
\&\fB\-Qy \-Qn \-YP,\fR\fIpaths\fR \fB\-Ym,\fR\fIdir\fR
.Sp
\&\fITILE-Gx Options\fR
-\&\fB\-mcpu=\fR\fIcpu\fR \fB\-m32 \-m64\fR
+\&\fB\-mcpu=\fR\fIcpu\fR \fB\-m32 \-m64 \-mcmodel=\fR\fIcode-model\fR
.Sp
\&\fITILEPro Options\fR
\&\fB\-mcpu=\fR\fIcpu\fR \fB\-m32\fR
\&\-mtda=\fR\fIn\fR \fB\-msda=\fR\fIn\fR \fB\-mzda=\fR\fIn\fR
\&\fB\-mapp\-regs \-mno\-app\-regs
\&\-mdisable\-callt \-mno\-disable\-callt
-\&\-mv850e2v3
-\&\-mv850e2
-\&\-mv850e1 \-mv850es
-\&\-mv850e
-\&\-mv850 \-mbig\-switch\fR
+\&\-mv850e2v3 \-mv850e2 \-mv850e1 \-mv850es
+\&\-mv850e \-mv850 \-mv850e3v5
+\&\-mloop
+\&\-mrelax
+\&\-mlong\-jumps
+\&\-msoft\-float
+\&\-mhard\-float
+\&\-mgcc\-abi
+\&\-mrh850\-abi
+\&\-mbig\-switch\fR
.Sp
\&\fI\s-1VAX\s0 Options\fR
\&\fB\-mg \-mgnu \-munix\fR
.Sp
+\&\fI\s-1VMS\s0 Options\fR
+\&\fB\-mvms\-return\-codes \-mdebug\-main=\fR\fIprefix\fR \fB\-mmalloc64
+\&\-mpointer\-size=\fR\fIsize\fR
+.Sp
\&\fIVxWorks Options\fR
\&\fB\-mrtp \-non\-static \-Bstatic \-Bdynamic
\&\-Xbind\-lazy \-Xbind\-now\fR
.IX Item "Code Generation Options"
\&\fB\-fcall\-saved\-\fR\fIreg\fR \fB\-fcall\-used\-\fR\fIreg\fR
\&\fB\-ffixed\-\fR\fIreg\fR \fB\-fexceptions
-\&\-fnon\-call\-exceptions \-funwind\-tables
+\&\-fnon\-call\-exceptions \-fdelete\-dead\-exceptions \-funwind\-tables
\&\-fasynchronous\-unwind\-tables
\&\-finhibit\-size\-directive \-finstrument\-functions
\&\-finstrument\-functions\-exclude\-function\-list=\fR\fIsym\fR\fB,\fR\fIsym\fR\fB,...
\&\-fstack\-limit\-register=\fR\fIreg\fR \fB\-fstack\-limit\-symbol=\fR\fIsym\fR
\&\fB\-fno\-stack\-limit \-fsplit\-stack
\&\-fleading\-underscore \-ftls\-model=\fR\fImodel\fR
+\&\fB\-fstack\-reuse=\fR\fIreuse_level\fR
\&\fB\-ftrapv \-fwrapv \-fbounds\-check
-\&\-fvisibility \-fstrict\-volatile\-bitfields\fR
-.Sh "Options Controlling the Kind of Output"
+\&\-fvisibility \-fstrict\-volatile\-bitfields \-fsync\-libcalls\fR
+.SS "Options Controlling the Kind of Output"
.IX Subsection "Options Controlling the Kind of Output"
Compilation can involve up to four stages: preprocessing, compilation
proper, assembly and linking, always in that order. \s-1GCC\s0 is capable of
has not been used at all).
.IP "\fB\-pass\-exit\-codes\fR" 4
.IX Item "-pass-exit-codes"
-Normally the \fBgcc\fR program will exit with the code of 1 if any
+Normally the \fBgcc\fR program exits with the code of 1 if any
phase of the compiler returns a non-success return code. If you specify
-\&\fB\-pass\-exit\-codes\fR, the \fBgcc\fR program will instead return with
-numerically highest error produced by any phase that returned an error
-indication. The C, \*(C+, and Fortran frontends return 4, if an internal
+\&\fB\-pass\-exit\-codes\fR, the \fBgcc\fR program instead returns with
+the numerically highest error produced by any phase returning an error
+indication. The C, \*(C+, and Fortran front ends return 4 if an internal
compiler error is encountered.
.PP
If you only want some of the stages of compilation, you can use
Input files that don't require preprocessing are ignored.
.IP "\fB\-o\fR \fIfile\fR" 4
.IX Item "-o file"
-Place output in file \fIfile\fR. This applies regardless to whatever
+Place output in file \fIfile\fR. This applies to whatever
sort of output is being produced, whether it be an executable file,
an object file, an assembler file or preprocessed C code.
.Sp
.IX Item "--help"
Print (on the standard output) a description of the command-line options
understood by \fBgcc\fR. If the \fB\-v\fR option is also specified
-then \fB\-\-help\fR will also be passed on to the various processes
+then \fB\-\-help\fR is also passed on to the various processes
invoked by \fBgcc\fR, so that they can display the command-line options
they accept. If the \fB\-Wextra\fR option has also been specified
(prior to the \fB\-\-help\fR option), then command-line options that
-have no documentation associated with them will also be displayed.
+have no documentation associated with them are also displayed.
.IP "\fB\-\-target\-help\fR" 4
.IX Item "--target-help"
Print (on the standard output) a description of target-specific command-line
.RS 4
.IP "\fBoptimizers\fR" 4
.IX Item "optimizers"
-This will display all of the optimization options supported by the
+Display all of the optimization options supported by the
compiler.
.IP "\fBwarnings\fR" 4
.IX Item "warnings"
-This will display all of the options controlling warning messages
+Display all of the options controlling warning messages
produced by the compiler.
.IP "\fBtarget\fR" 4
.IX Item "target"
-This will display target-specific options. Unlike the
+Display target-specific options. Unlike the
\&\fB\-\-target\-help\fR option however, target-specific options of the
-linker and assembler will not be displayed. This is because those
+linker and assembler are not displayed. This is because those
tools do not currently support the extended \fB\-\-help=\fR syntax.
.IP "\fBparams\fR" 4
.IX Item "params"
-This will display the values recognized by the \fB\-\-param\fR
+Display the values recognized by the \fB\-\-param\fR
option.
.IP "\fIlanguage\fR" 4
.IX Item "language"
-This will display the options supported for \fIlanguage\fR, where
+Display the options supported for \fIlanguage\fR, where
\&\fIlanguage\fR is the name of one of the languages supported in this
version of \s-1GCC\s0.
.IP "\fBcommon\fR" 4
.IX Item "common"
-This will display the options that are common to all languages.
+Display the options that are common to all languages.
.RE
.RS 4
.Sp
.RS 4
.Sp
Thus for example to display all the undocumented target-specific
-switches supported by the compiler the following can be used:
+switches supported by the compiler, use:
.Sp
.Vb 1
\& \-\-help=target,undocumented
qualifiers.
.Sp
Combining several classes is possible, although this usually
-restricts the output by so much that there is nothing to display. One
-case where it does work however is when one of the classes is
-\&\fItarget\fR. So for example to display all the target-specific
-optimization options the following can be used:
+restricts the output so much that there is nothing to display. One
+case where it does work, however, is when one of the classes is
+\&\fItarget\fR. For example, to display all the target-specific
+optimization options, use:
.Sp
.Vb 1
\& \-\-help=target,optimizers
.Ve
.Sp
The \fB\-\-help=\fR option can be repeated on the command line. Each
-successive use will display its requested class of options, skipping
+successive use displays its requested class of options, skipping
those that have already been displayed.
.Sp
If the \fB\-Q\fR option appears on the command line before the
\& gcc \-c t.c \-wrapper gdb,\-\-args
.Ve
.Sp
-This will invoke all subprograms of \fBgcc\fR under
-\&\fBgdb \-\-args\fR, thus the invocation of \fBcc1\fR will be
+This invokes all subprograms of \fBgcc\fR under
+\&\fBgdb \-\-args\fR, thus the invocation of \fBcc1\fR is
\&\fBgdb \-\-args cc1 ...\fR.
.IP "\fB\-fplugin=\fR\fIname\fR\fB.so\fR" 4
.IX Item "-fplugin=name.so"
backslash) may be included by prefixing the character to be included
with a backslash. The \fIfile\fR may itself contain additional
@\fIfile\fR options; any such options will be processed recursively.
-.Sh "Compiling \*(C+ Programs"
+.SS "Compiling \*(C+ Programs"
.IX Subsection "Compiling Programs"
\&\*(C+ source files conventionally use one of the suffixes \fB.C\fR,
\&\fB.cc\fR, \fB.cpp\fR, \fB.CPP\fR, \fB.c++\fR, \fB.cp\fR, or
with the name \fBgcc\fR).
.PP
However, the use of \fBgcc\fR does not add the \*(C+ library.
-\&\fBg++\fR is a program that calls \s-1GCC\s0 and treats \fB.c\fR,
+\&\fBg++\fR is a program that calls \s-1GCC\s0 and automatically specifies linking
+against the \*(C+ library. It treats \fB.c\fR,
\&\fB.h\fR and \fB.i\fR files as \*(C+ source files instead of C source
-files unless \fB\-x\fR is used, and automatically specifies linking
-against the \*(C+ library. This program is also useful when
+files unless \fB\-x\fR is used. This program is also useful when
precompiling a C header file with a \fB.h\fR extension for use in \*(C+
compilations. On many systems, \fBg++\fR is also installed with
the name \fBc++\fR.
command-line options that you use for compiling programs in any
language; or command-line options meaningful for C and related
languages; or options that are meaningful only for \*(C+ programs.
-.Sh "Options Controlling C Dialect"
+.SS "Options Controlling C Dialect"
.IX Subsection "Options Controlling C Dialect"
The following options control the dialect of C (or languages derived
from C, such as \*(C+, Objective-C and Objective\-\*(C+) that the compiler
without \fB\-ansi\fR.
.Sp
The \fB\-ansi\fR option does not cause non-ISO programs to be
-rejected gratuitously. For that, \fB\-pedantic\fR is required in
+rejected gratuitously. For that, \fB\-Wpedantic\fR is required in
addition to \fB\-ansi\fR.
.Sp
The macro \f(CW\*(C`_\|_STRICT_ANSI_\|_\*(C'\fR is predefined when the \fB\-ansi\fR
\&\s-1ISO\s0 standard doesn't call for; this is to avoid interfering with any
programs that might use these names for other things.
.Sp
-Functions that would normally be built in but do not have semantics
+Functions that are normally built in but do not have semantics
defined by \s-1ISO\s0 C (such as \f(CW\*(C`alloca\*(C'\fR and \f(CW\*(C`ffs\*(C'\fR) are not built-in
functions when \fB\-ansi\fR is used.
.IP "\fB\-std=\fR" 4
.Sp
The compiler can accept several base standards, such as \fBc90\fR or
\&\fBc++98\fR, and \s-1GNU\s0 dialects of those standards, such as
-\&\fBgnu90\fR or \fBgnu++98\fR. By specifying a base standard, the
-compiler will accept all programs following that standard and those
+\&\fBgnu90\fR or \fBgnu++98\fR. When a base standard is specified, the
+compiler accepts all programs following that standard plus those
using \s-1GNU\s0 extensions that do not contradict it. For example,
\&\fB\-std=c90\fR turns off certain features of \s-1GCC\s0 that are
incompatible with \s-1ISO\s0 C90, such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR
keywords, but not other \s-1GNU\s0 extensions that do not have a meaning in
\&\s-1ISO\s0 C90, such as omitting the middle term of a \f(CW\*(C`?:\*(C'\fR
-expression. On the other hand, by specifying a \s-1GNU\s0 dialect of a
-standard, all features the compiler support are enabled, even when
-those features change the meaning of the base standard and some
+expression. On the other hand, when a \s-1GNU\s0 dialect of a standard is
+specified, all features supported by the compiler are enabled, even when
+those features change the meaning of the base standard. As a result, some
strict-conforming programs may be rejected. The particular standard
-is used by \fB\-pedantic\fR to identify which features are \s-1GNU\s0
+is used by \fB\-Wpedantic\fR to identify which features are \s-1GNU\s0
extensions given that version of the standard. For example
-\&\fB\-std=gnu90 \-pedantic\fR would warn about \*(C+ style \fB//\fR
-comments, while \fB\-std=gnu99 \-pedantic\fR would not.
+\&\fB\-std=gnu90 \-Wpedantic\fR warns about \*(C+ style \fB//\fR
+comments, while \fB\-std=gnu99 \-Wpedantic\fR does not.
.Sp
A value for this option must be provided; possible values are
.RS 4
.IX Item "iso9899:199x"
.PD
\&\s-1ISO\s0 C99. Note that this standard is not yet fully supported; see
-<\fBhttp://gcc.gnu.org/gcc\-4.7/c99status.html\fR> for more information. The
+<\fBhttp://gcc.gnu.org/c99status.html\fR> for more information. The
names \fBc9x\fR and \fBiso9899:199x\fR are deprecated.
.IP "\fBc11\fR" 4
.IX Item "c11"
name \fBgnu1x\fR is deprecated.
.IP "\fBc++98\fR" 4
.IX Item "c++98"
-The 1998 \s-1ISO\s0 \*(C+ standard plus amendments. Same as \fB\-ansi\fR for
-\&\*(C+ code.
+.PD 0
+.IP "\fBc++03\fR" 4
+.IX Item "c++03"
+.PD
+The 1998 \s-1ISO\s0 \*(C+ standard plus the 2003 technical corrigendum and some
+additional defect reports. Same as \fB\-ansi\fR for \*(C+ code.
.IP "\fBgnu++98\fR" 4
.IX Item "gnu++98"
+.PD 0
+.IP "\fBgnu++03\fR" 4
+.IX Item "gnu++03"
+.PD
\&\s-1GNU\s0 dialect of \fB\-std=c++98\fR. This is the default for
\&\*(C+ code.
.IP "\fBc++11\fR" 4
.IX Item "c++11"
+.PD 0
+.IP "\fBc++0x\fR" 4
+.IX Item "c++0x"
+.PD
The 2011 \s-1ISO\s0 \*(C+ standard plus amendments. Support for \*(C+11 is still
experimental, and may change in incompatible ways in future releases.
+The name \fBc++0x\fR is deprecated.
.IP "\fBgnu++11\fR" 4
.IX Item "gnu++11"
+.PD 0
+.IP "\fBgnu++0x\fR" 4
+.IX Item "gnu++0x"
+.PD
\&\s-1GNU\s0 dialect of \fB\-std=c++11\fR. Support for \*(C+11 is still
experimental, and may change in incompatible ways in future releases.
+The name \fBgnu++0x\fR is deprecated.
+.IP "\fBc++1y\fR" 4
+.IX Item "c++1y"
+The next revision of the \s-1ISO\s0 \*(C+ standard, tentatively planned for
+2017. Support is highly experimental, and will almost certainly
+change in incompatible ways in future releases.
+.IP "\fBgnu++1y\fR" 4
+.IX Item "gnu++1y"
+\&\s-1GNU\s0 dialect of \fB\-std=c++1y\fR. Support is highly experimental,
+and will almost certainly change in incompatible ways in future
+releases.
.RE
.RS 4
.RE
that function, or to generate more efficient code, even if the
resulting code still contains calls to that function. For example,
warnings are given with \fB\-Wformat\fR for bad calls to
-\&\f(CW\*(C`printf\*(C'\fR, when \f(CW\*(C`printf\*(C'\fR is built in, and \f(CW\*(C`strlen\*(C'\fR is
+\&\f(CW\*(C`printf\*(C'\fR when \f(CW\*(C`printf\*(C'\fR is built in and \f(CW\*(C`strlen\*(C'\fR is
known not to modify global memory.
.Sp
With the \fB\-fno\-builtin\-\fR\fIfunction\fR option
.Ve
.IP "\fB\-fhosted\fR" 4
.IX Item "-fhosted"
-Assert that compilation takes place in a hosted environment. This implies
+Assert that compilation targets a hosted environment. This implies
\&\fB\-fbuiltin\fR. A hosted environment is one in which the
entire standard library is available, and in which \f(CW\*(C`main\*(C'\fR has a return
type of \f(CW\*(C`int\*(C'\fR. Examples are nearly everything except a kernel.
This is equivalent to \fB\-fno\-freestanding\fR.
.IP "\fB\-ffreestanding\fR" 4
.IX Item "-ffreestanding"
-Assert that compilation takes place in a freestanding environment. This
+Assert that compilation targets a freestanding environment. This
implies \fB\-fno\-builtin\fR. A freestanding environment
is one in which the standard library may not exist, and program startup may
not necessarily be at \f(CW\*(C`main\*(C'\fR. The most obvious example is an \s-1OS\s0 kernel.
have support for \fB\-pthread\fR.
.IP "\fB\-fgnu\-tm\fR" 4
.IX Item "-fgnu-tm"
-When the option \fB\-fgnu\-tm\fR is specified, the compiler will
-generate code for the Linux variant of Intel's current Transactional
+When the option \fB\-fgnu\-tm\fR is specified, the compiler
+generates code for the Linux variant of Intel's current Transactional
Memory \s-1ABI\s0 specification document (Revision 1.1, May 6 2009). This is
an experimental feature whose interface may change in future versions
of \s-1GCC\s0, as the official specification changes. Please note that not
.IX Item "-trigraphs"
Support \s-1ISO\s0 C trigraphs. The \fB\-ansi\fR option (and \fB\-std\fR
options for strict \s-1ISO\s0 C conformance) implies \fB\-trigraphs\fR.
-.IP "\fB\-no\-integrated\-cpp\fR" 4
-.IX Item "-no-integrated-cpp"
-Performs a compilation in two passes: preprocessing and compiling. This
-option allows a user supplied \*(L"cc1\*(R", \*(L"cc1plus\*(R", or \*(L"cc1obj\*(R" via the
-\&\fB\-B\fR option. The user supplied compilation step can then add in
-an additional preprocessing step after normal preprocessing but before
-compiling. The default is to use the integrated cpp (internal cpp)
-.Sp
-The semantics of this option will change if \*(L"cc1\*(R", \*(L"cc1plus\*(R", and
-\&\*(L"cc1obj\*(R" are merged.
.IP "\fB\-traditional\fR" 4
.IX Item "-traditional"
.PD 0
declaration does not use either \f(CW\*(C`signed\*(C'\fR or \f(CW\*(C`unsigned\*(C'\fR. By
default, such a bit-field is signed, because this is consistent: the
basic integer types such as \f(CW\*(C`int\*(C'\fR are signed types.
-.Sh "Options Controlling \*(C+ Dialect"
+.SS "Options Controlling \*(C+ Dialect"
.IX Subsection "Options Controlling Dialect"
This section describes the command-line options that are only meaningful
-for \*(C+ programs; but you can also use most of the \s-1GNU\s0 compiler options
+for \*(C+ programs. You can also use most of the \s-1GNU\s0 compiler options
regardless of what language your program is in. For example, you
might compile a file \f(CW\*(C`firstClass.C\*(C'\fR like this:
.PP
Here is a list of options that are \fIonly\fR for compiling \*(C+ programs:
.IP "\fB\-fabi\-version=\fR\fIn\fR" 4
.IX Item "-fabi-version=n"
-Use version \fIn\fR of the \*(C+ \s-1ABI\s0. Version 2 is the version of the
-\&\*(C+ \s-1ABI\s0 that first appeared in G++ 3.4. Version 1 is the version of
-the \*(C+ \s-1ABI\s0 that first appeared in G++ 3.2. Version 0 will always be
-the version that conforms most closely to the \*(C+ \s-1ABI\s0 specification.
-Therefore, the \s-1ABI\s0 obtained using version 0 will change as \s-1ABI\s0 bugs
-are fixed.
+Use version \fIn\fR of the \*(C+ \s-1ABI\s0. The default is version 2.
.Sp
-The default is version 2.
+Version 0 refers to the version conforming most closely to
+the \*(C+ \s-1ABI\s0 specification. Therefore, the \s-1ABI\s0 obtained using version 0
+will change in different versions of G++ as \s-1ABI\s0 bugs are fixed.
+.Sp
+Version 1 is the version of the \*(C+ \s-1ABI\s0 that first appeared in G++ 3.2.
+.Sp
+Version 2 is the version of the \*(C+ \s-1ABI\s0 that first appeared in G++ 3.4.
.Sp
Version 3 corrects an error in mangling a constant address as a
template argument.
Check that the pointer returned by \f(CW\*(C`operator new\*(C'\fR is non-null
before attempting to modify the storage allocated. This check is
normally unnecessary because the \*(C+ standard specifies that
-\&\f(CW\*(C`operator new\*(C'\fR will only return \f(CW0\fR if it is declared
-\&\fB\f(BIthrow()\fB\fR, in which case the compiler will always check the
+\&\f(CW\*(C`operator new\*(C'\fR only returns \f(CW0\fR if it is declared
+\&\fB\f(BIthrow()\fB\fR, in which case the compiler always checks the
return value even without this option. In all other cases, when
\&\f(CW\*(C`operator new\*(C'\fR has a non-empty exception specification, memory
exhaustion is signalled by throwing \f(CW\*(C`std::bad_alloc\*(C'\fR. See also
\&\fBnew (nothrow)\fR.
-.IP "\fB\-fconserve\-space\fR" 4
-.IX Item "-fconserve-space"
-Put uninitialized or run-time-initialized global variables into the
-common segment, as C does. This saves space in the executable at the
-cost of not diagnosing duplicate definitions. If you compile with this
-flag and your program mysteriously crashes after \f(CW\*(C`main()\*(C'\fR has
-completed, you may have an object that is being destroyed twice because
-two definitions were merged.
-.Sp
-This option is no longer useful on most targets, now that support has
-been added for putting variables into \s-1BSS\s0 without making them common.
.IP "\fB\-fconstexpr\-depth=\fR\fIn\fR" 4
.IX Item "-fconstexpr-depth=n"
Set the maximum nested evaluation depth for \*(C+11 constexpr functions
.IP "\fB\-fdeduce\-init\-list\fR" 4
.IX Item "-fdeduce-init-list"
Enable deduction of a template type parameter as
-std::initializer_list from a brace-enclosed initializer list, i.e.
+\&\f(CW\*(C`std::initializer_list\*(C'\fR from a brace-enclosed initializer list, i.e.
.Sp
.Vb 4
\& template <class T> auto forward(T t) \-> decltype (realfn (t))
for reducing code size in production builds, much like defining
\&\fB\s-1NDEBUG\s0\fR. This does not give user code permission to throw
exceptions in violation of the exception specifications; the compiler
-will still optimize based on the specifications, so throwing an
-unexpected exception will result in undefined behavior.
+still optimizes based on the specifications, so throwing an
+unexpected exception results in undefined behavior at run time.
+.IP "\fB\-fextern\-tls\-init\fR" 4
+.IX Item "-fextern-tls-init"
+.PD 0
+.IP "\fB\-fno\-extern\-tls\-init\fR" 4
+.IX Item "-fno-extern-tls-init"
+.PD
+The \*(C+11 and OpenMP standards allow \fBthread_local\fR and
+\&\fBthreadprivate\fR variables to have dynamic (runtime)
+initialization. To support this, any use of such a variable goes
+through a wrapper function that performs any necessary initialization.
+When the use and definition of the variable are in the same
+translation unit, this overhead can be optimized away, but when the
+use is in a different translation unit there is significant overhead
+even if the variable doesn't actually need dynamic initialization. If
+the programmer can be sure that no use of the variable in a
+non-defining \s-1TU\s0 needs to trigger dynamic initialization (either
+because the variable is statically initialized, or a use of the
+variable in the defining \s-1TU\s0 will be executed before any uses in
+another \s-1TU\s0), they can avoid this overhead with the
+\&\fB\-fno\-extern\-tls\-init\fR option.
+.Sp
+On targets that support symbol aliases, the default is
+\&\fB\-fextern\-tls\-init\fR. On targets that do not support symbol
+aliases, the default is \fB\-fno\-extern\-tls\-init\fR.
.IP "\fB\-ffor\-scope\fR" 4
.IX Item "-ffor-scope"
.PD 0
as was the case in old versions of G++, and other (traditional)
implementations of \*(C+.
.Sp
-The default if neither flag is given to follow the standard,
+If neither flag is given, the default is to follow the standard,
but to allow and give a warning for old-style code that would
otherwise be invalid, or have different behavior.
.IP "\fB\-fno\-gnu\-keywords\fR" 4
.IX Item "-fno-implicit-inline-templates"
Don't emit code for implicit instantiations of inline templates, either.
The default is to handle inlines differently so that compiles with and
-without optimization will need the same set of explicit instantiations.
+without optimization need the same set of explicit instantiations.
.IP "\fB\-fno\-implement\-inlines\fR" 4
.IX Item "-fno-implement-inlines"
To save space, do not emit out-of-line copies of inline functions
-controlled by \fB#pragma implementation\fR. This will cause linker
+controlled by \fB#pragma implementation\fR. This causes linker
errors if these functions are not inlined everywhere they are called.
.IP "\fB\-fms\-extensions\fR" 4
.IX Item "-fms-extensions"
-Disable pedantic warnings about constructs used in \s-1MFC\s0, such as implicit
+Disable Wpedantic warnings about constructs used in \s-1MFC\s0, such as implicit
int and getting a pointer to member function via non-standard syntax.
.IP "\fB\-fno\-nonansi\-builtins\fR" 4
.IX Item "-fno-nonansi-builtins"
\&\f(CW\*(C`index\*(C'\fR, \f(CW\*(C`bzero\*(C'\fR, \f(CW\*(C`conjf\*(C'\fR, and other related functions.
.IP "\fB\-fnothrow\-opt\fR" 4
.IX Item "-fnothrow-opt"
-Treat a \f(CW\*(C`throw()\*(C'\fR exception specification as though it were a
+Treat a \f(CW\*(C`throw()\*(C'\fR exception specification as if it were a
\&\f(CW\*(C`noexcept\*(C'\fR specification to reduce or eliminate the text size
overhead relative to a function with no exception specification. If
the function has local variables of types with non-trivial
-destructors, the exception specification will actually make the
+destructors, the exception specification actually makes the
function smaller because the \s-1EH\s0 cleanups for those variables can be
optimized away. The semantic effect is that an exception thrown out of
-a function with such an exception specification will result in a call
+a function with such an exception specification results in a call
to \f(CW\*(C`terminate\*(C'\fR rather than \f(CW\*(C`unexpected\*(C'\fR.
.IP "\fB\-fno\-operator\-names\fR" 4
.IX Item "-fno-operator-names"
.IP "\fB\-fpermissive\fR" 4
.IX Item "-fpermissive"
Downgrade some diagnostics about nonconformant code from errors to
-warnings. Thus, using \fB\-fpermissive\fR will allow some
+warnings. Thus, using \fB\-fpermissive\fR allows some
nonconforming code to compile.
.IP "\fB\-fno\-pretty\-templates\fR" 4
.IX Item "-fno-pretty-templates"
When an error message refers to a specialization of a function
-template, the compiler will normally print the signature of the
+template, the compiler normally prints the signature of the
template followed by the template arguments and any typedefs or
typenames in the signature (e.g. \f(CW\*(C`void f(T) [with T = int]\*(C'\fR
rather than \f(CW\*(C`void f(int)\*(C'\fR) so that it's clear which template is
involved. When an error message refers to a specialization of a class
-template, the compiler will omit any template arguments that match
+template, the compiler omits any template arguments that match
the default template arguments for that template. If either of these
behaviors make it harder to understand the error message rather than
-easier, using \fB\-fno\-pretty\-templates\fR will disable them.
+easier, you can use \fB\-fno\-pretty\-templates\fR to disable them.
.IP "\fB\-frepo\fR" 4
.IX Item "-frepo"
Enable automatic template instantiation at link time. This option also
functions for use by the \*(C+ run-time type identification features
(\fBdynamic_cast\fR and \fBtypeid\fR). If you don't use those parts
of the language, you can save some space by using this flag. Note that
-exception handling uses the same information, but it will generate it as
+exception handling uses the same information, but G++ generates it as
needed. The \fBdynamic_cast\fR operator can still be used for casts that
do not require run-time type information, i.e. casts to \f(CW\*(C`void *\*(C'\fR or to
unambiguous base classes.
represented in the minimum number of bits needed to represent all the
enumerators). This assumption may not be valid if the program uses a
cast to convert an arbitrary integer value to the enumerated type.
+.IP "\fB\-ftemplate\-backtrace\-limit=\fR\fIn\fR" 4
+.IX Item "-ftemplate-backtrace-limit=n"
+Set the maximum number of template instantiation notes for a single
+warning or error to \fIn\fR. The default value is 10.
.IP "\fB\-ftemplate\-depth=\fR\fIn\fR" 4
.IX Item "-ftemplate-depth=n"
Set the maximum instantiation depth for template classes to \fIn\fR.
Register destructors for objects with static storage duration with the
\&\f(CW\*(C`_\|_cxa_atexit\*(C'\fR function rather than the \f(CW\*(C`atexit\*(C'\fR function.
This option is required for fully standards-compliant handling of static
-destructors, but will only work if your C library supports
+destructors, but only works if your C library supports
\&\f(CW\*(C`_\|_cxa_atexit\*(C'\fR.
.IP "\fB\-fno\-use\-cxa\-get\-exception\-ptr\fR" 4
.IX Item "-fno-use-cxa-get-exception-ptr"
Don't use the \f(CW\*(C`_\|_cxa_get_exception_ptr\*(C'\fR runtime routine. This
-will cause \f(CW\*(C`std::uncaught_exception\*(C'\fR to be incorrect, but is necessary
+causes \f(CW\*(C`std::uncaught_exception\*(C'\fR to be incorrect, but is necessary
if the runtime routine is not available.
.IP "\fB\-fvisibility\-inlines\-hidden\fR" 4
.IX Item "-fvisibility-inlines-hidden"
This switch declares that the user does not attempt to compare
pointers to inline functions or methods where the addresses of the two functions
-were taken in different shared objects.
+are taken in different shared objects.
.Sp
The effect of this is that \s-1GCC\s0 may, effectively, mark inline methods with
\&\f(CW\*(C`_\|_attribute_\|_ ((visibility ("hidden")))\*(C'\fR so that they do not
effect of the switch for that method. For example, if you do want to
compare pointers to a particular inline method, you might mark it as
having default visibility. Marking the enclosing class with explicit
-visibility will have no effect.
+visibility has no effect.
.Sp
Explicitly instantiated inline methods are unaffected by this option
as their linkage might otherwise cross a shared library boundary.
Types, but not their members, are not hidden by default.
.IP "3." 4
The One Definition Rule is relaxed for types without explicit
-visibility specifications that are defined in more than one different
-shared object: those declarations are permitted if they would have
-been permitted when this option was not used.
+visibility specifications that are defined in more than one
+shared object: those declarations are permitted if they are
+permitted when this option is not used.
.RE
.RS 4
.Sp
.Sp
Among the consequences of these changes are that static data members
of the same type with the same name but defined in different shared
-objects will be different, so changing one will not change the other;
+objects are different, so changing one does not change the other;
and that pointers to function members defined in different shared
objects may not compare equal. When this flag is given, it is a
violation of the \s-1ODR\s0 to define types with the same name differently.
.IP "\fB\-fno\-weak\fR" 4
.IX Item "-fno-weak"
Do not use weak symbol support, even if it is provided by the linker.
-By default, G++ will use weak symbols if they are available. This
+By default, G++ uses weak symbols if they are available. This
option exists only for testing, and should not be used by end-users;
-it will result in inferior code and has no benefits. This option may
+it results in inferior code and has no benefits. This option may
be removed in a future release of G++.
.IP "\fB\-nostdinc++\fR" 4
.IX Item "-nostdinc++"
.IX Item "-fno-default-inline"
Do not assume \fBinline\fR for functions defined inside a class scope.
Note that these
-functions will have linkage like inline functions; they just won't be
+functions have linkage like inline functions; they just aren't
inlined by default.
.IP "\fB\-Wabi\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4
.IX Item "-Wabi (C, Objective-C, and Objective- only)"
all such cases, there are probably some cases that are not warned about,
even though G++ is generating incompatible code. There may also be
cases where warnings are emitted even though the code that is generated
-will be compatible.
+is compatible.
.Sp
You should rewrite your code to avoid these warnings if you are
concerned about the fact that code generated by G++ may not be binary
\& struct B : public A { int f2 : 1; };
.Ve
.Sp
-In this case, G++ will place \f(CW\*(C`B::f2\*(C'\fR into the same byte
-as\f(CW\*(C`A::f1\*(C'\fR; other compilers will not. You can avoid this problem
+In this case, G++ places \f(CW\*(C`B::f2\*(C'\fR into the same byte
+as \f(CW\*(C`A::f1\*(C'\fR; other compilers do not. You can avoid this problem
by explicitly padding \f(CW\*(C`A\*(C'\fR so that its size is a multiple of the
-byte size on your platform; that will cause G++ and other compilers to
-layout \f(CW\*(C`B\*(C'\fR identically.
+byte size on your platform; that causes G++ and other compilers to
+lay out \f(CW\*(C`B\*(C'\fR identically.
.IP "\(bu" 4
Incorrect handling of tail-padding for virtual bases. G++ does not use
tail padding when laying out virtual bases. For example:
\& struct C : public A, public virtual B {};
.Ve
.Sp
-In this case, G++ will not place \f(CW\*(C`B\*(C'\fR into the tail-padding for
-\&\f(CW\*(C`A\*(C'\fR; other compilers will. You can avoid this problem by
+In this case, G++ does not place \f(CW\*(C`B\*(C'\fR into the tail-padding for
+\&\f(CW\*(C`A\*(C'\fR; other compilers do. You can avoid this problem by
explicitly padding \f(CW\*(C`A\*(C'\fR so that its size is a multiple of its
-alignment (ignoring virtual base classes); that will cause G++ and other
-compilers to layout \f(CW\*(C`C\*(C'\fR identically.
+alignment (ignoring virtual base classes); that causes G++ and other
+compilers to lay out \f(CW\*(C`C\*(C'\fR identically.
.IP "\(bu" 4
Incorrect handling of bit-fields with declared widths greater than that
of their underlying types, when the bit-fields appear in a union. For
\& union U { int i : 4096; };
.Ve
.Sp
-Assuming that an \f(CW\*(C`int\*(C'\fR does not have 4096 bits, G++ will make the
+Assuming that an \f(CW\*(C`int\*(C'\fR does not have 4096 bits, G++ makes the
union too small by the number of bits in an \f(CW\*(C`int\*(C'\fR.
.IP "\(bu" 4
Empty classes can be placed at incorrect offsets. For example:
\& struct C : public B, public A {};
.Ve
.Sp
-G++ will place the \f(CW\*(C`A\*(C'\fR base class of \f(CW\*(C`C\*(C'\fR at a nonzero offset;
+G++ places the \f(CW\*(C`A\*(C'\fR base class of \f(CW\*(C`C\*(C'\fR at a nonzero offset;
it should be placed at offset zero. G++ mistakenly believes that the
\&\f(CW\*(C`A\*(C'\fR data member of \f(CW\*(C`B\*(C'\fR is already at offset zero.
.IP "\(bu" 4
.RE
.RS 4
.Sp
-It also warns psABI related changes. The known psABI changes at this
+It also warns about psABI-related changes. The known psABI changes at this
point include:
.IP "\(bu" 4
-For SYSV/x86\-64, when passing union with long double, it is changed to
-pass in memory as specified in psABI. For example:
+For SysV/x86\-64, unions with \f(CW\*(C`long double\*(C'\fR members are
+passed in memory as specified in psABI. For example:
.Sp
.Vb 4
\& union U {
\& };
.Ve
.Sp
-\&\f(CW\*(C`union U\*(C'\fR will always be passed in memory.
+\&\f(CW\*(C`union U\*(C'\fR is always passed in memory.
.RE
.RS 4
.RE
.IX Item "-Wctor-dtor-privacy ( and Objective- only)"
Warn when a class seems unusable because all the constructors or
destructors in that class are private, and it has neither friends nor
-public static member functions.
+public static member functions. Also warn if there are no non-private
+methods, and there's at least one private member function that isn't
+a constructor or destructor.
.IP "\fB\-Wdelete\-non\-virtual\-dtor\fR (\*(C+ and Objective\-\*(C+ only)" 4
.IX Item "-Wdelete-non-virtual-dtor ( and Objective- only)"
Warn when \fBdelete\fR is used to destroy an instance of a class that
an instance of a derived class through a pointer to a base class if the
base class does not have a virtual destructor. This warning is enabled
by \fB\-Wall\fR.
+.IP "\fB\-Wliteral\-suffix\fR (\*(C+ and Objective\-\*(C+ only)" 4
+.IX Item "-Wliteral-suffix ( and Objective- only)"
+Warn when a string or character literal is followed by a ud-suffix which does
+not begin with an underscore. As a conforming extension, \s-1GCC\s0 treats such
+suffixes as separate preprocessing tokens in order to maintain backwards
+compatibility with code that uses formatting macros from \f(CW\*(C`<inttypes.h>\*(C'\fR.
+For example:
+.Sp
+.Vb 3
+\& #define _\|_STDC_FORMAT_MACROS
+\& #include <inttypes.h>
+\& #include <stdio.h>
+\&
+\& int main() {
+\& int64_t i64 = 123;
+\& printf("My int64: %"PRId64"\en", i64);
+\& }
+.Ve
+.Sp
+In this case, \f(CW\*(C`PRId64\*(C'\fR is treated as a separate preprocessing token.
+.Sp
+This warning is enabled by default.
.IP "\fB\-Wnarrowing\fR (\*(C+ and Objective\-\*(C+ only)" 4
.IX Item "-Wnarrowing ( and Objective- only)"
Warn when a narrowing conversion prohibited by \*(C+11 occurs within
.Sp
This flag is included in \fB\-Wall\fR and \fB\-Wc++11\-compat\fR.
.Sp
-With \-std=c++11, \fB\-Wno\-narrowing\fR suppresses the diagnostic
+With \fB\-std=c++11\fR, \fB\-Wno\-narrowing\fR suppresses the diagnostic
required by the standard. Note that this does not affect the meaning
of well-formed code; narrowing conversions are still considered
ill-formed in \s-1SFINAE\s0 context.
the compiler to never throw an exception.
.IP "\fB\-Wnon\-virtual\-dtor\fR (\*(C+ and Objective\-\*(C+ only)" 4
.IX Item "-Wnon-virtual-dtor ( and Objective- only)"
-Warn when a class has virtual functions and accessible non-virtual
-destructor, in which case it would be possible but unsafe to delete
+Warn when a class has virtual functions and an accessible non-virtual
+destructor, in which case it is possible but unsafe to delete
an instance of a derived class through a pointer to the base class.
This warning is also enabled if \fB\-Weffc++\fR is specified.
.IP "\fB\-Wreorder\fR (\*(C+ and Objective\-\*(C+ only)" 4
\& };
.Ve
.Sp
-The compiler will rearrange the member initializers for \fBi\fR
+The compiler rearranges the member initializers for \fBi\fR
and \fBj\fR to match the declaration order of the members, emitting
a warning to that effect. This warning is enabled by \fB\-Wall\fR.
+.IP "\fB\-fext\-numeric\-literals\fR (\*(C+ and Objective\-\*(C+ only)" 4
+.IX Item "-fext-numeric-literals ( and Objective- only)"
+Accept imaginary, fixed-point, or machine-defined
+literal number suffixes as \s-1GNU\s0 extensions.
+When this option is turned off these suffixes are treated
+as \*(C+11 user-defined literal numeric suffixes.
+This is on by default for all pre\-\*(C+11 dialects and all \s-1GNU\s0 dialects:
+\&\fB\-std=c++98\fR, \fB\-std=gnu++98\fR, \fB\-std=gnu++11\fR,
+\&\fB\-std=gnu++1y\fR.
+This option is off by default
+for \s-1ISO\s0 \*(C+11 onwards (\fB\-std=c++11\fR, ...).
.PP
The following \fB\-W...\fR options are not affected by \fB\-Wall\fR.
.IP "\fB\-Weffc++\fR (\*(C+ and Objective\-\*(C+ only)" 4
.RS 4
.IP "\(bu" 4
Item 11: Define a copy constructor and an assignment operator for classes
-with dynamically allocated memory.
+with dynamically-allocated memory.
.IP "\(bu" 4
Item 12: Prefer initialization to assignment in constructors.
.IP "\(bu" 4
.RE
.IP "\fB\-Wstrict\-null\-sentinel\fR (\*(C+ and Objective\-\*(C+ only)" 4
.IX Item "-Wstrict-null-sentinel ( and Objective- only)"
-Warn also about the use of an uncasted \f(CW\*(C`NULL\*(C'\fR as sentinel. When
+Warn about the use of an uncasted \f(CW\*(C`NULL\*(C'\fR as sentinel. When
compiling only with \s-1GCC\s0 this is a valid sentinel, as \f(CW\*(C`NULL\*(C'\fR is defined
-to \f(CW\*(C`_\|_null\*(C'\fR. Although it is a null pointer constant not a null pointer,
-it is guaranteed to be of the same size as a pointer. But this use is
-not portable across different compilers.
+to \f(CW\*(C`_\|_null\*(C'\fR. Although it is a null pointer constant rather than a
+null pointer, it is guaranteed to be of the same size as a pointer.
+But this use is not portable across different compilers.
.IP "\fB\-Wno\-non\-template\-friend\fR (\*(C+ and Objective\-\*(C+ only)" 4
.IX Item "-Wno-non-template-friend ( and Objective- only)"
Disable warnings when non-templatized friend functions are declared
\& b\->f();
.Ve
.Sp
-will fail to compile.
+fails to compile.
.IP "\fB\-Wno\-pmf\-conversions\fR (\*(C+ and Objective\-\*(C+ only)" 4
.IX Item "-Wno-pmf-conversions ( and Objective- only)"
Disable the diagnostic for converting a bound pointer to member function
.IX Item "-Wsign-promo ( and Objective- only)"
Warn when overload resolution chooses a promotion from unsigned or
enumerated type to a signed type, over a conversion to an unsigned type of
-the same size. Previous versions of G++ would try to preserve
+the same size. Previous versions of G++ tried to preserve
unsignedness, but the standard mandates the current behavior.
-.Sp
-.Vb 4
-\& struct A {
-\& operator int ();
-\& A& operator = (int);
-\& };
-\&
-\& main ()
-\& {
-\& A a,b;
-\& a = b;
-\& }
-.Ve
-.Sp
-In this example, G++ will synthesize a default \fBA& operator =
-(const A&);\fR, while cfront will use the user-defined \fBoperator =\fR.
-.Sh "Options Controlling Objective-C and Objective\-\*(C+ Dialects"
+.SS "Options Controlling Objective-C and Objective\-\*(C+ Dialects"
.IX Subsection "Options Controlling Objective-C and Objective- Dialects"
(\s-1NOTE:\s0 This manual does not describe the Objective-C and Objective\-\*(C+
languages themselves.
.PP
This section describes the command-line options that are only meaningful
-for Objective-C and Objective\-\*(C+ programs, but you can also use most of
+for Objective-C and Objective\-\*(C+ programs. You can also use most of
the language-independent \s-1GNU\s0 compiler options.
For example, you might compile a file \f(CW\*(C`some_class.m\*(C'\fR like this:
.PP
literal string specified with the syntax \f(CW\*(C`@"..."\*(C'\fR. The default
class name is \f(CW\*(C`NXConstantString\*(C'\fR if the \s-1GNU\s0 runtime is being used, and
\&\f(CW\*(C`NSConstantString\*(C'\fR if the NeXT runtime is being used (see below). The
-\&\fB\-fconstant\-cfstrings\fR option, if also present, will override the
+\&\fB\-fconstant\-cfstrings\fR option, if also present, overrides the
\&\fB\-fconstant\-string\-class\fR setting and cause \f(CW\*(C`@"..."\*(C'\fR literals
to be laid out as constant CoreFoundation strings.
.IP "\fB\-fgnu\-runtime\fR" 4
.IX Item "-fobjc-call-cxx-cdtors"
For each Objective-C class, check if any of its instance variables is a
\&\*(C+ object with a non-trivial default constructor. If so, synthesize a
-special \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR instance method which will run
+special \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR instance method which runs
non-trivial default constructors on any such instance variables, in order,
and then return \f(CW\*(C`self\*(C'\fR. Similarly, check if any instance variable
is a \*(C+ object with a non-trivial destructor, and if so, synthesize a
-special \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR method which will run
+special \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR method which runs
all such default destructors, in reverse order.
.Sp
The \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR and \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR
-methods thusly generated will only operate on instance variables
+methods thusly generated only operate on instance variables
declared in the current Objective-C class, and not those inherited
from superclasses. It is the responsibility of the Objective-C
runtime to invoke all such methods in an object's inheritance
-hierarchy. The \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR methods will be invoked
+hierarchy. The \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR methods are invoked
by the runtime immediately after a new object instance is allocated;
-the \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods will be invoked immediately
+the \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods are invoked immediately
before the runtime deallocates an object instance.
.Sp
As of this writing, only the NeXT runtime on Mac \s-1OS\s0 X 10.4 and later has
Warn if multiple methods with differing argument and/or return types are
found for a given selector when attempting to send a message using this
selector to a receiver of type \f(CW\*(C`id\*(C'\fR or \f(CW\*(C`Class\*(C'\fR. When this flag
-is off (which is the default behavior), the compiler will omit such warnings
+is off (which is the default behavior), the compiler omits such warnings
if any differences found are confined to types that share the same size
and alignment.
.IP "\fB\-Wundeclared\-selector\fR (Objective-C and Objective\-\*(C+ only)" 4
.IX Item "-print-objc-runtime-info"
Generate C header describing the largest structure that is passed by
value, if any.
-.Sh "Options to Control Diagnostic Messages Formatting"
+.SS "Options to Control Diagnostic Messages Formatting"
.IX Subsection "Options to Control Diagnostic Messages Formatting"
Traditionally, diagnostic messages have been formatted irrespective of
-the output device's aspect (e.g. its width, ...). The options described
-below can be used to control the diagnostic messages formatting
-algorithm, e.g. how many characters per line, how often source location
-information should be reported. Right now, only the \*(C+ front end can
-honor these options. However it is expected, in the near future, that
-the remaining front ends would be able to digest them correctly.
+the output device's aspect (e.g. its width, ...). You can use the
+options described below
+to control the formatting algorithm for diagnostic messages,
+e.g. how many characters per line, how often source location
+information should be reported. Note that some language front ends may not
+honor these options.
.IP "\fB\-fmessage\-length=\fR\fIn\fR" 4
.IX Item "-fmessage-length=n"
Try to format error messages so that they fit on lines of about \fIn\fR
characters. The default is 72 characters for \fBg++\fR and 0 for the rest of
the front ends supported by \s-1GCC\s0. If \fIn\fR is zero, then no
-line-wrapping will be done; each error message will appear on a single
+line-wrapping is done; each error message appears on a single
line.
.IP "\fB\-fdiagnostics\-show\-location=once\fR" 4
.IX Item "-fdiagnostics-show-location=once"
Only meaningful in line-wrapping mode. Instructs the diagnostic messages
-reporter to emit \fIonce\fR source location information; that is, in
+reporter to emit source location information \fIonce\fR; that is, in
case the message is too long to fit on a single physical line and has to
be wrapped, the source location won't be emitted (as prefix) again,
over and over, in subsequent continuation lines. This is the default
command-line option that directly controls the diagnostic (if such an
option is known to the diagnostic machinery). Specifying the
\&\fB\-fno\-diagnostics\-show\-option\fR flag suppresses that behavior.
-.Sh "Options to Request or Suppress Warnings"
+.IP "\fB\-fno\-diagnostics\-show\-caret\fR" 4
+.IX Item "-fno-diagnostics-show-caret"
+By default, each diagnostic emitted includes the original source line
+and a caret '^' indicating the column. This option suppresses this
+information.
+.SS "Options to Request or Suppress Warnings"
.IX Subsection "Options to Request or Suppress Warnings"
Warnings are diagnostic messages that report constructions that
are not inherently erroneous but that are risky or suggest there
.IP "\fB\-Werror=\fR" 4
.IX Item "-Werror="
Make the specified warning into an error. The specifier for a warning
-is appended, for example \fB\-Werror=switch\fR turns the warnings
+is appended; for example \fB\-Werror=switch\fR turns the warnings
controlled by \fB\-Wswitch\fR into errors. This switch takes a
negative form, to be used to negate \fB\-Werror\fR for specific
-warnings, for example \fB\-Wno\-error=switch\fR makes
+warnings; for example \fB\-Wno\-error=switch\fR makes
\&\fB\-Wswitch\fR warnings not be errors, even when \fB\-Werror\fR
is in effect.
.Sp
occurred rather than trying to keep going and printing further error
messages.
.PP
-You can request many specific warnings with options beginning
+You can request many specific warnings with options beginning with
\&\fB\-W\fR, for example \fB\-Wimplicit\fR to request warnings on
implicit declarations. Each of these specific warning options also
has a negative form beginning \fB\-Wno\-\fR to turn off warnings; for
example, \fB\-Wno\-implicit\fR. This manual lists only one of the
-two forms, whichever is not the default. For further,
+two forms, whichever is not the default. For further
language-specific options also refer to \fB\*(C+ Dialect Options\fR and
\&\fBObjective-C and Objective\-\*(C+ Dialect Options\fR.
.PP
When an unrecognized warning option is requested (e.g.,
-\&\fB\-Wunknown\-warning\fR), \s-1GCC\s0 will emit a diagnostic stating
+\&\fB\-Wunknown\-warning\fR), \s-1GCC\s0 emits a diagnostic stating
that the option is not recognized. However, if the \fB\-Wno\-\fR form
-is used, the behavior is slightly different: No diagnostic will be
+is used, the behavior is slightly different: no diagnostic is
produced for \fB\-Wno\-unknown\-warning\fR unless other diagnostics
are being produced. This allows the use of new \fB\-Wno\-\fR options
-with old compilers, but if something goes wrong, the compiler will
-warn that an unrecognized option was used.
+with old compilers, but if something goes wrong, the compiler
+warns that an unrecognized option is present.
+.IP "\fB\-Wpedantic\fR" 4
+.IX Item "-Wpedantic"
+.PD 0
.IP "\fB\-pedantic\fR" 4
.IX Item "-pedantic"
+.PD
Issue all the warnings demanded by strict \s-1ISO\s0 C and \s-1ISO\s0 \*(C+;
reject all programs that use forbidden extensions, and some other
programs that do not follow \s-1ISO\s0 C and \s-1ISO\s0 \*(C+. For \s-1ISO\s0 C, follows the
version of the \s-1ISO\s0 C standard specified by any \fB\-std\fR option used.
.Sp
Valid \s-1ISO\s0 C and \s-1ISO\s0 \*(C+ programs should compile properly with or without
-this option (though a rare few will require \fB\-ansi\fR or a
+this option (though a rare few require \fB\-ansi\fR or a
\&\fB\-std\fR option specifying the required version of \s-1ISO\s0 C). However,
without this option, certain \s-1GNU\s0 extensions and traditional C and \*(C+
features are supported as well. With this option, they are rejected.
.Sp
-\&\fB\-pedantic\fR does not cause warning messages for use of the
+\&\fB\-Wpedantic\fR does not cause warning messages for use of the
alternate keywords whose names begin and end with \fB_\|_\fR. Pedantic
warnings are also disabled in the expression that follows
\&\f(CW\*(C`_\|_extension_\|_\*(C'\fR. However, only system header files should use
these escape routes; application programs should avoid them.
.Sp
-Some users try to use \fB\-pedantic\fR to check programs for strict \s-1ISO\s0
+Some users try to use \fB\-Wpedantic\fR to check programs for strict \s-1ISO\s0
C conformance. They soon find that it does not do quite what they want:
it finds some non-ISO practices, but not all\-\-\-only those for which
\&\s-1ISO\s0 C \fIrequires\fR a diagnostic, and some others for which
.Sp
A feature to report any failure to conform to \s-1ISO\s0 C might be useful in
some instances, but would require considerable additional work and would
-be quite different from \fB\-pedantic\fR. We don't have plans to
+be quite different from \fB\-Wpedantic\fR. We don't have plans to
support such a feature in the near future.
.Sp
Where the standard specified with \fB\-std\fR represents a \s-1GNU\s0
extended dialect of C, such as \fBgnu90\fR or \fBgnu99\fR, there is a
corresponding \fIbase standard\fR, the version of \s-1ISO\s0 C on which the \s-1GNU\s0
-extended dialect is based. Warnings from \fB\-pedantic\fR are given
-where they are required by the base standard. (It would not make sense
+extended dialect is based. Warnings from \fB\-Wpedantic\fR are given
+where they are required by the base standard. (It does not make sense
for such warnings to be given only for features not in the specified \s-1GNU\s0
C dialect, since by definition the \s-1GNU\s0 dialects of C include all
features the compiler supports with the given option, and there would be
nothing to warn about.)
.IP "\fB\-pedantic\-errors\fR" 4
.IX Item "-pedantic-errors"
-Like \fB\-pedantic\fR, except that errors are produced rather than
+Like \fB\-Wpedantic\fR, except that errors are produced rather than
warnings.
.IP "\fB\-Wall\fR" 4
.IX Item "-Wall"
\&\-Warray\-bounds\fR (only with\fB \fR\fB\-O2\fR)
\&\fB\-Wc++11\-compat
\&\-Wchar\-subscripts
-\&\-Wenum\-compare\fR (in C/Objc; this is on by default in \*(C+)
+\&\-Wenum\-compare\fR (in C/ObjC; this is on by default in \*(C+)
\&\fB\-Wimplicit\-int\fR (C and Objective-C only)
\&\fB\-Wimplicit\-function\-declaration\fR (C and Objective-C only)
\&\fB\-Wcomment
\&\-Wformat
\&\-Wmain\fR (only for C/ObjC and unless\fB \fR\fB\-ffreestanding\fR)
\&\fB\-Wmaybe\-uninitialized
-\&\-Wmissing\-braces
-\&\-Wnonnull
+\&\-Wmissing\-braces\fR (only for C/ObjC)
+\&\fB\-Wnonnull
\&\-Wparentheses
\&\-Wpointer\-sign
\&\-Wreorder
(\*(C+ only) Taking the address of a variable that has been declared
\&\fBregister\fR.
.IP "\(bu" 4
-(\*(C+ only) A base class is not initialized in a derived class' copy
+(\*(C+ only) A base class is not initialized in a derived class's copy
constructor.
.RE
.RS 4
.IX Item "-Wno-coverage-mismatch"
Warn if feedback profiles do not match when using the
\&\fB\-fprofile\-use\fR option.
-If a source file was changed between \fB\-fprofile\-gen\fR and
-\&\fB\-fprofile\-use\fR, the files with the profile feedback can fail
+If a source file is changed between compiling with \fB\-fprofile\-gen\fR and
+with \fB\-fprofile\-use\fR, the files with the profile feedback can fail
to match the source file and \s-1GCC\s0 cannot use the profile feedback
information. By default, this warning is enabled and is treated as an
error. \fB\-Wno\-coverage\-mismatch\fR can be used to disable the
\& }
.Ve
.Sp
-the compiler will perform the entire computation with \f(CW\*(C`double\*(C'\fR
+the compiler performs the entire computation with \f(CW\*(C`double\*(C'\fR
because the floating-point literal is a \f(CW\*(C`double\*(C'\fR.
.IP "\fB\-Wformat\fR" 4
.IX Item "-Wformat"
+.PD 0
+.IP "\fB\-Wformat=\fR\fIn\fR" 4
+.IX Item "-Wformat=n"
+.PD
Check calls to \f(CW\*(C`printf\*(C'\fR and \f(CW\*(C`scanf\*(C'\fR, etc., to make sure that
the arguments supplied have types appropriate to the format string
specified, and that the conversions specified in the format string make
as features from the Single Unix Specification and some \s-1BSD\s0 and \s-1GNU\s0
extensions. Other library implementations may not support all these
features; \s-1GCC\s0 does not support warning about features that go beyond a
-particular library's limitations. However, if \fB\-pedantic\fR is used
-with \fB\-Wformat\fR, warnings will be given about format features not
+particular library's limitations. However, if \fB\-Wpedantic\fR is used
+with \fB\-Wformat\fR, warnings are given about format features not
in the selected standard version (but not for \f(CW\*(C`strfmon\*(C'\fR formats,
since those are not in any version of the C standard).
-.Sp
-Since \fB\-Wformat\fR also checks for null format arguments for
-several functions, \fB\-Wformat\fR also implies \fB\-Wnonnull\fR.
-.Sp
-\&\fB\-Wformat\fR is included in \fB\-Wall\fR. For more control over some
-aspects of format checking, the options \fB\-Wformat\-y2k\fR,
-\&\fB\-Wno\-format\-extra\-args\fR, \fB\-Wno\-format\-zero\-length\fR,
-\&\fB\-Wformat\-nonliteral\fR, \fB\-Wformat\-security\fR, and
-\&\fB\-Wformat=2\fR are available, but are not included in \fB\-Wall\fR.
-.IP "\fB\-Wformat\-y2k\fR" 4
-.IX Item "-Wformat-y2k"
-If \fB\-Wformat\fR is specified, also warn about \f(CW\*(C`strftime\*(C'\fR
-formats that may yield only a two-digit year.
+.RS 4
+.IP "\fB\-Wformat=1\fR" 4
+.IX Item "-Wformat=1"
+.PD 0
+.IP "\fB\-Wformat\fR" 4
+.IX Item "-Wformat"
+.PD
+Option \fB\-Wformat\fR is equivalent to \fB\-Wformat=1\fR, and
+\&\fB\-Wno\-format\fR is equivalent to \fB\-Wformat=0\fR. Since
+\&\fB\-Wformat\fR also checks for null format arguments for several
+functions, \fB\-Wformat\fR also implies \fB\-Wnonnull\fR. Some
+aspects of this level of format checking can be disabled by the
+options: \fB\-Wno\-format\-contains\-nul\fR,
+\&\fB\-Wno\-format\-extra\-args\fR, and \fB\-Wno\-format\-zero\-length\fR.
+\&\fB\-Wformat\fR is enabled by \fB\-Wall\fR.
.IP "\fB\-Wno\-format\-contains\-nul\fR" 4
.IX Item "-Wno-format-contains-nul"
If \fB\-Wformat\fR is specified, do not warn about format strings that
specified with \fB$\fR operand number specifications, normally
warnings are still given, since the implementation could not know what
type to pass to \f(CW\*(C`va_arg\*(C'\fR to skip the unused arguments. However,
-in the case of \f(CW\*(C`scanf\*(C'\fR formats, this option will suppress the
+in the case of \f(CW\*(C`scanf\*(C'\fR formats, this option suppresses the
warning if the unused arguments are all pointers, since the Single
Unix Specification says that such unused arguments are allowed.
.IP "\fB\-Wno\-format\-zero\-length\fR" 4
.IX Item "-Wno-format-zero-length"
If \fB\-Wformat\fR is specified, do not warn about zero-length formats.
The C standard specifies that zero-length formats are allowed.
+.IP "\fB\-Wformat=2\fR" 4
+.IX Item "-Wformat=2"
+Enable \fB\-Wformat\fR plus additional format checks. Currently
+equivalent to \fB\-Wformat \-Wformat\-nonliteral \-Wformat\-security
+\&\-Wformat\-y2k\fR.
.IP "\fB\-Wformat\-nonliteral\fR" 4
.IX Item "-Wformat-nonliteral"
If \fB\-Wformat\fR is specified, also warn if the format string is not a
currently a subset of what \fB\-Wformat\-nonliteral\fR warns about, but
in future warnings may be added to \fB\-Wformat\-security\fR that are not
included in \fB\-Wformat\-nonliteral\fR.)
-.IP "\fB\-Wformat=2\fR" 4
-.IX Item "-Wformat=2"
-Enable \fB\-Wformat\fR plus format checks not included in
-\&\fB\-Wformat\fR. Currently equivalent to \fB\-Wformat
-\&\-Wformat\-nonliteral \-Wformat\-security \-Wformat\-y2k\fR.
+.IP "\fB\-Wformat\-y2k\fR" 4
+.IX Item "-Wformat-y2k"
+If \fB\-Wformat\fR is specified, also warn about \f(CW\*(C`strftime\*(C'\fR
+formats that may yield only a two-digit year.
+.RE
+.RS 4
+.RE
.IP "\fB\-Wnonnull\fR" 4
.IX Item "-Wnonnull"
Warn about passing a null pointer for arguments marked as
Warn about uninitialized variables that are initialized with themselves.
Note this option can only be used with the \fB\-Wuninitialized\fR option.
.Sp
-For example, \s-1GCC\s0 will warn about \f(CW\*(C`i\*(C'\fR being uninitialized in the
+For example, \s-1GCC\s0 warns about \f(CW\*(C`i\*(C'\fR being uninitialized in the
following snippet only when \fB\-Winit\-self\fR has been specified:
.Sp
.Vb 5
\& return i;
\& }
.Ve
+.Sp
+This warning is enabled by \fB\-Wall\fR in \*(C+.
.IP "\fB\-Wimplicit\-int\fR (C and Objective-C only)" 4
.IX Item "-Wimplicit-int (C and Objective-C only)"
Warn when a declaration does not specify a type.
a function with external linkage, returning int, taking either zero
arguments, two, or three arguments of appropriate types. This warning
is enabled by default in \*(C+ and is enabled by either \fB\-Wall\fR
-or \fB\-pedantic\fR.
+or \fB\-Wpedantic\fR.
.IP "\fB\-Wmissing\-braces\fR" 4
.IX Item "-Wmissing-braces"
Warn if an aggregate or union initializer is not fully bracketed. In
the following example, the initializer for \fBa\fR is not fully
-bracketed, but that for \fBb\fR is fully bracketed.
+bracketed, but that for \fBb\fR is fully bracketed. This warning is
+enabled by \fB\-Wall\fR in C.
.Sp
.Vb 2
\& int a[2][2] = { 0, 1, 2, 3 };
\&\f(CW\*(C`if\*(C'\fR statement, which in this example is \f(CW\*(C`if (b)\*(C'\fR. This is
often not what the programmer expected, as illustrated in the above
example by indentation the programmer chose. When there is the
-potential for this confusion, \s-1GCC\s0 will issue a warning when this flag
+potential for this confusion, \s-1GCC\s0 issues a warning when this flag
is specified. To eliminate the warning, add explicit braces around
the innermost \f(CW\*(C`if\*(C'\fR statement so there is no way the \f(CW\*(C`else\*(C'\fR
-could belong to the enclosing \f(CW\*(C`if\*(C'\fR. The resulting code would
-look like this:
+can belong to the enclosing \f(CW\*(C`if\*(C'\fR. The resulting code
+looks like this:
.Sp
.Vb 9
\& {
\& }
.Ve
.Sp
-Also warn for dangerous uses of the
-?: with omitted middle operand \s-1GNU\s0 extension. When the condition
-in the ?: operator is a boolean expression the omitted value will
-be always 1. Often the user expects it to be a value computed
+Also warn for dangerous uses of the \s-1GNU\s0 extension to
+\&\f(CW\*(C`?:\*(C'\fR with omitted middle operand. When the condition
+in the \f(CW\*(C`?\*(C'\fR: operator is a boolean expression, the omitted value is
+always 1. Often programmers expect it to be a value computed
inside the conditional expression instead.
.Sp
This warning is enabled by \fB\-Wall\fR.
Warn about code that may have undefined semantics because of violations
of sequence point rules in the C and \*(C+ standards.
.Sp
-The C and \*(C+ standards defines the order in which expressions in a C/\*(C+
+The C and \*(C+ standards define the order in which expressions in a C/\*(C+
program are evaluated in terms of \fIsequence points\fR, which represent
a partial ordering between the execution of parts of the program: those
executed before the sequence point, and those executed after it. These
<\fBhttp://gcc.gnu.org/readings.html\fR>.
.Sp
This warning is enabled by \fB\-Wall\fR for C and \*(C+.
+.IP "\fB\-Wno\-return\-local\-addr\fR" 4
+.IX Item "-Wno-return-local-addr"
+Do not warn about returning a pointer (or in \*(C+, a reference) to a
+variable that goes out of scope after the function returns.
.IP "\fB\-Wreturn\-type\fR" 4
.IX Item "-Wreturn-type"
-Warn whenever a function is defined with a return-type that defaults
+Warn whenever a function is defined with a return type that defaults
to \f(CW\*(C`int\*(C'\fR. Also warn about any \f(CW\*(C`return\*(C'\fR statement with no
-return-value in a function whose return-type is not \f(CW\*(C`void\*(C'\fR
+return value in a function whose return type is not \f(CW\*(C`void\*(C'\fR
(falling off the end of the function body is considered returning
without a value), and about a \f(CW\*(C`return\*(C'\fR statement with an
-expression in a function whose return-type is \f(CW\*(C`void\*(C'\fR.
+expression in a function whose return type is \f(CW\*(C`void\*(C'\fR.
.Sp
For \*(C+, a function without return type always produces a diagnostic
message, even when \fB\-Wno\-return\-type\fR is specified. The only
.IP "\fB\-Wunused\-local\-typedefs\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4
.IX Item "-Wunused-local-typedefs (C, Objective-C, and Objective- only)"
Warn when a typedef locally defined in a function is not used.
+This warning is enabled by \fB\-Wall\fR.
.IP "\fB\-Wunused\-parameter\fR" 4
.IX Item "-Wunused-parameter"
Warn whenever a function parameter is unused aside from its declaration.
used. To suppress this warning cast the unused expression to
\&\fBvoid\fR. This includes an expression-statement or the left-hand
side of a comma expression that contains no side effects. For example,
-an expression such as \fBx[i,j]\fR will cause a warning, while
-\&\fBx[(void)i,j]\fR will not.
+an expression such as \fBx[i,j]\fR causes a warning, while
+\&\fBx[(void)i,j]\fR does not.
.Sp
This warning is enabled by \fB\-Wall\fR.
.IP "\fB\-Wunused\fR" 4
variables that are uninitialized or clobbered as a whole. They do
not occur for variables or elements declared \f(CW\*(C`volatile\*(C'\fR. Because
these warnings depend on optimization, the exact variables or elements
-for which there are warnings will depend on the precise optimization
+for which there are warnings depends on the precise optimization
options and version of \s-1GCC\s0 used.
.Sp
Note that there may be no warning about a variable that is used only
.IX Item "-Wmaybe-uninitialized"
For an automatic variable, if there exists a path from the function
entry to a use of the variable that is initialized, but there exist
-some other paths the variable is not initialized, the compiler will
-emit a warning if it can not prove the uninitialized paths do not
-happen at run time. These warnings are made optional because \s-1GCC\s0 is
+some other paths for which the variable is not initialized, the compiler
+emits a warning if it cannot prove the uninitialized paths are not
+executed at run time. These warnings are made optional because \s-1GCC\s0 is
not smart enough to see all the reasons why the code might be correct
-despite appearing to have an error. Here is one example of how
+in spite of appearing to have an error. Here is one example of how
this can happen:
.Sp
.Vb 12
.Sp
If the value of \f(CW\*(C`y\*(C'\fR is always 1, 2 or 3, then \f(CW\*(C`x\*(C'\fR is
always initialized, but \s-1GCC\s0 doesn't know this. To suppress the
-warning, the user needs to provide a default case with \fIassert\fR\|(0) or
+warning, you need to provide a default case with \fIassert\fR\|(0) or
similar code.
.Sp
This option also warns when a non-volatile automatic variable might be
.IP "\fB\-Wunknown\-pragmas\fR" 4
.IX Item "-Wunknown-pragmas"
Warn when a \f(CW\*(C`#pragma\*(C'\fR directive is encountered that is not understood by
-\&\s-1GCC\s0. If this command-line option is used, warnings will even be issued
+\&\s-1GCC\s0. If this command-line option is used, warnings are even issued
for unknown pragmas in system header files. This is not the case if
-the warnings were only enabled by the \fB\-Wall\fR command-line option.
+the warnings are only enabled by the \fB\-Wall\fR command-line option.
.IP "\fB\-Wno\-pragmas\fR" 4
.IX Item "-Wno-pragmas"
Do not warn about misuses of pragmas, such as incorrect parameters,
It warns about code that might break the strict aliasing rules that the
compiler is using for optimization.
Higher levels correspond to higher accuracy (fewer false positives).
-Higher levels also correspond to more effort, similar to the way \-O works.
-\&\fB\-Wstrict\-aliasing\fR is equivalent to \fB\-Wstrict\-aliasing=n\fR,
-with n=3.
+Higher levels also correspond to more effort, similar to the way \fB\-O\fR
+works.
+\&\fB\-Wstrict\-aliasing\fR is equivalent to \fB\-Wstrict\-aliasing=3\fR.
.Sp
Level 1: Most aggressive, quick, least accurate.
Possibly useful when higher levels
-do not warn but \-fstrict\-aliasing still breaks the code, as it has very few
+do not warn but \fB\-fstrict\-aliasing\fR still breaks the code, as it has very few
false negatives. However, it has many false positives.
Warns for all pointer conversions between possibly incompatible types,
even if never dereferenced. Runs in the front end only.
actually a problem. To help focus on important issues, several
warning levels are defined. No warnings are issued for the use of
undefined signed overflow when estimating how many iterations a loop
-will require, in particular when determining whether a loop will be
+requires, in particular when determining whether a loop will be
executed at all.
.RS 4
.IP "\fB\-Wstrict\-overflow=1\fR" 4
.IX Item "-Wstrict-overflow=1"
Warn about cases that are both questionable and easy to avoid. For
-example: \f(CW\*(C`x + 1 > x\*(C'\fR; with \fB\-fstrict\-overflow\fR, the
-compiler will simplify this to \f(CW1\fR. This level of
+example, with \fB\-fstrict\-overflow\fR, the compiler simplifies
+\&\f(CW\*(C`x + 1 > x\*(C'\fR to \f(CW1\fR. This level of
\&\fB\-Wstrict\-overflow\fR is enabled by \fB\-Wall\fR; higher levels
are not, and must be explicitly requested.
.IP "\fB\-Wstrict\-overflow=2\fR" 4
.IP "\fB\-Wstrict\-overflow=3\fR" 4
.IX Item "-Wstrict-overflow=3"
Also warn about other cases where a comparison is simplified. For
-example: \f(CW\*(C`x + 1 > 1\*(C'\fR will be simplified to \f(CW\*(C`x > 0\*(C'\fR.
+example: \f(CW\*(C`x + 1 > 1\*(C'\fR is simplified to \f(CW\*(C`x > 0\*(C'\fR.
.IP "\fB\-Wstrict\-overflow=4\fR" 4
.IX Item "-Wstrict-overflow=4"
Also warn about other simplifications not covered by the above cases.
-For example: \f(CW\*(C`(x * 10) / 5\*(C'\fR will be simplified to \f(CW\*(C`x * 2\*(C'\fR.
+For example: \f(CW\*(C`(x * 10) / 5\*(C'\fR is simplified to \f(CW\*(C`x * 2\*(C'\fR.
.IP "\fB\-Wstrict\-overflow=5\fR" 4
.IX Item "-Wstrict-overflow=5"
Also warn about cases where the compiler reduces the magnitude of a
-constant involved in a comparison. For example: \f(CW\*(C`x + 2 > y\*(C'\fR will
-be simplified to \f(CW\*(C`x + 1 >= y\*(C'\fR. This is reported only at the
+constant involved in a comparison. For example: \f(CW\*(C`x + 2 > y\*(C'\fR is
+simplified to \f(CW\*(C`x + 1 >= y\*(C'\fR. This is reported only at the
highest warning level because this simplification applies to many
-comparisons, so this warning level will give a very large number of
+comparisons, so this warning level gives a very large number of
false positives.
.RE
.RS 4
.RE
-.IP "\fB\-Wsuggest\-attribute=\fR[\fBpure\fR|\fBconst\fR|\fBnoreturn\fR]" 4
-.IX Item "-Wsuggest-attribute=[pure|const|noreturn]"
+.IP "\fB\-Wsuggest\-attribute=\fR[\fBpure\fR|\fBconst\fR|\fBnoreturn\fR|\fBformat\fR]" 4
+.IX Item "-Wsuggest-attribute=[pure|const|noreturn|format]"
Warn for cases where adding an attribute may be beneficial. The
attributes currently supported are listed below.
.RS 4
\&\f(CW\*(C`pure\*(C'\fR, \f(CW\*(C`const\*(C'\fR or \f(CW\*(C`noreturn\*(C'\fR. The compiler only warns for
functions visible in other compilation units or (in the case of \f(CW\*(C`pure\*(C'\fR and
\&\f(CW\*(C`const\*(C'\fR) if it cannot prove that the function returns normally. A function
-returns normally if it doesn't contain an infinite loop nor returns abnormally
+returns normally if it doesn't contain an infinite loop or return abnormally
by throwing, calling \f(CW\*(C`abort()\*(C'\fR or trapping. This analysis requires option
\&\fB\-fipa\-pure\-const\fR, which is enabled by default at \fB\-O\fR and
higher. Higher optimization levels improve the accuracy of the analysis.
+.IP "\fB\-Wsuggest\-attribute=format\fR" 4
+.IX Item "-Wsuggest-attribute=format"
+.PD 0
+.IP "\fB\-Wmissing\-format\-attribute\fR" 4
+.IX Item "-Wmissing-format-attribute"
+.PD
+Warn about function pointers that might be candidates for \f(CW\*(C`format\*(C'\fR
+attributes. Note these are only possible candidates, not absolute ones.
+\&\s-1GCC\s0 guesses that function pointers with \f(CW\*(C`format\*(C'\fR attributes that
+are used in assignment, initialization, parameter passing or return
+statements should have a corresponding \f(CW\*(C`format\*(C'\fR attribute in the
+resulting type. I.e. the left-hand side of the assignment or
+initialization, the type of the parameter variable, or the return type
+of the containing function respectively should also have a \f(CW\*(C`format\*(C'\fR
+attribute to avoid the warning.
+.Sp
+\&\s-1GCC\s0 also warns about function definitions that might be
+candidates for \f(CW\*(C`format\*(C'\fR attributes. Again, these are only
+possible candidates. \s-1GCC\s0 guesses that \f(CW\*(C`format\*(C'\fR attributes
+might be appropriate for any function that calls a function like
+\&\f(CW\*(C`vprintf\*(C'\fR or \f(CW\*(C`vscanf\*(C'\fR, but this might not always be the
+case, and some functions for which \f(CW\*(C`format\*(C'\fR attributes are
+appropriate may not be detected.
.RE
.RS 4
.RE
compiler output harder to read. Using this command-line option tells
\&\s-1GCC\s0 to emit warnings from system headers as if they occurred in user
code. However, note that using \fB\-Wall\fR in conjunction with this
-option will \fInot\fR warn about unknown pragmas in system
+option does \fInot\fR warn about unknown pragmas in system
headers\-\-\-for that, \fB\-Wunknown\-pragmas\fR must also be used.
.IP "\fB\-Wtrampolines\fR" 4
.IX Item "-Wtrampolines"
likely maximum error that the computation introduces, and allow for it
when performing comparisons (and when producing output, but that's a
different problem). In particular, instead of testing for equality, you
-would check to see whether the two values have ranges that overlap; and
+should check to see whether the two values have ranges that overlap; and
this is done with the relational operators, so equality comparisons are
probably mistaken.
.IP "\fB\-Wtraditional\fR (C and Objective-C only)" 4
.IP "\(bu" 4
Macro parameters that appear within string literals in the macro body.
In traditional C macro replacement takes place within string literals,
-but does not in \s-1ISO\s0 C.
+but in \s-1ISO\s0 C it does not.
.IP "\(bu" 4
In traditional C, some preprocessor directives did not exist.
-Traditional preprocessors would only consider a line to be a directive
+Traditional preprocessors only considered a line to be a directive
if the \fB#\fR appeared in column 1 on the line. Therefore
\&\fB\-Wtraditional\fR warns about directives that traditional C
-understands but would ignore because the \fB#\fR does not appear as the
+understands but ignores because the \fB#\fR does not appear as the
first character on the line. It also suggests you hide directives like
\&\fB#pragma\fR not understood by traditional C by indenting them. Some
-traditional implementations would not recognize \fB#elif\fR, so it
+traditional implementations do not recognize \fB#elif\fR, so this option
suggests avoiding it altogether.
.IP "\(bu" 4
A function-like macro that appears without arguments.
.IP "\(bu" 4
Conversions by prototypes between fixed/floating\-point values and vice
versa. The absence of these prototypes when compiling with traditional
-C would cause serious problems. This is a subset of the possible
-conversion warnings, for the full set use \fB\-Wtraditional\-conversion\fR.
+C causes serious problems. This is a subset of the possible
+conversion warnings; for the full set use \fB\-Wtraditional\-conversion\fR.
.IP "\(bu" 4
Use of \s-1ISO\s0 C style function definitions. This warning intentionally is
\&\fInot\fR issued for prototype declarations or variadic functions
-because these \s-1ISO\s0 C features will appear in your code when using
+because these \s-1ISO\s0 C features appear in your code when using
libiberty's traditional C compatibility macros, \f(CW\*(C`PARAMS\*(C'\fR and
\&\f(CW\*(C`VPARAMS\*(C'\fR. This warning is also bypassed for nested functions
because that feature is already a \s-1GCC\s0 extension and thus not relevant to
.IX Item "-Wshadow"
Warn whenever a local variable or type declaration shadows another variable,
parameter, type, or class member (in \*(C+), or whenever a built-in function
-is shadowed. Note that in \*(C+, the compiler will not warn if a local variable
-shadows a struct/class/enum, but will warn if it shadows an explicit typedef.
+is shadowed. Note that in \*(C+, the compiler warns if a local variable
+shadows an explicit typedef, but not if it shadows a struct/class/enum.
.IP "\fB\-Wlarger\-than=\fR\fIlen\fR" 4
.IX Item "-Wlarger-than=len"
Warn whenever an object of larger than \fIlen\fR bytes is defined.
.RE
.IP "\fB\-Wunsafe\-loop\-optimizations\fR" 4
.IX Item "-Wunsafe-loop-optimizations"
-Warn if the loop cannot be optimized because the compiler could not
+Warn if the loop cannot be optimized because the compiler cannot
assume anything on the bounds of the loop indices. With
-\&\fB\-funsafe\-loop\-optimizations\fR warn if the compiler made
+\&\fB\-funsafe\-loop\-optimizations\fR warn if the compiler makes
such assumptions.
.IP "\fB\-Wno\-pedantic\-ms\-format\fR (MinGW targets only)" 4
.IX Item "-Wno-pedantic-ms-format (MinGW targets only)"
-Disables the warnings about non-ISO \f(CW\*(C`printf\*(C'\fR / \f(CW\*(C`scanf\*(C'\fR format
-width specifiers \f(CW\*(C`I32\*(C'\fR, \f(CW\*(C`I64\*(C'\fR, and \f(CW\*(C`I\*(C'\fR used on Windows targets
-depending on the \s-1MS\s0 runtime, when you are using the options \fB\-Wformat\fR
-and \fB\-pedantic\fR without gnu-extensions.
+When used in combination with \fB\-Wformat\fR
+and \fB\-pedantic\fR without \s-1GNU\s0 extensions, this option
+disables the warnings about non-ISO \f(CW\*(C`printf\*(C'\fR / \f(CW\*(C`scanf\*(C'\fR format
+width specifiers \f(CW\*(C`I32\*(C'\fR, \f(CW\*(C`I64\*(C'\fR, and \f(CW\*(C`I\*(C'\fR used on Windows targets,
+which depend on the \s-1MS\s0 runtime.
.IP "\fB\-Wpointer\-arith\fR" 4
.IX Item "-Wpointer-arith"
Warn about anything that depends on the \*(L"size of\*(R" a function type or
of \f(CW\*(C`void\*(C'\fR. \s-1GNU\s0 C assigns these types a size of 1, for
convenience in calculations with \f(CW\*(C`void *\*(C'\fR pointers and pointers
to functions. In \*(C+, warn also when an arithmetic operation involves
-\&\f(CW\*(C`NULL\*(C'\fR. This warning is also enabled by \fB\-pedantic\fR.
+\&\f(CW\*(C`NULL\*(C'\fR. This warning is also enabled by \fB\-Wpedantic\fR.
.IP "\fB\-Wtype\-limits\fR" 4
.IX Item "-Wtype-limits"
Warn if a comparison is always true or always false due to the limited
.IX Item "-Wwrite-strings"
When compiling C, give string constants the type \f(CW\*(C`const
char[\f(CIlength\f(CW]\*(C'\fR so that copying the address of one into a
-non\-\f(CW\*(C`const\*(C'\fR \f(CW\*(C`char *\*(C'\fR pointer will get a warning. These
-warnings will help you find at compile time code that can try to write
+non\-\f(CW\*(C`const\*(C'\fR \f(CW\*(C`char *\*(C'\fR pointer produces a warning. These
+warnings help you find at compile time code that can try to write
into a string constant, but only if you have been very careful about
-using \f(CW\*(C`const\*(C'\fR in declarations and prototypes. Otherwise, it will
-just be a nuisance. This is why we did not make \fB\-Wall\fR request
+using \f(CW\*(C`const\*(C'\fR in declarations and prototypes. Otherwise, it is
+just a nuisance. This is why we did not make \fB\-Wall\fR request
these warnings.
.Sp
When compiling \*(C+, warn about the deprecated conversion from string
using \fB\-Wno\-sign\-conversion\fR.
.Sp
For \*(C+, also warn for confusing overload resolution for user-defined
-conversions; and conversions that will never use a type conversion
+conversions; and conversions that never use a type conversion
operator: conversions to \f(CW\*(C`void\*(C'\fR, the same type, a base class or a
reference to them. Warnings about conversions between signed and
unsigned integers are disabled by default in \*(C+ unless
.IX Item "-Wzero-as-null-pointer-constant ( and Objective- only)"
Warn when a literal '0' is used as null pointer constant. This can
be useful to facilitate the conversion to \f(CW\*(C`nullptr\*(C'\fR in \*(C+11.
+.IP "\fB\-Wuseless\-cast\fR (\*(C+ and Objective\-\*(C+ only)" 4
+.IX Item "-Wuseless-cast ( and Objective- only)"
+Warn when an expression is casted to its own type.
.IP "\fB\-Wempty\-body\fR" 4
.IX Item "-Wempty-body"
Warn if an empty body occurs in an \fBif\fR, \fBelse\fR or \fBdo
value, like assigning a signed integer expression to an unsigned
integer variable. An explicit cast silences the warning. In C, this
option is enabled also by \fB\-Wconversion\fR.
+.IP "\fB\-Wsizeof\-pointer\-memaccess\fR" 4
+.IX Item "-Wsizeof-pointer-memaccess"
+Warn for suspicious length parameters to certain string and memory built-in
+functions if the argument uses \f(CW\*(C`sizeof\*(C'\fR. This warning warns e.g.
+about \f(CW\*(C`memset (ptr, 0, sizeof (ptr));\*(C'\fR if \f(CW\*(C`ptr\*(C'\fR is not an array,
+but a pointer, and suggests a possible fix, or about
+\&\f(CW\*(C`memcpy (&foo, ptr, sizeof (&foo));\*(C'\fR. This warning is enabled by
+\&\fB\-Wall\fR.
.IP "\fB\-Waddress\fR" 4
.IX Item "-Waddress"
Warn about suspicious uses of memory addresses. These include using
Warn if any functions that return structures or unions are defined or
called. (In languages where you can return an array, this also elicits
a warning.)
+.IP "\fB\-Wno\-aggressive\-loop\-optimizations\fR" 4
+.IX Item "-Wno-aggressive-loop-optimizations"
+Warn if in a loop with constant number of iterations the compiler detects
+undefined behavior in some statement during one or more of the iterations.
.IP "\fB\-Wno\-attributes\fR" 4
.IX Item "-Wno-attributes"
Do not warn if an unexpected \f(CW\*(C`_\|_attribute_\|_\*(C'\fR is used, such as
unrecognized attributes, function attributes applied to variables,
-etc. This will not stop errors for incorrect use of supported
+etc. This does not stop errors for incorrect use of supported
attributes.
.IP "\fB\-Wno\-builtin\-macro\-redefined\fR" 4
.IX Item "-Wno-builtin-macro-redefined"
.IX Item "-Wmissing-prototypes (C and Objective-C only)"
Warn if a global function is defined without a previous prototype
declaration. This warning is issued even if the definition itself
-provides a prototype. The aim is to detect global functions that
-are not declared in header files.
+provides a prototype. Use this option to detect global functions
+that do not have a matching prototype declaration in a header file.
+This option is not valid for \*(C+ because all function declarations
+provide prototypes and a non-matching declaration will declare an
+overload rather than conflict with an earlier declaration.
+Use \fB\-Wmissing\-declarations\fR to detect missing declarations in \*(C+.
.IP "\fB\-Wmissing\-declarations\fR" 4
.IX Item "-Wmissing-declarations"
Warn if a global function is defined without a previous declaration.
Do so even if the definition itself provides a prototype.
Use this option to detect global functions that are not declared in
-header files. In \*(C+, no warnings are issued for function templates,
+header files. In C, no warnings are issued for functions with previous
+non-prototype declarations; use \fB\-Wmissing\-prototype\fR to detect
+missing prototypes. In \*(C+, no warnings are issued for function templates,
or for inline functions, or for functions in anonymous namespaces.
.IP "\fB\-Wmissing\-field\-initializers\fR" 4
.IX Item "-Wmissing-field-initializers"
Warn if a structure's initializer has some fields missing. For
-example, the following code would cause such a warning, because
+example, the following code causes such a warning, because
\&\f(CW\*(C`x.h\*(C'\fR is implicitly zero:
.Sp
.Vb 2
.Ve
.Sp
This option does not warn about designated initializers, so the following
-modification would not trigger a warning:
+modification does not trigger a warning:
.Sp
.Vb 2
\& struct s { int f, g, h; };
.Sp
This warning is included in \fB\-Wextra\fR. To get other \fB\-Wextra\fR
warnings without this one, use \fB\-Wextra \-Wno\-missing\-field\-initializers\fR.
-.IP "\fB\-Wmissing\-format\-attribute\fR" 4
-.IX Item "-Wmissing-format-attribute"
-Warn about function pointers that might be candidates for \f(CW\*(C`format\*(C'\fR
-attributes. Note these are only possible candidates, not absolute ones.
-\&\s-1GCC\s0 will guess that function pointers with \f(CW\*(C`format\*(C'\fR attributes that
-are used in assignment, initialization, parameter passing or return
-statements should have a corresponding \f(CW\*(C`format\*(C'\fR attribute in the
-resulting type. I.e. the left-hand side of the assignment or
-initialization, the type of the parameter variable, or the return type
-of the containing function respectively should also have a \f(CW\*(C`format\*(C'\fR
-attribute to avoid the warning.
-.Sp
-\&\s-1GCC\s0 will also warn about function definitions that might be
-candidates for \f(CW\*(C`format\*(C'\fR attributes. Again, these are only
-possible candidates. \s-1GCC\s0 will guess that \f(CW\*(C`format\*(C'\fR attributes
-might be appropriate for any function that calls a function like
-\&\f(CW\*(C`vprintf\*(C'\fR or \f(CW\*(C`vscanf\*(C'\fR, but this might not always be the
-case, and some functions for which \f(CW\*(C`format\*(C'\fR attributes are
-appropriate may not be detected.
.IP "\fB\-Wno\-multichar\fR" 4
.IX Item "-Wno-multichar"
Do not warn if a multicharacter constant (\fB'\s-1FOOF\s0'\fR) is used.
this, which is why this option is not the default.
.Sp
You can switch the warning off for all characters by writing
-\&\fB\-Wnormalized=none\fR. You would only want to do this if you
-were using some other normalization scheme (like \*(L"D\*(R"), because
+\&\fB\-Wnormalized=none\fR. You should only do this if you
+are using some other normalization scheme (like \*(L"D\*(R"), because
otherwise you can easily create bugs that are literally impossible to see.
.Sp
Some characters in \s-1ISO\s0 10646 have distinct meanings but look identical
in some fonts or display methodologies, especially once formatting has
been applied. For instance \f(CW\*(C`\eu207F\*(C'\fR, \*(L"\s-1SUPERSCRIPT\s0 \s-1LATIN\s0 \s-1SMALL\s0
-\&\s-1LETTER\s0 N\*(R", will display just like a regular \f(CW\*(C`n\*(C'\fR that has been
+\&\s-1LETTER\s0 N\*(R", displays just like a regular \f(CW\*(C`n\*(C'\fR that has been
placed in a superscript. \s-1ISO\s0 10646 defines the \fI\s-1NFKC\s0\fR
normalization scheme to convert all these into a standard form as
-well, and \s-1GCC\s0 will warn if your code is not in \s-1NFKC\s0 if you use
+well, and \s-1GCC\s0 warns if your code is not in \s-1NFKC\s0 if you use
\&\fB\-Wnormalized=nfkc\fR. This warning is comparable to warning
about every identifier that contains the letter O because it might be
confused with the digit 0, and so is not the default, but may be
-useful as a local coding convention if the programming environment is
-unable to be fixed to display these characters distinctly.
+useful as a local coding convention if the programming environment
+cannot be fixed to display these characters distinctly.
.IP "\fB\-Wno\-deprecated\fR" 4
.IX Item "-Wno-deprecated"
Do not warn about usage of deprecated features.
attribute has no effect on the layout or size of the structure.
Such structures may be mis-aligned for little benefit. For
instance, in this code, the variable \f(CW\*(C`f.x\*(C'\fR in \f(CW\*(C`struct bar\*(C'\fR
-will be misaligned even though \f(CW\*(C`struct bar\*(C'\fR does not itself
+is misaligned even though \f(CW\*(C`struct bar\*(C'\fR does not itself
have the packed attribute:
.Sp
.Vb 8
.IP "\fB\-Wnested\-externs\fR (C and Objective-C only)" 4
.IX Item "-Wnested-externs (C and Objective-C only)"
Warn if an \f(CW\*(C`extern\*(C'\fR declaration is encountered within a function.
+.IP "\fB\-Wno\-inherited\-variadic\-ctor\fR" 4
+.IX Item "-Wno-inherited-variadic-ctor"
+Suppress warnings about use of \*(C+11 inheriting constructors when the
+base class inherited from has a C variadic constructor; the warning is
+on by default because the ellipsis is not inherited.
.IP "\fB\-Winline\fR" 4
.IX Item "-Winline"
-Warn if a function can not be inlined and it was declared as inline.
-Even with this option, the compiler will not warn about failures to
+Warn if a function that is declared as inline cannot be inlined.
+Even with this option, the compiler does not warn about failures to
inline functions declared in system headers.
.Sp
The compiler uses a variety of heuristics to determine whether or not
type. According to the 1998 \s-1ISO\s0 \*(C+ standard, applying \fBoffsetof\fR
to a non-POD type is undefined. In existing \*(C+ implementations,
however, \fBoffsetof\fR typically gives meaningful results even when
-applied to certain kinds of non-POD types. (Such as a simple
+applied to certain kinds of non-POD types (such as a simple
\&\fBstruct\fR that fails to be a \s-1POD\s0 type only by virtue of having a
-constructor.) This flag is for users who are aware that they are
+constructor). This flag is for users who are aware that they are
writing nonportable code and who have deliberately chosen to ignore the
warning about it.
.Sp
.IP "\fB\-Wlong\-long\fR" 4
.IX Item "-Wlong-long"
Warn if \fBlong long\fR type is used. This is enabled by either
-\&\fB\-pedantic\fR or \fB\-Wtraditional\fR in \s-1ISO\s0 C90 and \*(C+98
+\&\fB\-Wpedantic\fR or \fB\-Wtraditional\fR in \s-1ISO\s0 C90 and \*(C+98
modes. To inhibit the warning messages, use \fB\-Wno\-long\-long\fR.
.IP "\fB\-Wvariadic\-macros\fR" 4
.IX Item "-Wvariadic-macros"
Warn if variadic macros are used in pedantic \s-1ISO\s0 C90 mode, or the \s-1GNU\s0
alternate syntax when in pedantic \s-1ISO\s0 C99 mode. This is default.
To inhibit the warning messages, use \fB\-Wno\-variadic\-macros\fR.
+.IP "\fB\-Wvarargs\fR" 4
+.IX Item "-Wvarargs"
+Warn upon questionable usage of the macros used to handle variable
+arguments like \fBva_start\fR. This is default. To inhibit the
+warning messages, use \fB\-Wno\-varargs\fR.
.IP "\fB\-Wvector\-operation\-performance\fR" 4
.IX Item "-Wvector-operation-performance"
Warn if vector operation is not implemented via \s-1SIMD\s0 capabilities of the
using scalars of wider type, which normally is more performance efficient;
and \f(CW\*(C`as a single scalar\*(C'\fR, which means that vector fits into a
scalar type.
+.IP "\fB\-Wno\-virtual\-move\-assign\fR" 4
+.IX Item "-Wno-virtual-move-assign"
+Suppress warnings about inheriting from a virtual base with a
+non-trivial \*(C+11 move assignment operator. This is dangerous because
+if the virtual base is reachable along more than one path, it will be
+moved multiple times, which can mean both objects end up in the
+moved-from state. If the move assignment operator is written to avoid
+moving from a moved-from object, this warning can be disabled.
.IP "\fB\-Wvla\fR" 4
.IX Item "-Wvla"
Warn if variable length array is used in the code.
-\&\fB\-Wno\-vla\fR will prevent the \fB\-pedantic\fR warning of
+\&\fB\-Wno\-vla\fR prevents the \fB\-Wpedantic\fR warning of
the variable length array.
.IP "\fB\-Wvolatile\-register\-var\fR" 4
.IX Item "-Wvolatile-register-var"
.IX Item "-Wdisabled-optimization"
Warn if a requested optimization pass is disabled. This warning does
not generally indicate that there is anything wrong with your code; it
-merely indicates that \s-1GCC\s0's optimizers were unable to handle the code
+merely indicates that \s-1GCC\s0's optimizers are unable to handle the code
effectively. Often, the problem is that your code is too big or too
-complex; \s-1GCC\s0 will refuse to optimize programs when the optimization
+complex; \s-1GCC\s0 refuses to optimize programs when the optimization
itself is likely to take inordinate amounts of time.
.IP "\fB\-Wpointer\-sign\fR (C and Objective-C only)" 4
.IX Item "-Wpointer-sign (C and Objective-C only)"
Warn for pointer argument passing or assignment with different signedness.
This option is only supported for C and Objective-C. It is implied by
-\&\fB\-Wall\fR and by \fB\-pedantic\fR, which can be disabled with
+\&\fB\-Wall\fR and by \fB\-Wpedantic\fR, which can be disabled with
\&\fB\-Wno\-pointer\-sign\fR.
.IP "\fB\-Wstack\-protector\fR" 4
.IX Item "-Wstack-protector"
This option is only active when \fB\-fstack\-protector\fR is active. It
-warns about functions that will not be protected against stack smashing.
+warns about functions that are not protected against stack smashing.
.IP "\fB\-Wno\-mudflap\fR" 4
.IX Item "-Wno-mudflap"
Suppress warnings about constructs that cannot be instrumented by
C99, it was raised to 4095. \*(C+98 does not specify a normative
minimum maximum, so we do not diagnose overlength strings in \*(C+.
.Sp
-This option is implied by \fB\-pedantic\fR, and can be disabled with
+This option is implied by \fB\-Wpedantic\fR, and can be disabled with
\&\fB\-Wno\-overlength\-strings\fR.
.IP "\fB\-Wunsuffixed\-float\-constants\fR (C and Objective-C only)" 4
.IX Item "-Wunsuffixed-float-constants (C and Objective-C only)"
-\&\s-1GCC\s0 will issue a warning for any floating constant that does not have
-a suffix. When used together with \fB\-Wsystem\-headers\fR it will
-warn about such constants in system header files. This can be useful
+Issue a warning for any floating constant that does not have
+a suffix. When used together with \fB\-Wsystem\-headers\fR it
+warns about such constants in system header files. This can be useful
when preparing code to use with the \f(CW\*(C`FLOAT_CONST_DECIMAL64\*(C'\fR pragma
from the decimal floating-point extension to C99.
-.Sh "Options for Debugging Your Program or \s-1GCC\s0"
+.SS "Options for Debugging Your Program or \s-1GCC\s0"
.IX Subsection "Options for Debugging Your Program or GCC"
\&\s-1GCC\s0 has various special options that are used for debugging
either your program or \s-1GCC:\s0
.Sp
On most systems that use stabs format, \fB\-g\fR enables use of extra
debugging information that only \s-1GDB\s0 can use; this extra information
-makes debugging work better in \s-1GDB\s0 but will probably make other debuggers
+makes debugging work better in \s-1GDB\s0 but probably makes other debuggers
crash or
refuse to read the program. If you want to control for certain whether
to generate the extra information, use \fB\-gstabs+\fR, \fB\-gstabs\fR,
produce surprising results: some variables you declared may not exist
at all; flow of control may briefly move where you did not expect it;
some statements may not be executed because they compute constant
-results or their values were already at hand; some statements may
-execute in different places because they were moved out of loops.
+results or their values are already at hand; some statements may
+execute in different places because they have been moved out of loops.
.Sp
Nevertheless it proves possible to debug optimized output. This makes
it reasonable to use the optimizer for programs that might have bugs.
.Sp
The following options are useful when \s-1GCC\s0 is generated with the
capability for more than one debugging format.
+.IP "\fB\-gsplit\-dwarf\fR" 4
+.IX Item "-gsplit-dwarf"
+Separate as much dwarf debugging information as possible into a
+separate output file with the extension .dwo. This option allows
+the build system to avoid linking files with debug information. To
+be useful, this option requires a debugger capable of reading .dwo
+files.
.IP "\fB\-ggdb\fR" 4
.IX Item "-ggdb"
Produce debugging information for use by \s-1GDB\s0. This means to use the
most expressive format available (\s-1DWARF\s0 2, stabs, or the native format
if neither of those are supported), including \s-1GDB\s0 extensions if at all
possible.
+.IP "\fB\-gpubnames\fR" 4
+.IX Item "-gpubnames"
+Generate dwarf .debug_pubnames and .debug_pubtypes sections.
.IP "\fB\-gstabs\fR" 4
.IX Item "-gstabs"
Produce debugging information in stabs format (if that is supported),
object file, emit it in all object files using the class. This option
should be used only with debuggers that are unable to handle the way \s-1GCC\s0
normally emits debugging information for classes because using this
-option will increase the size of debugging information by as much as a
+option increases the size of debugging information by as much as a
factor of two.
-.IP "\fB\-fno\-debug\-types\-section\fR" 4
-.IX Item "-fno-debug-types-section"
-By default when using \s-1DWARF\s0 v4 or higher type DIEs will be put into
-their own .debug_types section instead of making them part of the
-\&.debug_info section. It is more efficient to put them in a separate
-comdat sections since the linker will then be able to remove duplicates.
-But not all \s-1DWARF\s0 consumers support .debug_types sections yet.
+.IP "\fB\-fdebug\-types\-section\fR" 4
+.IX Item "-fdebug-types-section"
+When using \s-1DWARF\s0 Version 4 or higher, type DIEs can be put into
+their own \f(CW\*(C`.debug_types\*(C'\fR section instead of making them part of the
+\&\f(CW\*(C`.debug_info\*(C'\fR section. It is more efficient to put them in a separate
+comdat sections since the linker can then remove duplicates.
+But not all \s-1DWARF\s0 consumers support \f(CW\*(C`.debug_types\*(C'\fR sections yet
+and on some objects \f(CW\*(C`.debug_types\*(C'\fR produces larger instead of smaller
+debugging information.
.IP "\fB\-gstabs+\fR" 4
.IX Item "-gstabs+"
Produce debugging information in stabs format (if that is supported),
assembler (\s-1GAS\s0) to fail with an error.
.IP "\fB\-gdwarf\-\fR\fIversion\fR" 4
.IX Item "-gdwarf-version"
-Produce debugging information in \s-1DWARF\s0 format (if that is
-supported). This is the format used by \s-1DBX\s0 on \s-1IRIX\s0 6. The value
-of \fIversion\fR may be either 2, 3 or 4; the default version is 2.
+Produce debugging information in \s-1DWARF\s0 format (if that is supported).
+The value of \fIversion\fR may be either 2, 3 or 4; the default version
+for most targets is 4.
.Sp
-Note that with \s-1DWARF\s0 version 2 some ports require, and will always
-use, some non-conflicting \s-1DWARF\s0 3 extensions in the unwind tables.
+Note that with \s-1DWARF\s0 Version 2, some ports require and always
+use some non-conflicting \s-1DWARF\s0 3 extensions in the unwind tables.
.Sp
Version 4 may require \s-1GDB\s0 7.0 and \fB\-fvar\-tracking\-assignments\fR
for maximum benefit.
DW_AT_producer attribute in \s-1DWARF\s0 debugging information. The options
are concatenated with spaces separating them from each other and from
the compiler version. See also \fB\-frecord\-gcc\-switches\fR for another
-way of storing compiler options into the object file.
+way of storing compiler options into the object file. This is the default.
.IP "\fB\-gno\-record\-gcc\-switches\fR" 4
.IX Item "-gno-record-gcc-switches"
Disallow appending command-line options to the DW_AT_producer attribute
-in \s-1DWARF\s0 debugging information. This is the default.
+in \s-1DWARF\s0 debugging information.
.IP "\fB\-gstrict\-dwarf\fR" 4
.IX Item "-gstrict-dwarf"
Disallow using extensions of later \s-1DWARF\s0 standard version than selected
\&\fB\-gdwarf\-\fR\fIversion\fR.
.IP "\fB\-gvms\fR" 4
.IX Item "-gvms"
-Produce debugging information in \s-1VMS\s0 debug format (if that is
-supported). This is the format used by \s-1DEBUG\s0 on \s-1VMS\s0 systems.
+Produce debugging information in Alpha/VMS debug format (if that is
+supported). This is the format used by \s-1DEBUG\s0 on Alpha/VMS systems.
.IP "\fB\-g\fR\fIlevel\fR" 4
.IX Item "-glevel"
.PD 0
debug level for \s-1DWARF\s0.
.IP "\fB\-gtoggle\fR" 4
.IX Item "-gtoggle"
-Turn off generation of debug info, if leaving out this option would have
-generated it, or turn it on at level 2 otherwise. The position of this
-argument in the command line does not matter, it takes effect after all
+Turn off generation of debug info, if leaving out this option
+generates it, or turn it on at level 2 otherwise. The position of this
+argument in the command line does not matter; it takes effect after all
other options are processed, and it does so only once, no matter how
many times it is given. This is mainly intended to be used with
\&\fB\-fcompare\-debug\fR.
+.IP "\fB\-fsanitize=address\fR" 4
+.IX Item "-fsanitize=address"
+Enable AddressSanitizer, a fast memory error detector.
+Memory access instructions will be instrumented to detect
+out-of-bounds and use-after-free bugs.
+See <\fBhttp://code.google.com/p/address\-sanitizer/\fR> for more details.
+.IP "\fB\-fsanitize=thread\fR" 4
+.IX Item "-fsanitize=thread"
+Enable ThreadSanitizer, a fast data race detector.
+Memory access instructions will be instrumented to detect
+data race bugs.
+See <\fBhttp://code.google.com/p/data\-race\-test/wiki/ThreadSanitizer\fR> for more details.
.IP "\fB\-fdump\-final\-insns\fR[\fB=\fR\fIfile\fR]" 4
.IX Item "-fdump-final-insns[=file]"
Dump the final internal representation (\s-1RTL\s0) to \fIfile\fR. If the
optional argument is omitted (or if \fIfile\fR is \f(CW\*(C`.\*(C'\fR), the name
-of the dump file will be determined by appending \f(CW\*(C`.gkd\*(C'\fR to the
+of the dump file is determined by appending \f(CW\*(C`.gkd\*(C'\fR to the
compilation output file name.
.IP "\fB\-fcompare\-debug\fR[\fB=\fR\fIopts\fR]" 4
.IX Item "-fcompare-debug[=opts]"
.Sp
To verify full coverage during \fB\-fcompare\-debug\fR testing, set
\&\fB\s-1GCC_COMPARE_DEBUG\s0\fR to say \fB\-fcompare\-debug\-not\-overridden\fR,
-which \s-1GCC\s0 will reject as an invalid option in any actual compilation
+which \s-1GCC\s0 rejects as an invalid option in any actual compilation
(rather than preprocessing, assembly or linking). To get just a
warning, setting \fB\s-1GCC_COMPARE_DEBUG\s0\fR to \fB\-w%n\-fcompare\-debug
not overridden\fR will do.
other than debugging the compiler proper.
.IP "\fB\-feliminate\-dwarf2\-dups\fR" 4
.IX Item "-feliminate-dwarf2-dups"
-Compress \s-1DWARF2\s0 debugging information by eliminating duplicated
+Compress \s-1DWARF\s0 2 debugging information by eliminating duplicated
information about each symbol. This option only makes sense when
-generating \s-1DWARF2\s0 debugging information with \fB\-gdwarf\-2\fR.
+generating \s-1DWARF\s0 2 debugging information with \fB\-gdwarf\-2\fR.
.IP "\fB\-femit\-struct\-debug\-baseonly\fR" 4
.IX Item "-femit-struct-debug-baseonly"
Emit debug information for struct-like types
only when the base name of the compilation source file
-matches the base name of file in which the struct was defined.
+matches the base name of file in which the struct is defined.
.Sp
This option substantially reduces the size of debugging information,
but at significant potential loss in type information to the debugger.
.IX Item "-femit-struct-debug-reduced"
Emit debug information for struct-like types
only when the base name of the compilation source file
-matches the base name of file in which the type was defined,
+matches the base name of file in which the type is defined,
unless the struct is a template or defined in a system header.
.Sp
This option significantly reduces the size of debugging information,
.IP "\fB\-femit\-struct\-debug\-detailed\fR[\fB=\fR\fIspec-list\fR]" 4
.IX Item "-femit-struct-debug-detailed[=spec-list]"
Specify the struct-like types
-for which the compiler will generate debug information.
+for which the compiler generates debug information.
The intent is to reduce duplicate struct debug information
between different object files within the same program.
.Sp
This option is a detailed version of
\&\fB\-femit\-struct\-debug\-reduced\fR and \fB\-femit\-struct\-debug\-baseonly\fR,
-which will serve for most needs.
+which serves for most needs.
.Sp
A specification has the syntax[\fBdir:\fR|\fBind:\fR][\fBord:\fR|\fBgen:\fR](\fBany\fR|\fBsys\fR|\fBbase\fR|\fBnone\fR)
.Sp
structs that are used directly (\fBdir:\fR) or used indirectly (\fBind:\fR).
A struct type is used directly when it is the type of a variable, member.
Indirect uses arise through pointers to structs.
-That is, when use of an incomplete struct would be legal, the use is indirect.
+That is, when use of an incomplete struct is valid, the use is indirect.
An example is
\&\fBstruct one direct; struct two * indirect;\fR.
.Sp
but \fB\-femit\-struct\-debug\-detailed\fR does not yet implement them.
.Sp
The third word specifies the source files for those
-structs for which the compiler will emit debug information.
+structs for which the compiler should emit debug information.
The values \fBnone\fR and \fBany\fR have the normal meaning.
The value \fBbase\fR means that
the base of name of the file in which the type declaration appears
must match the base of the name of the main compilation file.
-In practice, this means that
-types declared in \fIfoo.c\fR and \fIfoo.h\fR will have debug information,
-but types declared in other header will not.
+In practice, this means that when compiling \fIfoo.c\fR, debug information
+is generated for types declared in that file and \fIfoo.h\fR,
+but not other header files.
The value \fBsys\fR means those types satisfying \fBbase\fR
or declared in system or compiler headers.
.Sp
.IX Item "-fmem-report"
Makes the compiler print some statistics about permanent memory
allocation when it finishes.
+.IP "\fB\-fmem\-report\-wpa\fR" 4
+.IX Item "-fmem-report-wpa"
+Makes the compiler print some statistics about permanent memory
+allocation for the \s-1WPA\s0 phase only.
.IP "\fB\-fpre\-ipa\-mem\-report\fR" 4
.IX Item "-fpre-ipa-mem-report"
.PD 0
.PD
Makes the compiler print some statistics about permanent memory
allocation before or after interprocedural optimization.
+.IP "\fB\-fprofile\-report\fR" 4
+.IX Item "-fprofile-report"
+Makes the compiler print some statistics about consistency of the
+(estimated) profile and effect of individual passes.
.IP "\fB\-fstack\-usage\fR" 4
.IX Item "-fstack-usage"
Makes the compiler output stack usage information for the program, on a
show program coverage. Each source file's note file is called
\&\fI\fIauxname\fI.gcno\fR. Refer to the \fB\-fprofile\-arcs\fR option
above for a description of \fIauxname\fR and instructions on how to
-generate test coverage data. Coverage data will match the source files
-more closely, if you do not optimize.
+generate test coverage data. Coverage data matches the source files
+more closely if you do not optimize.
.IP "\fB\-fdbg\-cnt\-list\fR" 4
.IX Item "-fdbg-cnt-list"
Print the name and the counter upper bound for all debug counters.
Set the internal debug counter upper bound. \fIcounter-value-list\fR
is a comma-separated list of \fIname\fR:\fIvalue\fR pairs
which sets the upper bound of each debug counter \fIname\fR to \fIvalue\fR.
-All debug counters have the initial upper bound of \fI\s-1UINT_MAX\s0\fR,
-thus \fIdbg_cnt()\fR returns true always unless the upper bound is set by this option.
-e.g. With \-fdbg\-cnt=dce:10,tail_call:0
-dbg_cnt(dce) will return true only for first 10 invocations
+All debug counters have the initial upper bound of \f(CW\*(C`UINT_MAX\*(C'\fR;
+thus \f(CW\*(C`dbg_cnt()\*(C'\fR returns true always unless the upper bound
+is set by this option.
+For example, with \fB\-fdbg\-cnt=dce:10,tail_call:0\fR,
+\&\f(CW\*(C`dbg_cnt(dce)\*(C'\fR returns true only for first 10 invocations.
.IP "\fB\-fenable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR" 4
.IX Item "-fenable-kind-pass"
.PD 0
.IP "\fB\-fdisable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR" 4
.IX Item "-fdisable-kind-pass=range-list"
.PD
-This is a set of debugging options that are used to explicitly disable/enable
-optimization passes. For compiler users, regular options for enabling/disabling
-passes should be used instead.
+This is a set of options that are used to explicitly disable/enable
+optimization passes. These options are intended for use for debugging \s-1GCC\s0.
+Compiler users should use regular options for enabling/disabling
+passes instead.
.RS 4
-.IP "*<\-fdisable\-ipa\-\fIpass\fR>" 4
-.IX Item "*<-fdisable-ipa-pass>"
-Disable ipa pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is
+.IP "\fB\-fdisable\-ipa\-\fR\fIpass\fR" 4
+.IX Item "-fdisable-ipa-pass"
+Disable \s-1IPA\s0 pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is
statically invoked in the compiler multiple times, the pass name should be
appended with a sequential number starting from 1.
-.IP "*<\-fdisable\-rtl\-\fIpass\fR>" 4
-.IX Item "*<-fdisable-rtl-pass>"
+.IP "\fB\-fdisable\-rtl\-\fR\fIpass\fR" 4
+.IX Item "-fdisable-rtl-pass"
.PD 0
-.IP "*<\-fdisable\-rtl\-\fIpass\fR=\fIrange-list\fR>" 4
-.IX Item "*<-fdisable-rtl-pass=range-list>"
+.IP "\fB\-fdisable\-rtl\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR" 4
+.IX Item "-fdisable-rtl-pass=range-list"
.PD
-Disable rtl pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is
+Disable \s-1RTL\s0 pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is
statically invoked in the compiler multiple times, the pass name should be
-appended with a sequential number starting from 1. \fIrange-list\fR is a comma
-seperated list of function ranges or assembler names. Each range is a number
-pair seperated by a colon. The range is inclusive in both ends. If the range
+appended with a sequential number starting from 1. \fIrange-list\fR is a
+comma-separated list of function ranges or assembler names. Each range is a number
+pair separated by a colon. The range is inclusive in both ends. If the range
is trivial, the number pair can be simplified as a single number. If the
-function's cgraph node's \fIuid\fR is falling within one of the specified ranges,
+function's call graph node's \fIuid\fR falls within one of the specified ranges,
the \fIpass\fR is disabled for that function. The \fIuid\fR is shown in the
function header of a dump file, and the pass names can be dumped by using
option \fB\-fdump\-passes\fR.
-.IP "*<\-fdisable\-tree\-\fIpass\fR>" 4
-.IX Item "*<-fdisable-tree-pass>"
+.IP "\fB\-fdisable\-tree\-\fR\fIpass\fR" 4
+.IX Item "-fdisable-tree-pass"
.PD 0
-.IP "*<\-fdisable\-tree\-\fIpass\fR=\fIrange-list\fR>" 4
-.IX Item "*<-fdisable-tree-pass=range-list>"
+.IP "\fB\-fdisable\-tree\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR" 4
+.IX Item "-fdisable-tree-pass=range-list"
.PD
Disable tree pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for the description of
option arguments.
-.IP "*<\-fenable\-ipa\-\fIpass\fR>" 4
-.IX Item "*<-fenable-ipa-pass>"
-Enable ipa pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is
+.IP "\fB\-fenable\-ipa\-\fR\fIpass\fR" 4
+.IX Item "-fenable-ipa-pass"
+Enable \s-1IPA\s0 pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is
statically invoked in the compiler multiple times, the pass name should be
appended with a sequential number starting from 1.
-.IP "*<\-fenable\-rtl\-\fIpass\fR>" 4
-.IX Item "*<-fenable-rtl-pass>"
+.IP "\fB\-fenable\-rtl\-\fR\fIpass\fR" 4
+.IX Item "-fenable-rtl-pass"
.PD 0
-.IP "*<\-fenable\-rtl\-\fIpass\fR=\fIrange-list\fR>" 4
-.IX Item "*<-fenable-rtl-pass=range-list>"
+.IP "\fB\-fenable\-rtl\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR" 4
+.IX Item "-fenable-rtl-pass=range-list"
.PD
-Enable rtl pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for option argument
+Enable \s-1RTL\s0 pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for option argument
description and examples.
-.IP "*<\-fenable\-tree\-\fIpass\fR>" 4
-.IX Item "*<-fenable-tree-pass>"
+.IP "\fB\-fenable\-tree\-\fR\fIpass\fR" 4
+.IX Item "-fenable-tree-pass"
.PD 0
-.IP "*<\-fenable\-tree\-\fIpass\fR=\fIrange-list\fR>" 4
-.IX Item "*<-fenable-tree-pass=range-list>"
+.IP "\fB\-fenable\-tree\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR" 4
+.IX Item "-fenable-tree-pass=range-list"
.PD
Enable tree pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for the description
of option arguments.
+.RE
+.RS 4
+.Sp
+Here are some examples showing uses of these options.
.Sp
.Vb 10
\& # disable ccp1 for all functions
\& \-fenable\-tree\-unroll
.Ve
.RE
-.RS 4
-.RE
.IP "\fB\-d\fR\fIletters\fR" 4
.IX Item "-dletters"
.PD 0
.IP "\fB\-fdump\-rtl\-\fR\fIpass\fR" 4
.IX Item "-fdump-rtl-pass"
+.IP "\fB\-fdump\-rtl\-\fR\fIpass\fR\fB=\fR\fIfilename\fR" 4
+.IX Item "-fdump-rtl-pass=filename"
.PD
Says to make debugging dumps during compilation at times specified by
\&\fIletters\fR. This is used for debugging the RTL-based passes of the
compiler. The file names for most of the dumps are made by appending
a pass number and a word to the \fIdumpname\fR, and the files are
-created in the directory of the output file. Note that the pass
-number is computed statically as passes get registered into the pass
-manager. Thus the numbering is not related to the dynamic order of
-execution of passes. In particular, a pass installed by a plugin
-could have a number over 200 even if it executed quite early.
-\&\fIdumpname\fR is generated from the name of the output file, if
-explicitly specified and it is not an executable, otherwise it is the
-basename of the source file. These switches may have different effects
-when \fB\-E\fR is used for preprocessing.
+created in the directory of the output file. In case of
+\&\fB=\fR\fIfilename\fR option, the dump is output on the given file
+instead of the pass numbered dump files. Note that the pass number is
+computed statically as passes get registered into the pass manager.
+Thus the numbering is not related to the dynamic order of execution of
+passes. In particular, a pass installed by a plugin could have a
+number over 200 even if it executed quite early. \fIdumpname\fR is
+generated from the name of the output file, if explicitly specified
+and it is not an executable, otherwise it is the basename of the
+source file. These switches may have different effects when
+\&\fB\-E\fR is used for preprocessing.
.Sp
Debug dumps can be enabled with a \fB\-fdump\-rtl\fR switch or some
\&\fB\-d\fR option \fIletters\fR. Here are the possible
.IX Item "-fdump-rtl-cse2"
.PD
\&\fB\-fdump\-rtl\-cse1\fR and \fB\-fdump\-rtl\-cse2\fR enable dumping after
-the two common sub-expression elimination passes.
+the two common subexpression elimination passes.
.IP "\fB\-fdump\-rtl\-dce\fR" 4
.IX Item "-fdump-rtl-dce"
Dump after the standalone dead code elimination passes.
.IP "\fB\-dp\fR" 4
.IX Item "-dp"
Annotate the assembler output with a comment indicating which
-pattern and alternative was used. The length of each instruction is
+pattern and alternative is used. The length of each instruction is
also printed.
.IP "\fB\-dP\fR" 4
.IX Item "-dP"
Dump the \s-1RTL\s0 in the assembler output as a comment before each instruction.
Also turns on \fB\-dp\fR annotation.
-.IP "\fB\-dv\fR" 4
-.IX Item "-dv"
-For each of the other indicated dump files (\fB\-fdump\-rtl\-\fR\fIpass\fR),
-dump a representation of the control flow graph suitable for viewing with \s-1VCG\s0
-to \fI\fIfile\fI.\fIpass\fI.vcg\fR.
.IP "\fB\-dx\fR" 4
.IX Item "-dx"
Just generate \s-1RTL\s0 for a function instead of compiling it. Usually used
file name is generated by appending a suffix ending in
\&\fB.statistics\fR to the source file name, and the file is created in
the same directory as the output file. If the \fB\-\fR\fIoption\fR
-form is used, \fB\-stats\fR will cause counters to be summed over the
-whole compilation unit while \fB\-details\fR will dump every event as
+form is used, \fB\-stats\fR causes counters to be summed over the
+whole compilation unit while \fB\-details\fR dumps every event as
the passes generate them. The default with no option is to sum
counters for each function compiled.
.IP "\fB\-fdump\-tree\-\fR\fIswitch\fR" 4
.PD 0
.IP "\fB\-fdump\-tree\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR" 4
.IX Item "-fdump-tree-switch-options"
+.IP "\fB\-fdump\-tree\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR\fB=\fR\fIfilename\fR" 4
+.IX Item "-fdump-tree-switch-options=filename"
.PD
Control the dumping at various stages of processing the intermediate
language tree to a file. The file name is generated by appending a
-switch specific suffix to the source file name, and the file is
-created in the same directory as the output file. If the
-\&\fB\-\fR\fIoptions\fR form is used, \fIoptions\fR is a list of
-\&\fB\-\fR separated options which control the details of the dump. Not
-all options are applicable to all dumps; those that are not
-meaningful will be ignored. The following options are available
+switch-specific suffix to the source file name, and the file is
+created in the same directory as the output file. In case of
+\&\fB=\fR\fIfilename\fR option, the dump is output on the given file
+instead of the auto named dump files. If the \fB\-\fR\fIoptions\fR
+form is used, \fIoptions\fR is a list of \fB\-\fR separated options
+which control the details of the dump. Not all options are applicable
+to all dumps; those that are not meaningful are ignored. The
+following options are available
.RS 4
.IP "\fBaddress\fR" 4
.IX Item "address"
use working backward from mangled names in the assembly file.
.IP "\fBslim\fR" 4
.IX Item "slim"
-Inhibit dumping of members of a scope or body of a function merely
-because that scope has been reached. Only dump such items when they
-are directly reachable by some other path. When dumping pretty-printed
-trees, this option inhibits dumping the bodies of control structures.
+When dumping front-end intermediate representations, inhibit dumping
+of members of a scope or body of a function merely because that scope
+has been reached. Only dump such items when they are directly reachable
+by some other path.
+.Sp
+When dumping pretty-printed trees, this option inhibits dumping the
+bodies of control structures.
+.Sp
+When dumping \s-1RTL\s0, print the \s-1RTL\s0 in slim (condensed) form instead of
+the default LISP-like representation.
.IP "\fBraw\fR" 4
.IX Item "raw"
Print a raw representation of the tree. By default, trees are
pretty-printed into a C\-like representation.
.IP "\fBdetails\fR" 4
.IX Item "details"
-Enable more detailed dumps (not honored by every dump option).
+Enable more detailed dumps (not honored by every dump option). Also
+include information from the optimization passes.
.IP "\fBstats\fR" 4
.IX Item "stats"
Enable dumping various statistics about the pass (not honored by every dump
.IP "\fBblocks\fR" 4
.IX Item "blocks"
Enable showing basic block boundaries (disabled in raw dumps).
+.IP "\fBgraph\fR" 4
+.IX Item "graph"
+For each of the other indicated dump files (\fB\-fdump\-rtl\-\fR\fIpass\fR),
+dump a representation of the control flow graph suitable for viewing with
+GraphViz to \fI\fIfile\fI.\fIpassid\fI.\fIpass\fI.dot\fR. Each function in
+the file is pretty-printed as a subgraph, so that GraphViz can render them
+all in a single plot.
+.Sp
+This option currently only works for \s-1RTL\s0 dumps, and the \s-1RTL\s0 is always
+dumped in slim form.
.IP "\fBvops\fR" 4
.IX Item "vops"
Enable showing virtual operands for every statement.
.IP "\fBscev\fR" 4
.IX Item "scev"
Enable showing scalar evolution analysis details.
+.IP "\fBoptimized\fR" 4
+.IX Item "optimized"
+Enable showing optimization information (only available in certain
+passes).
+.IP "\fBmissed\fR" 4
+.IX Item "missed"
+Enable showing missed optimization information (only available in certain
+passes).
+.IP "\fBnotes\fR" 4
+.IX Item "notes"
+Enable other detailed optimization information (only available in
+certain passes).
+.IP "\fB=\fR\fIfilename\fR" 4
+.IX Item "=filename"
+Instead of an auto named dump file, output into the given file
+name. The file names \fIstdout\fR and \fIstderr\fR are treated
+specially and are considered already open standard streams. For
+example,
+.Sp
+.Vb 2
+\& gcc \-O2 \-ftree\-vectorize \-fdump\-tree\-vect\-blocks=foo.dump
+\& \-fdump\-tree\-pre=stderr file.c
+.Ve
+.Sp
+outputs vectorizer dump into \fIfoo.dump\fR, while the \s-1PRE\s0 dump is
+output on to \fIstderr\fR. If two conflicting dump filenames are
+given for the same pass, then the latter option overrides the earlier
+one.
.IP "\fBall\fR" 4
.IX Item "all"
Turn on all options, except \fBraw\fR, \fBslim\fR, \fBverbose\fR
and \fBlineno\fR.
+.IP "\fBoptall\fR" 4
+.IX Item "optall"
+Turn on all optimization options, i.e., \fBoptimized\fR,
+\&\fBmissed\fR, and \fBnote\fR.
.RE
.RS 4
.Sp
.IX Item "cfg"
Dump the control flow graph of each function to a file. The file name is
made by appending \fI.cfg\fR to the source file name.
-.IP "\fBvcg\fR" 4
-.IX Item "vcg"
-Dump the control flow graph of each function to a file in \s-1VCG\s0 format. The
-file name is made by appending \fI.vcg\fR to the source file name. Note
-that if the file contains more than one function, the generated file cannot
-be used directly by \s-1VCG\s0. You will need to cut and paste each function's
-graph into its own separate file first.
.IP "\fBch\fR" 4
.IX Item "ch"
Dump each function after copying loop headers. The file name is made by
.RE
.RS 4
.RE
+.IP "\fB\-fopt\-info\fR" 4
+.IX Item "-fopt-info"
+.PD 0
+.IP "\fB\-fopt\-info\-\fR\fIoptions\fR" 4
+.IX Item "-fopt-info-options"
+.IP "\fB\-fopt\-info\-\fR\fIoptions\fR\fB=\fR\fIfilename\fR" 4
+.IX Item "-fopt-info-options=filename"
+.PD
+Controls optimization dumps from various optimization passes. If the
+\&\fB\-\fR\fIoptions\fR form is used, \fIoptions\fR is a list of
+\&\fB\-\fR separated options to select the dump details and
+optimizations. If \fIoptions\fR is not specified, it defaults to
+\&\fBall\fR for details and \fBoptall\fR for optimization
+groups. If the \fIfilename\fR is not specified, it defaults to
+\&\fIstderr\fR. Note that the output \fIfilename\fR will be overwritten
+in case of multiple translation units. If a combined output from
+multiple translation units is desired, \fIstderr\fR should be used
+instead.
+.Sp
+The options can be divided into two groups, 1) options describing the
+verbosity of the dump, and 2) options describing which optimizations
+should be included. The options from both the groups can be freely
+mixed as they are non-overlapping. However, in case of any conflicts,
+the latter options override the earlier options on the command
+line. Though multiple \-fopt\-info options are accepted, only one of
+them can have \fB=filename\fR. If other filenames are provided then
+all but the first one are ignored.
+.Sp
+The dump verbosity has the following options
+.RS 4
+.IP "\fBoptimized\fR" 4
+.IX Item "optimized"
+Print information when an optimization is successfully applied. It is
+up to a pass to decide which information is relevant. For example, the
+vectorizer passes print the source location of loops which got
+successfully vectorized.
+.IP "\fBmissed\fR" 4
+.IX Item "missed"
+Print information about missed optimizations. Individual passes
+control which information to include in the output. For example,
+.Sp
+.Vb 1
+\& gcc \-O2 \-ftree\-vectorize \-fopt\-info\-vec\-missed
+.Ve
+.Sp
+will print information about missed optimization opportunities from
+vectorization passes on stderr.
+.IP "\fBnote\fR" 4
+.IX Item "note"
+Print verbose information about optimizations, such as certain
+transformations, more detailed messages about decisions etc.
+.IP "\fBall\fR" 4
+.IX Item "all"
+Print detailed optimization information. This includes
+\&\fIoptimized\fR, \fImissed\fR, and \fInote\fR.
+.RE
+.RS 4
+.Sp
+The second set of options describes a group of optimizations and may
+include one or more of the following.
+.IP "\fBipa\fR" 4
+.IX Item "ipa"
+Enable dumps from all interprocedural optimizations.
+.IP "\fBloop\fR" 4
+.IX Item "loop"
+Enable dumps from all loop optimizations.
+.IP "\fBinline\fR" 4
+.IX Item "inline"
+Enable dumps from all inlining optimizations.
+.IP "\fBvec\fR" 4
+.IX Item "vec"
+Enable dumps from all vectorization optimizations.
+.RE
+.RS 4
+.Sp
+For example,
+.Sp
+.Vb 1
+\& gcc \-O3 \-fopt\-info\-missed=missed.all
+.Ve
+.Sp
+outputs missed optimization report from all the passes into
+\&\fImissed.all\fR.
+.Sp
+As another example,
+.Sp
+.Vb 1
+\& gcc \-O3 \-fopt\-info\-inline\-optimized\-missed=inline.txt
+.Ve
+.Sp
+will output information about missed optimizations as well as
+optimized locations from all the inlining passes into
+\&\fIinline.txt\fR.
+.Sp
+If the \fIfilename\fR is provided, then the dumps from all the
+applicable optimizations are concatenated into the \fIfilename\fR.
+Otherwise the dump is output onto \fIstderr\fR. If \fIoptions\fR is
+omitted, it defaults to \fBall-optall\fR, which means dump all
+available optimization info from all the passes. In the following
+example, all optimization info is output on to \fIstderr\fR.
+.Sp
+.Vb 1
+\& gcc \-O3 \-fopt\-info
+.Ve
+.Sp
+Note that \fB\-fopt\-info\-vec\-missed\fR behaves the same as
+\&\fB\-fopt\-info\-missed\-vec\fR.
+.Sp
+As another example, consider
+.Sp
+.Vb 1
+\& gcc \-fopt\-info\-vec\-missed=vec.miss \-fopt\-info\-loop\-optimized=loop.opt
+.Ve
+.Sp
+Here the two output filenames \fIvec.miss\fR and \fIloop.opt\fR are
+in conflict since only one output file is allowed. In this case, only
+the first option takes effect and the subsequent options are
+ignored. Thus only the \fIvec.miss\fR is produced which cotaints
+dumps from the vectorizer about missed opportunities.
+.RE
.IP "\fB\-ftree\-vectorizer\-verbose=\fR\fIn\fR" 4
.IX Item "-ftree-vectorizer-verbose=n"
-This option controls the amount of debugging output the vectorizer prints.
-This information is written to standard error, unless
-\&\fB\-fdump\-tree\-all\fR or \fB\-fdump\-tree\-vect\fR is specified,
-in which case it is output to the usual dump listing file, \fI.vect\fR.
-For \fIn\fR=0 no diagnostic information is reported.
-If \fIn\fR=1 the vectorizer reports each loop that got vectorized,
-and the total number of loops that got vectorized.
-If \fIn\fR=2 the vectorizer also reports non-vectorized loops that passed
-the first analysis phase (vect_analyze_loop_form) \- i.e. countable,
-inner-most, single-bb, single\-entry/exit loops. This is the same verbosity
-level that \fB\-fdump\-tree\-vect\-stats\fR uses.
-Higher verbosity levels mean either more information dumped for each
-reported loop, or same amount of information reported for more loops:
-if \fIn\fR=3, vectorizer cost model information is reported.
-If \fIn\fR=4, alignment related information is added to the reports.
-If \fIn\fR=5, data-references related information (e.g. memory dependences,
-memory access-patterns) is added to the reports.
-If \fIn\fR=6, the vectorizer reports also non-vectorized inner-most loops
-that did not pass the first analysis phase (i.e., may not be countable, or
-may have complicated control-flow).
-If \fIn\fR=7, the vectorizer reports also non-vectorized nested loops.
-If \fIn\fR=8, \s-1SLP\s0 related information is added to the reports.
-For \fIn\fR=9, all the information the vectorizer generates during its
-analysis and transformation is reported. This is the same verbosity level
-that \fB\-fdump\-tree\-vect\-details\fR uses.
+This option is deprecated and is implemented in terms of
+\&\fB\-fopt\-info\fR. Please use \fB\-fopt\-info\-\fR\fIkind\fR form
+instead, where \fIkind\fR is one of the valid opt-info options. It
+prints additional optimization information. For \fIn\fR=0 no
+diagnostic information is reported. If \fIn\fR=1 the vectorizer
+reports each loop that got vectorized, and the total number of loops
+that got vectorized. If \fIn\fR=2 the vectorizer reports locations
+which could not be vectorized and the reasons for those. For any
+higher verbosity levels all the analysis and transformation
+information from the vectorizer is reported.
+.Sp
+Note that the information output by \fB\-ftree\-vectorizer\-verbose\fR
+option is sent to \fIstderr\fR. If the equivalent form
+\&\fB\-fopt\-info\-\fR\fIoptions\fR\fB=\fR\fIfilename\fR is used then the
+output is sent into \fIfilename\fR instead.
.IP "\fB\-frandom\-seed=\fR\fIstring\fR" 4
.IX Item "-frandom-seed=string"
-This option provides a seed that \s-1GCC\s0 uses when it would otherwise use
-random numbers. It is used to generate certain symbol names
+This option provides a seed that \s-1GCC\s0 uses in place of
+random numbers in generating certain symbol names
that have to be different in every compiled file. It is also used to
place unique stamps in coverage data files and the object files that
produce them. You can use the \fB\-frandom\-seed\fR option to produce
.PD
Store the usual \*(L"temporary\*(R" intermediate files permanently; place them
in the current directory and name them based on the source file. Thus,
-compiling \fIfoo.c\fR with \fB\-c \-save\-temps\fR would produce files
+compiling \fIfoo.c\fR with \fB\-c \-save\-temps\fR produces files
\&\fIfoo.i\fR and \fIfoo.s\fR, as well as \fIfoo.o\fR. This creates a
preprocessed \fIfoo.i\fR output file even though the compiler now
normally uses an integrated preprocessor.
\& gcc \-save\-temps=obj foobar.c \-o dir2/yfoobar
.Ve
.Sp
-would create \fIfoo.i\fR, \fIfoo.s\fR, \fIdir/xbar.i\fR,
+creates \fIfoo.i\fR, \fIfoo.s\fR, \fIdir/xbar.i\fR,
\&\fIdir/xbar.s\fR, \fIdir2/yfoobar.i\fR, \fIdir2/yfoobar.s\fR, and
\&\fIdir2/yfoobar.o\fR.
.IP "\fB\-time\fR[\fB=\fR\fIfile\fR]" 4
optimizing. Use of \fB\-gdwarf\-4\fR is recommended along with it.
.Sp
It can be enabled even if var-tracking is disabled, in which case
-annotations will be created and maintained, but discarded at the end.
+annotations are created and maintained, but discarded at the end.
.IP "\fB\-fvar\-tracking\-assignments\-toggle\fR" 4
.IX Item "-fvar-tracking-assignments-toggle"
Toggle \fB\-fvar\-tracking\-assignments\fR, in the same way that
that enable them. The directory name is separated from the switches by
\&\fB;\fR, and each switch starts with an \fB@\fR instead of the
\&\fB\-\fR, without spaces between multiple switches. This is supposed to
-ease shell-processing.
+ease shell processing.
.IP "\fB\-print\-multi\-os\-directory\fR" 4
.IX Item "-print-multi-os-directory"
Print the path to \s-1OS\s0 libraries for the selected
Same as \fB\-print\-file\-name=libgcc.a\fR.
.Sp
This is useful when you use \fB\-nostdlib\fR or \fB\-nodefaultlibs\fR
-but you do want to link with \fIlibgcc.a\fR. You can do
+but you do want to link with \fIlibgcc.a\fR. You can do:
.Sp
.Vb 1
\& gcc \-nostdlib <files>... \`gcc \-print\-libgcc\-file\-name\`
.IP "\fB\-print\-search\-dirs\fR" 4
.IX Item "-print-search-dirs"
Print the name of the configured installation directory and a list of
-program and library directories \fBgcc\fR will search\-\-\-and don't do anything else.
+program and library directories \fBgcc\fR searches\-\-\-and don't do anything else.
.Sp
This is useful when \fBgcc\fR prints the error message
\&\fBinstallation problem, cannot exec cpp0: No such file or directory\fR.
Don't forget the trailing \fB/\fR.
.IP "\fB\-print\-sysroot\fR" 4
.IX Item "-print-sysroot"
-Print the target sysroot directory that will be used during
+Print the target sysroot directory that is used during
compilation. This is the target sysroot specified either at configure
time or using the \fB\-\-sysroot\fR option, possibly with an extra
suffix that depends on compilation options. If no target sysroot is
.IX Item "-dumpspecs"
Print the compiler's built-in specs\-\-\-and don't do anything else. (This
is used when \s-1GCC\s0 itself is being built.)
-.IP "\fB\-feliminate\-unused\-debug\-types\fR" 4
-.IX Item "-feliminate-unused-debug-types"
-Normally, when producing \s-1DWARF2\s0 output, \s-1GCC\s0 will emit debugging
+.IP "\fB\-fno\-eliminate\-unused\-debug\-types\fR" 4
+.IX Item "-fno-eliminate-unused-debug-types"
+Normally, when producing \s-1DWARF\s0 2 output, \s-1GCC\s0 avoids producing debug symbol
+output for types that are nowhere used in the source file being compiled.
+Sometimes it is useful to have \s-1GCC\s0 emit debugging
information for all types declared in a compilation
unit, regardless of whether or not they are actually used
-in that compilation unit. Sometimes this is useful, such as
+in that compilation unit, for example
if, in the debugger, you want to cast a value to a type that is
not actually used in your program (but is declared). More often,
however, this results in a significant amount of wasted space.
-With this option, \s-1GCC\s0 will avoid producing debug symbol output
-for types that are nowhere used in the source file being compiled.
-.Sh "Options That Control Optimization"
+.SS "Options That Control Optimization"
.IX Subsection "Options That Control Optimization"
These options control various sorts of optimizations.
.PP
results. Statements are independent: if you stop the program with a
breakpoint between statements, you can then assign a new value to any
variable or change the program counter to any other statement in the
-function and get exactly the results you would expect from the source
+function and get exactly the results you expect from the source
code.
.PP
Turning on optimization flags makes the compiler attempt to improve
\&\-ftree\-forwprop
\&\-ftree\-fre
\&\-ftree\-phiprop
+\&\-ftree\-slsr
\&\-ftree\-sra
\&\-ftree\-pta
\&\-ftree\-ter
\&\-fdevirtualize
\&\-fexpensive\-optimizations
\&\-fgcse \-fgcse\-lm
+\&\-fhoist\-adjacent\-loads
\&\-finline\-small\-functions
\&\-findirect\-inlining
\&\-fipa\-sra
Optimize yet more. \fB\-O3\fR turns on all optimizations specified
by \fB\-O2\fR and also turns on the \fB\-finline\-functions\fR,
\&\fB\-funswitch\-loops\fR, \fB\-fpredictive\-commoning\fR,
-\&\fB\-fgcse\-after\-reload\fR, \fB\-ftree\-vectorize\fR and
-\&\fB\-fipa\-cp\-clone\fR options.
+\&\fB\-fgcse\-after\-reload\fR, \fB\-ftree\-vectorize\fR,
+\&\fB\-fvect\-cost\-model\fR,
+\&\fB\-ftree\-partial\-pre\fR and \fB\-fipa\-cp\-clone\fR options.
.IP "\fB\-O0\fR" 4
.IX Item "-O0"
Reduce compilation time and make debugging produce the expected
.IX Item "-Ofast"
Disregard strict standards compliance. \fB\-Ofast\fR enables all
\&\fB\-O3\fR optimizations. It also enables optimizations that are not
-valid for all standard compliant programs.
+valid for all standard-compliant programs.
It turns on \fB\-ffast\-math\fR and the Fortran-specific
\&\fB\-fno\-protect\-parens\fR and \fB\-fstack\-arrays\fR.
+.IP "\fB\-Og\fR" 4
+.IX Item "-Og"
+Optimize debugging experience. \fB\-Og\fR enables optimizations
+that do not interfere with debugging. It should be the optimization
+level of choice for the standard edit-compile-debug cycle, offering
+a reasonable level of optimization while maintaining fast compilation
+and a good debugging experience.
.Sp
If you use multiple \fB\-O\fR options, with or without level numbers,
the last such option is the one that is effective.
.PP
Options of the form \fB\-f\fR\fIflag\fR specify machine-independent
flags. Most flags have both positive and negative forms; the negative
-form of \fB\-ffoo\fR would be \fB\-fno\-foo\fR. In the table
-below, only one of the forms is listed\-\-\-the one you typically will
+form of \fB\-ffoo\fR is \fB\-fno\-foo\fR. In the table
+below, only one of the forms is listed\-\-\-the one you typically
use. You can figure out the other form by either removing \fBno\-\fR
or adding it.
.PP
whether a target machine supports this flag.
.Sp
Starting with \s-1GCC\s0 version 4.6, the default setting (when not optimizing for
-size) for 32\-bit Linux x86 and 32\-bit Darwin x86 targets has been changed to
+size) for 32\-bit GNU/Linux x86 and 32\-bit Darwin x86 targets has been changed to
\&\fB\-fomit\-frame\-pointer\fR. The default can be reverted to
\&\fB\-fno\-omit\-frame\-pointer\fR by configuring \s-1GCC\s0 with the
\&\fB\-\-enable\-frame\-pointer\fR configure option.
on, even if the variables aren't referenced.
.Sp
\&\s-1GCC\s0 enables this option by default. If you want to force the compiler to
-check if the variable was referenced, regardless of whether or not
+check if a variable is referenced, regardless of whether or not
optimization is turned on, use the \fB\-fno\-keep\-static\-consts\fR option.
.IP "\fB\-fmerge\-constants\fR" 4
.IX Item "-fmerge-constants"
arrays or initialized constant variables with integral or floating-point
types. Languages like C or \*(C+ require each variable, including multiple
instances of the same variable in recursive calls, to have distinct locations,
-so using this option will result in non-conforming
+so using this option results in non-conforming
behavior.
.IP "\fB\-fmodulo\-sched\fR" 4
.IX Item "-fmodulo-sched"
instructions by overlapping different iterations.
.IP "\fB\-fmodulo\-sched\-allow\-regmoves\fR" 4
.IX Item "-fmodulo-sched-allow-regmoves"
-Perform more aggressive \s-1SMS\s0 based modulo scheduling with register moves
-allowed. By setting this flag certain anti-dependences edges will be
-deleted which will trigger the generation of reg-moves based on the
+Perform more aggressive SMS-based modulo scheduling with register moves
+allowed. By setting this flag certain anti-dependences edges are
+deleted, which triggers the generation of reg-moves based on the
life-range analysis. This option is effective only with
\&\fB\-fmodulo\-sched\fR enabled.
.IP "\fB\-fno\-branch\-count\-reg\fR" 4
code.
.Sp
This option turns off this behavior because some programs explicitly
-rely on variables going to the data section. E.g., so that the
+rely on variables going to the data section\-\-\-e.g., so that the
resulting executable can find the beginning of that section and/or make
assumptions based on that.
.Sp
range/validity tests. Modules so instrumented should be immune to
buffer overflows, invalid heap use, and some other classes of C/\*(C+
programming errors. The instrumentation relies on a separate runtime
-library (\fIlibmudflap\fR), which will be linked into a program if
+library (\fIlibmudflap\fR), which is linked into a program if
\&\fB\-fmudflap\fR is given at link time. Run-time behavior of the
instrumented program is controlled by the \fB\s-1MUDFLAP_OPTIONS\s0\fR
environment variable. See \f(CW\*(C`env MUDFLAP_OPTIONS=\-help a.out\*(C'\fR
erroneously read data to propagate within a program.
.IP "\fB\-fthread\-jumps\fR" 4
.IX Item "-fthread-jumps"
-Perform optimizations where we check to see if a jump branches to a
+Perform optimizations that check to see if a jump branches to a
location where another comparison subsumed by the first is found. If
so, the first branch is redirected to either the destination of the
second branch or a point immediately following it, depending on whether
In common subexpression elimination (\s-1CSE\s0), scan through jump instructions
when the target of the jump is not reached by any other path. For
example, when \s-1CSE\s0 encounters an \f(CW\*(C`if\*(C'\fR statement with an
-\&\f(CW\*(C`else\*(C'\fR clause, \s-1CSE\s0 will follow the jump when the condition
+\&\f(CW\*(C`else\*(C'\fR clause, \s-1CSE\s0 follows the jump when the condition
tested is false.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.IP "\fB\-frerun\-cse\-after\-loop\fR" 4
.IX Item "-frerun-cse-after-loop"
-Re-run common subexpression elimination after loop optimizations has been
+Re-run common subexpression elimination after loop optimizations are
performed.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.IP "\fB\-fgcse\-lm\fR" 4
.IX Item "-fgcse-lm"
-When \fB\-fgcse\-lm\fR is enabled, global common subexpression elimination will
-attempt to move loads that are only killed by stores into themselves. This
+When \fB\-fgcse\-lm\fR is enabled, global common subexpression elimination
+attempts to move loads that are only killed by stores into themselves. This
allows a loop containing a load/store sequence to be changed to a load outside
the loop, and a copy/store within the loop.
.Sp
-Enabled by default when gcse is enabled.
+Enabled by default when \fB\-fgcse\fR is enabled.
.IP "\fB\-fgcse\-sm\fR" 4
.IX Item "-fgcse-sm"
When \fB\-fgcse\-sm\fR is enabled, a store motion pass is run after
-global common subexpression elimination. This pass will attempt to move
+global common subexpression elimination. This pass attempts to move
stores out of loops. When used in conjunction with \fB\-fgcse\-lm\fR,
loops containing a load/store sequence can be changed to a load before
the loop and a store after the loop.
.IP "\fB\-fgcse\-after\-reload\fR" 4
.IX Item "-fgcse-after-reload"
When \fB\-fgcse\-after\-reload\fR is enabled, a redundant load elimination
-pass is performed after reload. The purpose of this pass is to cleanup
+pass is performed after reload. The purpose of this pass is to clean up
redundant spilling.
+.IP "\fB\-faggressive\-loop\-optimizations\fR" 4
+.IX Item "-faggressive-loop-optimizations"
+This option tells the loop optimizer to use language constraints to
+derive bounds for the number of iterations of a loop. This assumes that
+loop code does not invoke undefined behavior by for example causing signed
+integer overflows or out-of-bound array accesses. The bounds for the
+number of iterations of a loop are used to guide loop unrolling and peeling
+and loop exit test optimizations.
+This option is enabled by default.
.IP "\fB\-funsafe\-loop\-optimizations\fR" 4
.IX Item "-funsafe-loop-optimizations"
-If given, the loop optimizer will assume that loop indices do not
-overflow, and that the loops with nontrivial exit condition are not
+This option tells the loop optimizer to assume that loop indices do not
+overflow, and that loops with nontrivial exit condition are not
infinite. This enables a wider range of loop optimizations even if
the loop optimizer itself cannot prove that these assumptions are valid.
-Using \fB\-Wunsafe\-loop\-optimizations\fR, the compiler will warn you
+If you use \fB\-Wunsafe\-loop\-optimizations\fR, the compiler warns you
if it finds this kind of loop.
.IP "\fB\-fcrossjumping\fR" 4
.IX Item "-fcrossjumping"
-Perform cross-jumping transformation. This transformation unifies equivalent code and save code size. The
+Perform cross-jumping transformation.
+This transformation unifies equivalent code and saves code size. The
resulting code may or may not perform better than without cross-jumping.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.IP "\fB\-fif\-conversion\fR" 4
.IX Item "-fif-conversion"
Attempt to transform conditional jumps into branch-less equivalents. This
-include use of conditional moves, min, max, set flags and abs instructions, and
+includes use of conditional moves, min, max, set flags and abs instructions, and
some tricks doable by standard arithmetics. The use of conditional execution
on chips where it is available is controlled by \f(CW\*(C`if\-conversion2\*(C'\fR.
.Sp
.IP "\fB\-free\fR" 4
.IX Item "-free"
Attempt to remove redundant extension instructions. This is especially
-helpful for the x86\-64 architecture which implicitly zero-extends in 64\-bit
+helpful for the x86\-64 architecture, which implicitly zero-extends in 64\-bit
registers after writing to their lower 32\-bit half.
.Sp
Enabled for x86 at levels \fB\-O2\fR, \fB\-O3\fR.
.RE
.RS 4
.RE
+.IP "\fB\-fira\-hoist\-pressure\fR" 4
+.IX Item "-fira-hoist-pressure"
+Use \s-1IRA\s0 to evaluate register pressure in the code hoisting pass for
+decisions to hoist expressions. This option usually results in smaller
+code, but it can slow the compiler down.
+.Sp
+This option is enabled at level \fB\-Os\fR for all targets.
.IP "\fB\-fira\-loop\-pressure\fR" 4
.IX Item "-fira-loop-pressure"
Use \s-1IRA\s0 to evaluate register pressure in loops for decisions to move
with \fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher.
.IP "\fB\-fsched\-pressure\fR" 4
.IX Item "-fsched-pressure"
-Enable register pressure sensitive insn scheduling before the register
+Enable register pressure sensitive insn scheduling before register
allocation. This only makes sense when scheduling before register
allocation is enabled, i.e. with \fB\-fschedule\-insns\fR or at
\&\fB\-O2\fR or higher. Usage of this option can improve the
generated code and decrease its size by preventing register pressure
-increase above the number of available hard registers and as a
-consequence register spills in the register allocation.
+increase above the number of available hard registers and subsequent
+spills in register allocation.
.IP "\fB\-fsched\-spec\-load\fR" 4
.IX Item "-fsched-spec-load"
Allow speculative motion of some load instructions. This only makes
.IX Item "-fsched-stalled-insns=n"
.PD
Define how many insns (if any) can be moved prematurely from the queue
-of stalled insns into the ready list, during the second scheduling pass.
-\&\fB\-fno\-sched\-stalled\-insns\fR means that no insns will be moved
+of stalled insns into the ready list during the second scheduling pass.
+\&\fB\-fno\-sched\-stalled\-insns\fR means that no insns are moved
prematurely, \fB\-fsched\-stalled\-insns=0\fR means there is no limit
on how many queued insns can be moved prematurely.
\&\fB\-fsched\-stalled\-insns\fR without a value is equivalent to
.IP "\fB\-fsched\-stalled\-insns\-dep=\fR\fIn\fR" 4
.IX Item "-fsched-stalled-insns-dep=n"
.PD
-Define how many insn groups (cycles) will be examined for a dependency
-on a stalled insn that is candidate for premature removal from the queue
+Define how many insn groups (cycles) are examined for a dependency
+on a stalled insn that is a candidate for premature removal from the queue
of stalled insns. This has an effect only during the second scheduling pass,
and only if \fB\-fsched\-stalled\-insns\fR is used.
\&\fB\-fno\-sched\-stalled\-insns\-dep\fR is equivalent to
\&\fB\-fsched\-stalled\-insns\-dep=1\fR.
.IP "\fB\-fsched2\-use\-superblocks\fR" 4
.IX Item "-fsched2-use-superblocks"
-When scheduling after register allocation, do use superblock scheduling
-algorithm. Superblock scheduling allows motion across basic block boundaries
-resulting on faster schedules. This option is experimental, as not all machine
+When scheduling after register allocation, use superblock scheduling.
+This allows motion across basic block boundaries,
+resulting in faster schedules. This option is experimental, as not all machine
descriptions used by \s-1GCC\s0 model the \s-1CPU\s0 closely enough to avoid unreliable
results from the algorithm.
.Sp
at \fB\-O2\fR or higher.
.IP "\fB\-freschedule\-modulo\-scheduled\-loops\fR" 4
.IX Item "-freschedule-modulo-scheduled-loops"
-The modulo scheduling comes before the traditional scheduling, if a loop
-was modulo scheduled we may want to prevent the later scheduling passes
-from changing its schedule, we use this option to control that.
+Modulo scheduling is performed before traditional scheduling. If a loop
+is modulo scheduled, later scheduling passes may change its schedule.
+Use this option to control that behavior.
.IP "\fB\-fselective\-scheduling\fR" 4
.IX Item "-fselective-scheduling"
Schedule instructions using selective scheduling algorithm. Selective
.IP "\fB\-fsel\-sched\-pipelining\fR" 4
.IX Item "-fsel-sched-pipelining"
Enable software pipelining of innermost loops during selective scheduling.
-This option has no effect until one of \fB\-fselective\-scheduling\fR or
+This option has no effect unless one of \fB\-fselective\-scheduling\fR or
\&\fB\-fselective\-scheduling2\fR is turned on.
.IP "\fB\-fsel\-sched\-pipelining\-outer\-loops\fR" 4
.IX Item "-fsel-sched-pipelining-outer-loops"
When pipelining loops during selective scheduling, also pipeline outer loops.
-This option has no effect until \fB\-fsel\-sched\-pipelining\fR is turned on.
+This option has no effect unless \fB\-fsel\-sched\-pipelining\fR is turned on.
.IP "\fB\-fshrink\-wrap\fR" 4
.IX Item "-fshrink-wrap"
Emit function prologues only before parts of the function that need it,
\&\fB\-O\fR and higher.
.IP "\fB\-fcaller\-saves\fR" 4
.IX Item "-fcaller-saves"
-Enable values to be allocated in registers that will be clobbered by
+Enable allocation of values to registers that are clobbered by
function calls, by emitting extra instructions to save and restore the
registers around such calls. Such allocation is done only when it
-seems to result in better code than would otherwise be produced.
+seems to result in better code.
.Sp
This option is always enabled by default on certain machines, usually
those which have no call-preserved registers to use instead.
Enabled by default at \fB\-O1\fR and higher.
.IP "\fB\-fconserve\-stack\fR" 4
.IX Item "-fconserve-stack"
-Attempt to minimize stack usage. The compiler will attempt to use less
+Attempt to minimize stack usage. The compiler attempts to use less
stack space, even if that makes the program slower. This option
implies setting the \fBlarge-stack-frame\fR parameter to 100
and the \fBlarge-stack-frame-growth\fR parameter to 400.
.IX Item "-ftree-pre"
Perform partial redundancy elimination (\s-1PRE\s0) on trees. This flag is
enabled by default at \fB\-O2\fR and \fB\-O3\fR.
+.IP "\fB\-ftree\-partial\-pre\fR" 4
+.IX Item "-ftree-partial-pre"
+Make partial redundancy elimination (\s-1PRE\s0) more aggressive. This flag is
+enabled by default at \fB\-O3\fR.
.IP "\fB\-ftree\-forwprop\fR" 4
.IX Item "-ftree-forwprop"
Perform forward propagation on trees. This flag is enabled by default
.IX Item "-ftree-phiprop"
Perform hoisting of loads from conditional pointers on trees. This
pass is enabled by default at \fB\-O\fR and higher.
+.IP "\fB\-fhoist\-adjacent\-loads\fR" 4
+.IX Item "-fhoist-adjacent-loads"
+Speculatively hoist loads from both branches of an if-then-else if the
+loads are from adjacent locations in the same structure and the target
+architecture has a conditional move instruction. This flag is enabled
+by default at \fB\-O2\fR and higher.
.IP "\fB\-ftree\-copy\-prop\fR" 4
.IX Item "-ftree-copy-prop"
Perform copy propagation on trees. This pass eliminates unnecessary
Enabled by default at \fB\-O\fR and higher.
.IP "\fB\-fipa\-reference\fR" 4
.IX Item "-fipa-reference"
-Discover which static variables do not escape cannot escape the
+Discover which static variables do not escape the
compilation unit.
Enabled by default at \fB\-O\fR and higher.
.IP "\fB\-fipa\-pta\fR" 4
.IP "\fB\-fipa\-cp\-clone\fR" 4
.IX Item "-fipa-cp-clone"
Perform function cloning to make interprocedural constant propagation stronger.
-When enabled, interprocedural constant propagation will perform function cloning
+When enabled, interprocedural constant propagation performs function cloning
when externally visible function can be called with constant arguments.
Because this optimization can create multiple copies of functions,
it may significantly increase code size
(see \fB\-\-param ipcp\-unit\-growth=\fR\fIvalue\fR).
This flag is enabled by default at \fB\-O3\fR.
-.IP "\fB\-fipa\-matrix\-reorg\fR" 4
-.IX Item "-fipa-matrix-reorg"
-Perform matrix flattening and transposing.
-Matrix flattening tries to replace an m\-dimensional matrix
-with its equivalent n\-dimensional matrix, where n < m.
-This reduces the level of indirection needed for accessing the elements
-of the matrix. The second optimization is matrix transposing, which
-attempts to change the order of the matrix's dimensions in order to
-improve cache locality.
-Both optimizations need the \fB\-fwhole\-program\fR flag.
-Transposing is enabled only if profiling information is available.
.IP "\fB\-ftree\-sink\fR" 4
.IX Item "-ftree-sink"
Perform forward store motion on trees. This flag is
default at \fB\-O\fR and higher.
.IP "\fB\-ftree\-builtin\-call\-dce\fR" 4
.IX Item "-ftree-builtin-call-dce"
-Perform conditional dead code elimination (\s-1DCE\s0) for calls to builtin functions
+Perform conditional dead code elimination (\s-1DCE\s0) for calls to built-in functions
that may set \f(CW\*(C`errno\*(C'\fR but are otherwise side-effect free. This flag is
enabled by default at \fB\-O2\fR and higher if \fB\-Os\fR is not also
specified.
\& ENDDO
.Ve
.Sp
-loop interchange will transform the loop as if the user had written:
+loop interchange transforms the loop as if it were written:
.Sp
.Vb 5
\& DO I = 1, N
\& ENDDO
.Ve
.Sp
-loop strip mining will transform the loop as if the user had written:
+loop strip mining transforms the loop as if it were written:
.Sp
.Vb 5
\& DO II = 1, N, 51
\& ENDDO
.Ve
.Sp
-loop blocking will transform the loop as if the user had written:
+loop blocking transforms the loop as if it were written:
.Sp
.Vb 9
\& DO II = 1, N, 51
.Ve
.Sp
which can be beneficial when \f(CW\*(C`M\*(C'\fR is larger than the caches,
-because the innermost loop will iterate over a smaller amount of data
+because the innermost loop iterates over a smaller amount of data
which can be kept in the caches. This optimization applies to all the
languages supported by \s-1GCC\s0 and is not limited to Fortran. To use this
code transformation, \s-1GCC\s0 has to be configured with \fB\-\-with\-ppl\fR
\&\s-1GIMPLE\s0 \-> \s-1GRAPHITE\s0 \-> \s-1GIMPLE\s0 transformation. Some minimal optimizations
are also performed by the code generator CLooG, like index splitting and
dead code elimination in loops.
-.IP "\fB\-floop\-flatten\fR" 4
-.IX Item "-floop-flatten"
-Removes the loop nesting structure: transforms the loop nest into a
-single loop. This transformation can be useful as an enablement
-transform for vectorization and parallelization. This feature
+.IP "\fB\-floop\-nest\-optimize\fR" 4
+.IX Item "-floop-nest-optimize"
+Enable the \s-1ISL\s0 based loop nest optimizer. This is a generic loop nest
+optimizer based on the Pluto optimization algorithms. It calculates a loop
+structure optimized for data-locality and parallelism. This option
is experimental.
-To use this code transformation, \s-1GCC\s0 has to be configured
-with \fB\-\-with\-ppl\fR and \fB\-\-with\-cloog\fR to enable the
-Graphite loop transformation infrastructure.
.IP "\fB\-floop\-parallelize\-all\fR" 4
.IX Item "-floop-parallelize-all"
Use the Graphite data dependence analysis to identify loops that can
\& A[i] = expr;
.Ve
.Sp
-would be transformed to
+is transformed to
.Sp
.Vb 2
\& for (i = 0; i < N; i++)
.IP "\fB\-ftree\-loop\-im\fR" 4
.IX Item "-ftree-loop-im"
Perform loop invariant motion on trees. This pass moves only invariants that
-would be hard to handle at \s-1RTL\s0 level (function calls, operations that expand to
+are hard to handle at \s-1RTL\s0 level (function calls, operations that expand to
nontrivial sequences of insns). With \fB\-funswitch\-loops\fR it also moves
operands of conditions that are invariant out of the loop, so that we can use
just trivial invariantness analysis in loop unswitching. The pass also includes
temporaries to other variables at copy locations, usually resulting in
variable names which more closely resemble the original variables. This flag
is enabled by default at \fB\-O\fR and higher.
+.IP "\fB\-ftree\-coalesce\-inlined\-vars\fR" 4
+.IX Item "-ftree-coalesce-inlined-vars"
+Tell the copyrename pass (see \fB\-ftree\-copyrename\fR) to attempt to
+combine small user-defined variables too, but only if they were inlined
+from other functions. It is a more limited form of
+\&\fB\-ftree\-coalesce\-vars\fR. This may harm debug information of such
+inlined variables, but it will keep variables of the inlined-into
+function apart from each other, such that they are more likely to
+contain the expected values in a debugging session. This was the
+default in \s-1GCC\s0 versions older than 4.7.
+.IP "\fB\-ftree\-coalesce\-vars\fR" 4
+.IX Item "-ftree-coalesce-vars"
+Tell the copyrename pass (see \fB\-ftree\-copyrename\fR) to attempt to
+combine small user-defined variables too, instead of just compiler
+temporaries. This may severely limit the ability to debug an optimized
+program compiled with \fB\-fno\-var\-tracking\-assignments\fR. In the
+negated form, this flag prevents \s-1SSA\s0 coalescing of user variables,
+including inlined ones. This option is enabled by default.
.IP "\fB\-ftree\-ter\fR" 4
.IX Item "-ftree-ter"
Perform temporary expression replacement during the \s-1SSA\-\s0>normal phase. Single
defining expression. This results in non-GIMPLE code, but gives the expanders
much more complex trees to work on resulting in better \s-1RTL\s0 generation. This is
enabled by default at \fB\-O\fR and higher.
+.IP "\fB\-ftree\-slsr\fR" 4
+.IX Item "-ftree-slsr"
+Perform straight-line strength reduction on trees. This recognizes related
+expressions involving multiplications and replaces them by less expensive
+calculations when possible. This is enabled by default at \fB\-O\fR and
+higher.
.IP "\fB\-ftree\-vectorize\fR" 4
.IX Item "-ftree-vectorize"
Perform loop vectorization on trees. This flag is enabled by default at
except at level \fB\-Os\fR where it is disabled.
.IP "\fB\-fvect\-cost\-model\fR" 4
.IX Item "-fvect-cost-model"
-Enable cost model for vectorization.
+Enable cost model for vectorization. This option is enabled by default at
+\&\fB\-O3\fR.
.IP "\fB\-ftree\-vrp\fR" 4
.IX Item "-ftree-vrp"
Perform Value Range Propagation on trees. This is similar to the
.IX Item "-ftracer"
Perform tail duplication to enlarge superblock size. This transformation
simplifies the control flow of the function allowing other optimizations to do
-better job.
+a better job.
.IP "\fB\-funroll\-loops\fR" 4
.IX Item "-funroll-loops"
Unroll loops whose number of iterations can be determined at compile
\&\fB\-funroll\-loops\fR,
.IP "\fB\-fsplit\-ivs\-in\-unroller\fR" 4
.IX Item "-fsplit-ivs-in-unroller"
-Enables expressing of values of induction variables in later iterations
+Enables expression of values of induction variables in later iterations
of the unrolled loop using the value in the first iteration. This breaks
long dependency chains, thus improving efficiency of the scheduling passes.
.Sp
-Combination of \fB\-fweb\fR and \s-1CSE\s0 is often sufficient to obtain the
-same effect. However in cases the loop body is more complicated than
-a single basic block, this is not reliable. It also does not work at all
-on some of the architectures due to restrictions in the \s-1CSE\s0 pass.
+A combination of \fB\-fweb\fR and \s-1CSE\s0 is often sufficient to obtain the
+same effect. However, that is not reliable in cases where the loop body
+is more complicated than a single basic block. It also does not work at all
+on some architectures due to restrictions in the \s-1CSE\s0 pass.
.Sp
This optimization is enabled by default.
.IP "\fB\-fvariable\-expansion\-in\-unroller\fR" 4
.IX Item "-fvariable-expansion-in-unroller"
-With this option, the compiler will create multiple copies of some
-local variables when unrolling a loop which can result in superior code.
+With this option, the compiler creates multiple copies of some
+local variables when unrolling a loop, which can result in superior code.
.IP "\fB\-fpartial\-inlining\fR" 4
.IX Item "-fpartial-inlining"
Inline parts of functions. This option has any effect only
.IX Item "-fno-guess-branch-probability"
Do not guess branch probabilities using heuristics.
.Sp
-\&\s-1GCC\s0 will use heuristics to guess branch probabilities if they are
+\&\s-1GCC\s0 uses heuristics to guess branch probabilities if they are
not provided by profiling feedback (\fB\-fprofile\-arcs\fR). These
heuristics are based on the control flow graph. If some branch probabilities
-are specified by \fB_\|_builtin_expect\fR, then the heuristics will be
+are specified by \fB_\|_builtin_expect\fR, then the heuristics are
used to guess branch probabilities for the rest of the control flow graph,
taking the \fB_\|_builtin_expect\fR info into account. The interactions
between the heuristics and \fB_\|_builtin_expect\fR can be complex, and in
the linker so object file format must support named sections and linker must
place them in a reasonable way.
.Sp
-Also profile feedback must be available in to make this option effective. See
+Also profile feedback must be available to make this option effective. See
\&\fB\-fprofile\-arcs\fR for details.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
The practice of reading from a different union member than the one most
recently written to (called \*(L"type-punning\*(R") is common. Even with
\&\fB\-fstrict\-aliasing\fR, type-punning is allowed, provided the memory
-is accessed through the union type. So, the code above will work as
+is accessed through the union type. So, the code above works as
expected. However, this code might not:
.Sp
.Vb 7
Allow the compiler to assume strict signed overflow rules, depending
on the language being compiled. For C (and \*(C+) this means that
overflow when doing arithmetic with signed numbers is undefined, which
-means that the compiler may assume that it will not happen. This
-permits various optimizations. For example, the compiler will assume
-that an expression like \f(CW\*(C`i + 10 > i\*(C'\fR will always be true for
+means that the compiler may assume that it does not happen. This
+permits various optimizations. For example, the compiler assumes
+that an expression like \f(CW\*(C`i + 10 > i\*(C'\fR is always true for
signed \f(CW\*(C`i\*(C'\fR. This assumption is only valid if signed overflow is
undefined, as the expression is false if \f(CW\*(C`i + 10\*(C'\fR overflows when
using twos complement arithmetic. When this option is in effect any
-attempt to determine whether an operation on signed numbers will
-overflow must be written carefully to not actually involve overflow.
+attempt to determine whether an operation on signed numbers
+overflows must be written carefully to not actually involve overflow.
.Sp
This option also allows the compiler to assume strict pointer
semantics: given a pointer to an object, if adding an offset to that
Align the start of functions to the next power-of-two greater than
\&\fIn\fR, skipping up to \fIn\fR bytes. For instance,
\&\fB\-falign\-functions=32\fR aligns functions to the next 32\-byte
-boundary, but \fB\-falign\-functions=24\fR would align to the next
+boundary, but \fB\-falign\-functions=24\fR aligns to the next
32\-byte boundary only if this can be done by skipping 23 bytes or less.
.Sp
\&\fB\-fno\-align\-functions\fR and \fB\-falign\-functions=1\fR are
-equivalent and mean that functions will not be aligned.
+equivalent and mean that functions are not aligned.
.Sp
Some assemblers only support this flag when \fIn\fR is a power of two;
in that case, it is rounded up.
branch target is reached in the usual flow of the code.
.Sp
\&\fB\-fno\-align\-labels\fR and \fB\-falign\-labels=1\fR are
-equivalent and mean that labels will not be aligned.
+equivalent and mean that labels are not aligned.
.Sp
If \fB\-falign\-loops\fR or \fB\-falign\-jumps\fR are applicable and
are greater than this value, then their values are used instead.
.IX Item "-falign-loops=n"
.PD
Align loops to a power-of-two boundary, skipping up to \fIn\fR bytes
-like \fB\-falign\-functions\fR. The hope is that the loop will be
-executed many times, which will make up for any execution of the dummy
+like \fB\-falign\-functions\fR. If the loops are
+executed many times, this makes up for any execution of the dummy
operations.
.Sp
\&\fB\-fno\-align\-loops\fR and \fB\-falign\-loops=1\fR are
-equivalent and mean that loops will not be aligned.
+equivalent and mean that loops are not aligned.
.Sp
If \fIn\fR is not specified or is zero, use a machine-dependent default.
.Sp
need be executed.
.Sp
\&\fB\-fno\-align\-jumps\fR and \fB\-falign\-jumps=1\fR are
-equivalent and mean that loops will not be aligned.
+equivalent and mean that loops are not aligned.
.Sp
If \fIn\fR is not specified or is zero, use a machine-dependent default.
.Sp
Do not reorder top-level functions, variables, and \f(CW\*(C`asm\*(C'\fR
statements. Output them in the same order that they appear in the
input file. When this option is used, unreferenced static variables
-will not be removed. This option is intended to support existing code
+are not removed. This option is intended to support existing code
that relies on a particular ordering. For new code, it is better to
use attributes.
.Sp
each web individual pseudo register. This allows the register allocation pass
to operate on pseudos directly, but also strengthens several other optimization
passes, such as \s-1CSE\s0, loop optimizer and trivial dead code remover. It can,
-however, make debugging impossible, since variables will no longer stay in a
+however, make debugging impossible, since variables no longer stay in a
\&\*(L"home register\*(R".
.Sp
Enabled by default with \fB\-funroll\-loops\fR.
Assume that the current compilation unit represents the whole program being
compiled. All public functions and variables with the exception of \f(CW\*(C`main\*(C'\fR
and those merged by attribute \f(CW\*(C`externally_visible\*(C'\fR become static functions
-and in effect are optimized more aggressively by interprocedural optimizers. If \fBgold\fR is used as the linker plugin, \f(CW\*(C`externally_visible\*(C'\fR attributes are automatically added to functions (not variable yet due to a current \fBgold\fR issue) that are accessed outside of \s-1LTO\s0 objects according to resolution file produced by \fBgold\fR. For other linkers that cannot generate resolution file, explicit \f(CW\*(C`externally_visible\*(C'\fR attributes are still necessary.
-While this option is equivalent to proper use of the \f(CW\*(C`static\*(C'\fR keyword for
-programs consisting of a single file, in combination with option
-\&\fB\-flto\fR this flag can be used to
-compile many smaller scale programs since the functions and variables become
-local for the whole combined compilation unit, not for the single source file
-itself.
-.Sp
-This option implies \fB\-fwhole\-file\fR for Fortran programs.
+and in effect are optimized more aggressively by interprocedural optimizers.
+.Sp
+This option should not be used in combination with \f(CW\*(C`\-flto\*(C'\fR.
+Instead relying on a linker plugin should provide safer and more precise
+information.
.IP "\fB\-flto[=\fR\fIn\fR\fB]\fR" 4
.IX Item "-flto[=n]"
This option runs the standard link-time optimizer. When invoked
for this to work. This option likely only works if \fB\s-1MAKE\s0\fR is
\&\s-1GNU\s0 make.
.Sp
-This option is disabled by default
+This option is disabled by default.
.IP "\fB\-flto\-partition=\fR\fIalg\fR" 4
.IX Item "-flto-partition=alg"
Specify the partitioning algorithm used by the link-time optimizer.
The value is either \f(CW\*(C`1to1\*(C'\fR to specify a partitioning mirroring
the original source files or \f(CW\*(C`balanced\*(C'\fR to specify partitioning
-into equally sized chunks (whenever possible). Specifying \f(CW\*(C`none\*(C'\fR
-as an algorithm disables partitioning and streaming completely. The
-default value is \f(CW\*(C`balanced\*(C'\fR.
+into equally sized chunks (whenever possible) or \f(CW\*(C`max\*(C'\fR to create
+new partition for every symbol where possible. Specifying \f(CW\*(C`none\*(C'\fR
+as an algorithm disables partitioning and streaming completely.
+The default value is \f(CW\*(C`balanced\*(C'\fR. While \f(CW\*(C`1to1\*(C'\fR can be used
+as an workaround for various code ordering issues, the \f(CW\*(C`max\*(C'\fR
+partitioning is intended for internal testing only.
.IP "\fB\-flto\-compression\-level=\fR\fIn\fR" 4
.IX Item "-flto-compression-level=n"
This option specifies the level of compression used for intermediate
.Sp
\&\fB\-fno\-fat\-lto\-objects\fR improves compilation time over plain \s-1LTO\s0, but
requires the complete toolchain to be aware of \s-1LTO\s0. It requires a linker with
-linker plugin support for basic functionality. Additionally, nm, ar and ranlib
+linker plugin support for basic functionality. Additionally,
+\&\fBnm\fR, \fBar\fR and \fBranlib\fR
need to support linker plugins to allow a full-featured build environment
-(capable of building static libraries etc).
+(capable of building static libraries etc). \s-1GCC\s0 provides the \fBgcc-ar\fR,
+\&\fBgcc-nm\fR, \fBgcc-ranlib\fR wrappers to pass the right options
+to these tools. With non fat \s-1LTO\s0 makefiles need to be modified to use them.
.Sp
The default is \fB\-ffat\-lto\-objects\fR but this default is intended to
change in future releases when linker plugin enabled environments become more
the comparison operation before register allocation is complete.
.Sp
Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
+.IP "\fB\-fuse\-ld=bfd\fR" 4
+.IX Item "-fuse-ld=bfd"
+Use the \fBbfd\fR linker instead of the default linker.
+.IP "\fB\-fuse\-ld=gold\fR" 4
+.IX Item "-fuse-ld=gold"
+Use the \fBgold\fR linker instead of the default linker.
.IP "\fB\-fcprop\-registers\fR" 4
.IX Item "-fcprop-registers"
After register allocation and post-register allocation instruction splitting,
-we perform a copy-propagation pass to try to reduce scheduling dependencies
+perform a copy-propagation pass to try to reduce scheduling dependencies
and occasionally eliminate the copy.
.Sp
Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.IX Item "-fprofile-correction"
Profiles collected using an instrumented binary for multi-threaded programs may
be inconsistent due to missed counter updates. When this option is specified,
-\&\s-1GCC\s0 will use heuristics to correct or smooth out such inconsistencies. By
-default, \s-1GCC\s0 will emit an error message when an inconsistent profile is detected.
+\&\s-1GCC\s0 uses heuristics to correct or smooth out such inconsistencies. By
+default, \s-1GCC\s0 emits an error message when an inconsistent profile is detected.
.IP "\fB\-fprofile\-dir=\fR\fIpath\fR" 4
.IX Item "-fprofile-dir=path"
Set the directory to search for the profile data files in to \fIpath\fR.
\&\fB\-fprofile\-generate\fR, \fB\-ftest\-coverage\fR, \fB\-fprofile\-arcs\fR
and used by \fB\-fprofile\-use\fR and \fB\-fbranch\-probabilities\fR
and its related options. Both absolute and relative paths can be used.
-By default, \s-1GCC\s0 will use the current directory as \fIpath\fR, thus the
-profile data file will appear in the same directory as the object file.
+By default, \s-1GCC\s0 uses the current directory as \fIpath\fR, thus the
+profile data file appears in the same directory as the object file.
.IP "\fB\-fprofile\-generate\fR" 4
.IX Item "-fprofile-generate"
.PD 0
.Sp
The following options are enabled: \f(CW\*(C`\-fprofile\-arcs\*(C'\fR, \f(CW\*(C`\-fprofile\-values\*(C'\fR, \f(CW\*(C`\-fvpt\*(C'\fR.
.Sp
-If \fIpath\fR is specified, \s-1GCC\s0 will look at the \fIpath\fR to find
+If \fIpath\fR is specified, \s-1GCC\s0 looks at the \fIpath\fR to find
the profile feedback data files. See \fB\-fprofile\-dir\fR.
.IP "\fB\-fprofile\-use\fR" 4
.IX Item "-fprofile-use"
generally profitable only with profile feedback available.
.Sp
The following options are enabled: \f(CW\*(C`\-fbranch\-probabilities\*(C'\fR, \f(CW\*(C`\-fvpt\*(C'\fR,
-\&\f(CW\*(C`\-funroll\-loops\*(C'\fR, \f(CW\*(C`\-fpeel\-loops\*(C'\fR, \f(CW\*(C`\-ftracer\*(C'\fR
+\&\f(CW\*(C`\-funroll\-loops\*(C'\fR, \f(CW\*(C`\-fpeel\-loops\*(C'\fR, \f(CW\*(C`\-ftracer\*(C'\fR, \f(CW\*(C`\-ftree\-vectorize\*(C'\fR,
+\&\f(CW\*(C`ftree\-loop\-distribute\-patterns\*(C'\fR
.Sp
By default, \s-1GCC\s0 emits an error message if the feedback profiles do not
match the source code. This error can be turned into a warning by using
\&\fB\-Wcoverage\-mismatch\fR. Note this may result in poorly optimized
code.
.Sp
-If \fIpath\fR is specified, \s-1GCC\s0 will look at the \fIpath\fR to find
+If \fIpath\fR is specified, \s-1GCC\s0 looks at the \fIpath\fR to find
the profile feedback data files. See \fB\-fprofile\-dir\fR.
.PP
The following options control compiler behavior regarding floating-point
it is unpredictable when rounding to the types specified in the source
code takes place. When compiling C, if
\&\fB\-fexcess\-precision=standard\fR is specified then excess
-precision will follow the rules specified in \s-1ISO\s0 C99; in particular,
+precision follows the rules specified in \s-1ISO\s0 C99; in particular,
both casts and assignments cause values to be rounded to their
semantic types (whereas \fB\-ffloat\-store\fR only affects
assignments). This option is enabled by default for C if a strict
that do not require the guarantees of these specifications.
.IP "\fB\-fno\-math\-errno\fR" 4
.IX Item "-fno-math-errno"
-Do not set \s-1ERRNO\s0 after calling math functions that are executed
-with a single instruction, e.g., sqrt. A program that relies on
+Do not set \f(CW\*(C`errno\*(C'\fR after calling math functions that are executed
+with a single instruction, e.g., \f(CW\*(C`sqrt\*(C'\fR. A program that relies on
\&\s-1IEEE\s0 exceptions for math error handling may want to use this flag
for speed while maintaining \s-1IEEE\s0 arithmetic compatibility.
.Sp
.IX Item "-fbranch-probabilities"
After running a program compiled with \fB\-fprofile\-arcs\fR, you can compile it a second time using
\&\fB\-fbranch\-probabilities\fR, to improve optimizations based on
-the number of times each branch was taken. When the program
-compiled with \fB\-fprofile\-arcs\fR exits it saves arc execution
+the number of times each branch was taken. When a program
+compiled with \fB\-fprofile\-arcs\fR exits, it saves arc execution
counts to a file called \fI\fIsourcename\fI.gcda\fR for each source
file. The information in this data file is very dependent on the
structure of the generated code, so you must use the same source code
Enabled with \fB\-fprofile\-generate\fR and \fB\-fprofile\-use\fR.
.IP "\fB\-fvpt\fR" 4
.IX Item "-fvpt"
-If combined with \fB\-fprofile\-arcs\fR, it instructs the compiler to add
-a code to gather information about values of expressions.
+If combined with \fB\-fprofile\-arcs\fR, this option instructs the compiler
+to add code to gather information about values of expressions.
.Sp
With \fB\-fbranch\-probabilities\fR, it reads back the data gathered
and actually performs the optimizations based on them.
-Currently the optimizations include specialization of division operation
+Currently the optimizations include specialization of division operations
using the knowledge about the value of the denominator.
.IP "\fB\-frename\-registers\fR" 4
.IX Item "-frename-registers"
Attempt to avoid false dependencies in scheduled code by making use
of registers left over after register allocation. This optimization
-will most benefit processors with lots of registers. Depending on the
+most benefits processors with lots of registers. Depending on the
debug information format adopted by the target, however, it can
-make debugging impossible, since variables will no longer stay in
+make debugging impossible, since variables no longer stay in
a \*(L"home register\*(R".
.Sp
Enabled by default with \fB\-funroll\-loops\fR and \fB\-fpeel\-loops\fR.
.IX Item "-ftracer"
Perform tail duplication to enlarge superblock size. This transformation
simplifies the control flow of the function allowing other optimizations to do
-better job.
+a better job.
.Sp
Enabled with \fB\-fprofile\-use\fR.
.IP "\fB\-funroll\-loops\fR" 4
upon entry to the loop. \fB\-funroll\-loops\fR implies
\&\fB\-frerun\-cse\-after\-loop\fR, \fB\-fweb\fR and \fB\-frename\-registers\fR.
It also turns on complete loop peeling (i.e. complete removal of loops with
-small constant number of iterations). This option makes code larger, and may
+a small constant number of iterations). This option makes code larger, and may
or may not make it run faster.
.Sp
Enabled with \fB\-fprofile\-use\fR.
the future.
.Sp
Only use these options when there are significant benefits from doing
-so. When you specify these options, the assembler and linker will
-create larger object and executable files and will also be slower.
-You will not be able to use \f(CW\*(C`gprof\*(C'\fR on all systems if you
-specify this option and you may have problems with debugging if
+so. When you specify these options, the assembler and linker
+create larger object and executable files and are also slower.
+You cannot use \f(CW\*(C`gprof\*(C'\fR on all systems if you
+specify this option, and you may have problems with debugging if
you specify both this option and \fB\-g\fR.
.IP "\fB\-fbranch\-target\-load\-optimize\fR" 4
.IX Item "-fbranch-target-load-optimize"
.IP "\fB\-fbtr\-bb\-exclusive\fR" 4
.IX Item "-fbtr-bb-exclusive"
When performing branch target register load optimization, don't reuse
-branch target registers in within any basic block.
+branch target registers within any basic block.
.IP "\fB\-fstack\-protector\fR" 4
.IX Item "-fstack-protector"
Emit extra code to check for buffer overflows, such as stack smashing
attacks. This is done by adding a guard variable to functions with
-vulnerable objects. This includes functions that call alloca, and
+vulnerable objects. This includes functions that call \f(CW\*(C`alloca\*(C'\fR, and
functions with buffers larger than 8 bytes. The guards are initialized
when a function is entered and then checked when the function exits.
If a guard check fails, an error message is printed and the program exits.
\& int foo (void) { return a + b + c; }
.Ve
.Sp
-would usually calculate the addresses of all three variables, but if you
-compile it with \fB\-fsection\-anchors\fR, it will access the variables
+usually calculates the addresses of all three variables, but if you
+compile it with \fB\-fsection\-anchors\fR, it accesses the variables
from a common anchor point instead. The effect is similar to the
following pseudocode (which isn't valid C):
.Sp
.IP "\fB\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR" 4
.IX Item "--param name=value"
In some places, \s-1GCC\s0 uses various constants to control the amount of
-optimization that is done. For example, \s-1GCC\s0 will not inline functions
+optimization that is done. For example, \s-1GCC\s0 does not inline functions
that contain more than a certain number of instructions. You can
control some of these constants on the command line using the
\&\fB\-\-param\fR option.
without notice in future releases.
.Sp
In each case, the \fIvalue\fR is an integer. The allowable choices for
-\&\fIname\fR are given in the following table:
+\&\fIname\fR are:
.RS 4
.IP "\fBpredictable-branch-outcome\fR" 4
.IX Item "predictable-branch-outcome"
(in percent), then it is considered well predictable. The default is 10.
.IP "\fBmax-crossjump-edges\fR" 4
.IX Item "max-crossjump-edges"
-The maximum number of incoming edges to consider for crossjumping.
+The maximum number of incoming edges to consider for cross-jumping.
The algorithm used by \fB\-fcrossjumping\fR is O(N^2) in
the number of edges incoming to each block. Increasing values mean
more aggressive optimization, making the compilation time increase with
.IP "\fBmin-crossjump-insns\fR" 4
.IX Item "min-crossjump-insns"
The minimum number of instructions that must be matched at the end
-of two blocks before crossjumping will be performed on them. This
+of two blocks before cross-jumping is performed on them. This
value is ignored in the case where all instructions in the block being
-crossjumped from are matched. The default value is 5.
+cross-jumped from are matched. The default value is 5.
.IP "\fBmax-grow-copy-bb-insns\fR" 4
.IX Item "max-grow-copy-bb-insns"
The maximum code size expansion factor when copying basic blocks
.IX Item "max-delay-slot-insn-search"
The maximum number of instructions to consider when looking for an
instruction to fill a delay slot. If more than this arbitrary number of
-instructions is searched, the time savings from filling the delay slot
-will be minimal so stop searching. Increasing values mean more
+instructions are searched, the time savings from filling the delay slot
+are minimal, so stop searching. Increasing values mean more
aggressive optimization, making the compilation time increase with probably
small improvement in execution time.
.IP "\fBmax-delay-slot-live-search\fR" 4
control-flow graph.
.IP "\fBmax-gcse-memory\fR" 4
.IX Item "max-gcse-memory"
-The approximate maximum amount of memory that will be allocated in
+The approximate maximum amount of memory that can be allocated in
order to perform the global common subexpression elimination
optimization. If more memory than specified is required, the
-optimization will not be done.
+optimization is not done.
.IP "\fBmax-gcse-insertion-ratio\fR" 4
.IX Item "max-gcse-insertion-ratio"
If the ratio of expression insertions to deletions is larger than this value
-for any expression, then \s-1RTL\s0 \s-1PRE\s0 will insert or remove the expression and thus
-leave partially redundant computations in the instruction stream. The default value is 20.
+for any expression, then \s-1RTL\s0 \s-1PRE\s0 inserts or removes the expression and thus
+leaves partially redundant computations in the instruction stream. The default value is 20.
.IP "\fBmax-pending-list-length\fR" 4
.IX Item "max-pending-list-length"
-The maximum number of pending dependencies scheduling will allow
+The maximum number of pending dependencies scheduling allows
before flushing the current state and starting over. Large functions
with few branches or calls can create excessively large lists which
needlessly consume memory and resources.
compilation time.
.IP "\fBmax-inline-insns-single\fR" 4
.IX Item "max-inline-insns-single"
-Several parameters control the tree inliner used in gcc.
+Several parameters control the tree inliner used in \s-1GCC\s0.
This number sets the maximum number of instructions (counted in \s-1GCC\s0's
internal representation) in a single function that the tree inliner
-will consider for inlining. This only affects functions declared
+considers for inlining. This only affects functions declared
inline and methods implemented in a class declaration (\*(C+).
The default value is 400.
.IP "\fBmax-inline-insns-auto\fR" 4
.IX Item "max-inline-insns-auto"
When you use \fB\-finline\-functions\fR (included in \fB\-O3\fR),
a lot of functions that would otherwise not be considered for inlining
-by the compiler will be investigated. To those functions, a different
+by the compiler are investigated. To those functions, a different
(more restrictive) limit compared to functions declared inline can
be applied.
The default value is 40.
+.IP "\fBinline-min-speedup\fR" 4
+.IX Item "inline-min-speedup"
+When estimated performance improvement of caller + callee runtime exceeds this
+threshold (in precent), the function can be inlined regardless the limit on
+\&\fB\-\-param max-inline-insns-single\fR and \fB\-\-param
+max-inline-insns-auto\fR.
.IP "\fBlarge-function-insns\fR" 4
.IX Item "large-function-insns"
The limit specifying really large functions. For functions larger than this
.IX Item "large-unit-insns"
The limit specifying large translation unit. Growth caused by inlining of
units larger than this limit is limited by \fB\-\-param inline-unit-growth\fR.
-For small units this might be too tight (consider unit consisting of function A
-that is inline and B that just calls A three time. If B is small relative to
+For small units this might be too tight.
+For example, consider a unit consisting of function A
+that is inline and B that just calls A three times. If B is small relative to
A, the growth of unit is 300\e% and yet such inlining is very sane. For very
-large units consisting of small inlineable functions however the overall unit
+large units consisting of small inlineable functions, however, the overall unit
growth limit is needed to avoid exponential explosion of code size. Thus for
smaller units, the size is increased to \fB\-\-param large-unit-insns\fR
-before applying \fB\-\-param inline-unit-growth\fR. The default is 10000
+before applying \fB\-\-param inline-unit-growth\fR. The default is 10000.
.IP "\fBinline-unit-growth\fR" 4
.IX Item "inline-unit-growth"
Specifies maximal overall growth of the compilation unit caused by inlining.
.IP "\fBlarge-stack-frame\fR" 4
.IX Item "large-stack-frame"
The limit specifying large stack frames. While inlining the algorithm is trying
-to not grow past this limit too much. Default value is 256 bytes.
+to not grow past this limit too much. The default value is 256 bytes.
.IP "\fBlarge-stack-frame-growth\fR" 4
.IX Item "large-stack-frame-growth"
Specifies maximal growth of large stack frames caused by inlining in percents.
.IP "\fBmax-inline-insns-recursive-auto\fR" 4
.IX Item "max-inline-insns-recursive-auto"
.PD
-Specifies maximum number of instructions out-of-line copy of self recursive inline
+Specifies the maximum number of instructions an out-of-line copy of a
+self-recursive inline
function can grow into by performing recursive inlining.
.Sp
-For functions declared inline \fB\-\-param max-inline-insns-recursive\fR is
-taken into account. For function not declared inline, recursive inlining
+For functions declared inline, \fB\-\-param max-inline-insns-recursive\fR is
+taken into account. For functions not declared inline, recursive inlining
happens only when \fB\-finline\-functions\fR (included in \fB\-O3\fR) is
enabled and \fB\-\-param max-inline-insns-recursive-auto\fR is used. The
default value is 450.
.IP "\fBmax-inline-recursive-depth-auto\fR" 4
.IX Item "max-inline-recursive-depth-auto"
.PD
-Specifies maximum recursion depth used by the recursive inlining.
+Specifies the maximum recursion depth used for recursive inlining.
.Sp
-For functions declared inline \fB\-\-param max-inline-recursive-depth\fR is
-taken into account. For function not declared inline, recursive inlining
+For functions declared inline, \fB\-\-param max-inline-recursive-depth\fR is
+taken into account. For functions not declared inline, recursive inlining
happens only when \fB\-finline\-functions\fR (included in \fB\-O3\fR) is
enabled and \fB\-\-param max-inline-recursive-depth-auto\fR is used. The
default value is 8.
optimizers.
.Sp
When profile feedback is available (see \fB\-fprofile\-generate\fR) the actual
-recursion depth can be guessed from probability that function will recurse via
-given call expression. This parameter limits inlining only to call expression
-whose probability exceeds given threshold (in percents). The default value is
-10.
+recursion depth can be guessed from probability that function recurses via a
+given call expression. This parameter limits inlining only to call expressions
+whose probability exceeds the given threshold (in percents).
+The default value is 10.
.IP "\fBearly-inlining-insns\fR" 4
.IX Item "early-inlining-insns"
-Specify growth that early inliner can make. In effect it increases amount of
-inlining for code having large abstraction penalty. The default value is 10.
+Specify growth that the early inliner can make. In effect it increases
+the amount of inlining for code having a large abstraction penalty.
+The default value is 10.
.IP "\fBmax-early-inliner-iterations\fR" 4
.IX Item "max-early-inliner-iterations"
.PD 0
.IP "\fBmax-early-inliner-iterations\fR" 4
.IX Item "max-early-inliner-iterations"
.PD
-Limit of iterations of early inliner. This basically bounds number of nested
-indirect calls early inliner can resolve. Deeper chains are still handled by
-late inlining.
+Limit of iterations of the early inliner. This basically bounds
+the number of nested indirect calls the early inliner can resolve.
+Deeper chains are still handled by late inlining.
.IP "\fBcomdat-sharing-probability\fR" 4
.IX Item "comdat-sharing-probability"
.PD 0
.IX Item "comdat-sharing-probability"
.PD
Probability (in percent) that \*(C+ inline function with comdat visibility
-will be shared across multiple compilation units. The default value is 20.
+are shared across multiple compilation units. The default value is 20.
.IP "\fBmin-vect-loop-bound\fR" 4
.IX Item "min-vect-loop-bound"
-The minimum number of iterations under which a loop will not get vectorized
+The minimum number of iterations under which loops are not vectorized
when \fB\-ftree\-vectorize\fR is used. The number of iterations after
vectorization needs to be greater than the value specified by this option
to allow vectorization. The default value is 0.
Scaling factor in calculation of maximum distance an expression
can be moved by \s-1GCSE\s0 optimizations. This is currently supported only in the
code hoisting pass. The bigger the ratio, the more aggressive code hoisting
-will be with simple expressions, i.e., the expressions that have cost
-less than \fBgcse-unrestricted-cost\fR. Specifying 0 will disable
+is with simple expressions, i.e., the expressions that have cost
+less than \fBgcse-unrestricted-cost\fR. Specifying 0 disables
hoisting of simple expressions. The default value is 10.
.IP "\fBgcse-unrestricted-cost\fR" 4
.IX Item "gcse-unrestricted-cost"
Cost, roughly measured as the cost of a single typical machine
-instruction, at which \s-1GCSE\s0 optimizations will not constrain
+instruction, at which \s-1GCSE\s0 optimizations do not constrain
the distance an expression can travel. This is currently
supported only in the code hoisting pass. The lesser the cost,
-the more aggressive code hoisting will be. Specifying 0 will
-allow all expressions to travel unrestricted distances.
+the more aggressive code hoisting is. Specifying 0
+allows all expressions to travel unrestricted distances.
The default value is 3.
.IP "\fBmax-hoist-depth\fR" 4
.IX Item "max-hoist-depth"
The depth of search in the dominator tree for expressions to hoist.
This is used to avoid quadratic behavior in hoisting algorithm.
-The value of 0 will avoid limiting the search, but may slow down compilation
+The value of 0 does not limit on the search, but may slow down compilation
of huge functions. The default value is 30.
.IP "\fBmax-tail-merge-comparisons\fR" 4
.IX Item "max-tail-merge-comparisons"
limit compilation time in tree tail merging. The default value is 2.
.IP "\fBmax-unrolled-insns\fR" 4
.IX Item "max-unrolled-insns"
-The maximum number of instructions that a loop should have if that loop
-is unrolled, and if the loop is unrolled, it determines how many times
+The maximum number of instructions that a loop may have to be unrolled.
+If a loop is unrolled, this parameter also determines how many times
the loop code is unrolled.
.IP "\fBmax-average-unrolled-insns\fR" 4
.IX Item "max-average-unrolled-insns"
The maximum number of instructions biased by probabilities of their execution
-that a loop should have if that loop is unrolled, and if the loop is unrolled,
-it determines how many times the loop code is unrolled.
+that a loop may have to be unrolled. If a loop is unrolled,
+this parameter also determines how many times the loop code is unrolled.
.IP "\fBmax-unroll-times\fR" 4
.IX Item "max-unroll-times"
The maximum number of unrollings of a single loop.
.IP "\fBmax-peeled-insns\fR" 4
.IX Item "max-peeled-insns"
-The maximum number of instructions that a loop should have if that loop
-is peeled, and if the loop is peeled, it determines how many times
+The maximum number of instructions that a loop may have to be peeled.
+If a loop is peeled, this parameter also determines how many times
the loop code is peeled.
.IP "\fBmax-peel-times\fR" 4
.IX Item "max-peel-times"
The maximum number of peelings of a single loop.
+.IP "\fBmax-peel-branches\fR" 4
+.IX Item "max-peel-branches"
+The maximum number of branches on the hot path through the peeled sequence.
.IP "\fBmax-completely-peeled-insns\fR" 4
.IX Item "max-completely-peeled-insns"
The maximum number of insns of a completely peeled loop.
The minimum cost of an expensive expression in the loop invariant motion.
.IP "\fBiv-consider-all-candidates-bound\fR" 4
.IX Item "iv-consider-all-candidates-bound"
-Bound on number of candidates for induction variables below that
+Bound on number of candidates for induction variables, below which
all candidates are considered for each use in induction variable
-optimizations. Only the most relevant candidates are considered
-if there are more candidates, to avoid quadratic time complexity.
+optimizations. If there are more candidates than this,
+only the most relevant ones are considered to avoid quadratic time complexity.
.IP "\fBiv-max-considered-uses\fR" 4
.IX Item "iv-max-considered-uses"
The induction variable optimizations give up on loops that contain more
induction variable uses.
.IP "\fBiv-always-prune-cand-set-bound\fR" 4
.IX Item "iv-always-prune-cand-set-bound"
-If number of candidates in the set is smaller than this value,
-we always try to remove unnecessary ivs from the set during its
-optimization when a new iv is added to the set.
+If the number of candidates in the set is smaller than this value,
+always try to remove unnecessary ivs from the set
+when adding a new one.
.IP "\fBscev-max-expr-size\fR" 4
.IX Item "scev-max-expr-size"
Bound on size of expressions used in the scalar evolutions analyzer.
The default value is 128.
.IP "\fBomega-max-wild-cards\fR" 4
.IX Item "omega-max-wild-cards"
-The maximum number of wildcard variables that the Omega solver will
-be able to insert. The default value is 18.
+The maximum number of wildcard variables that the Omega solver is
+able to insert. The default value is 18.
.IP "\fBomega-hash-table-size\fR" 4
.IX Item "omega-hash-table-size"
The size of the hash table in the Omega solver. The default value is
.IX Item "vect-max-version-for-alignment-checks"
The maximum number of run-time checks that can be performed when
doing loop versioning for alignment in the vectorizer. See option
-ftree-vect-loop-version for more information.
+\&\fB\-ftree\-vect\-loop\-version\fR for more information.
.IP "\fBvect-max-version-for-alias-checks\fR" 4
.IX Item "vect-max-version-for-alias-checks"
The maximum number of run-time checks that can be performed when
doing loop versioning for alias in the vectorizer. See option
-ftree-vect-loop-version for more information.
+\&\fB\-ftree\-vect\-loop\-version\fR for more information.
.IP "\fBmax-iterations-to-track\fR" 4
.IX Item "max-iterations-to-track"
-The maximum number of iterations of a loop the brute force algorithm
-for analysis of # of iterations of the loop tries to evaluate.
-.IP "\fBhot-bb-count-fraction\fR" 4
-.IX Item "hot-bb-count-fraction"
-Select fraction of the maximal count of repetitions of basic block in program
-given basic block needs to have to be considered hot.
+The maximum number of iterations of a loop the brute-force algorithm
+for analysis of the number of iterations of the loop tries to evaluate.
+.IP "\fBhot-bb-count-ws-permille\fR" 4
+.IX Item "hot-bb-count-ws-permille"
+A basic block profile count is considered hot if it contributes to
+the given permillage (i.e. 0...1000) of the entire profiled execution.
.IP "\fBhot-bb-frequency-fraction\fR" 4
.IX Item "hot-bb-frequency-fraction"
Select fraction of the entry block frequency of executions of basic block in
.IP "\fBmax-predicted-iterations\fR" 4
.IX Item "max-predicted-iterations"
The maximum number of loop iterations we predict statically. This is useful
-in cases where function contain single loop with known bound and other loop
-with unknown. We predict the known number of iterations correctly, while
+in cases where a function contains a single loop with known bound and
+another loop with unknown bound.
+The known number of iterations is predicted correctly, while
the unknown number of iterations average to roughly 10. This means that the
-loop without bounds would appear artificially cold relative to the other one.
+loop without bounds appears artificially cold relative to the other one.
.IP "\fBalign-threshold\fR" 4
.IX Item "align-threshold"
-Select fraction of the maximal frequency of executions of basic block in
-function given basic block will get aligned.
+Select fraction of the maximal frequency of executions of a basic block in
+a function to align the basic block.
.IP "\fBalign-loop-iterations\fR" 4
.IX Item "align-loop-iterations"
-A loop expected to iterate at lest the selected number of iterations will get
+A loop expected to iterate at least the selected number of iterations is
aligned.
.IP "\fBtracer-dynamic-coverage\fR" 4
.IX Item "tracer-dynamic-coverage"
.IP "\fBtracer-max-code-growth\fR" 4
.IX Item "tracer-max-code-growth"
Stop tail duplication once code growth has reached given percentage. This is
-rather hokey argument, as most of the duplicates will be eliminated later in
+a rather artificial limit, as most of the duplicates are eliminated later in
cross jumping, so it may be set to much higher values than is the desired code
growth.
.IP "\fBtracer-min-branch-ratio\fR" 4
.IP "\fBtracer-min-branch-ratio-feedback\fR" 4
.IX Item "tracer-min-branch-ratio-feedback"
.PD
-Stop forward growth if the best edge do have probability lower than this
+Stop forward growth if the best edge has probability lower than this
threshold.
.Sp
Similarly to \fBtracer-dynamic-coverage\fR two values are present, one for
order to make tracer effective.
.IP "\fBmax-cse-path-length\fR" 4
.IX Item "max-cse-path-length"
-Maximum number of basic blocks on path that cse considers. The default is 10.
+The maximum number of basic blocks on path that \s-1CSE\s0 considers.
+The default is 10.
.IP "\fBmax-cse-insns\fR" 4
.IX Item "max-cse-insns"
-The maximum instructions \s-1CSE\s0 process before flushing. The default is 1000.
+The maximum number of instructions \s-1CSE\s0 processes before flushing.
+The default is 1000.
.IP "\fBggc-min-expand\fR" 4
.IX Item "ggc-min-expand"
\&\s-1GCC\s0 uses a garbage collector to manage its own memory allocation. This
.IP "\fBreorder-blocks-duplicate-feedback\fR" 4
.IX Item "reorder-blocks-duplicate-feedback"
.PD
-Used by basic block reordering pass to decide whether to use unconditional
+Used by the basic block reordering pass to decide whether to use unconditional
branch or duplicate the code on its destination. Code is duplicated when its
estimated size is smaller than this value multiplied by the estimated size of
unconditional jump in the hot spots of the program.
.Sp
The \fBreorder-block-duplicate-feedback\fR is used only when profile
-feedback is available and may be set to higher values than
+feedback is available. It may be set to higher values than
\&\fBreorder-block-duplicate\fR since information about the hot spots is more
accurate.
.IP "\fBmax-sched-ready-insns\fR" 4
.IP "\fBmax-sched-extend-regions-iters\fR" 4
.IX Item "max-sched-extend-regions-iters"
The maximum number of iterations through \s-1CFG\s0 to extend regions.
-0 \- disable region extension,
-N \- do at most N iterations.
-The default value is 0.
+A value of 0 (the default) disables region extensions.
.IP "\fBmax-sched-insn-conflict-delay\fR" 4
.IX Item "max-sched-insn-conflict-delay"
The maximum conflict delay for an insn to be considered for speculative motion.
.IP "\fBsched-spec-prob-cutoff\fR" 4
.IX Item "sched-spec-prob-cutoff"
The minimal probability of speculation success (in percents), so that
-speculative insn will be scheduled.
+speculative insns are scheduled.
The default value is 40.
+.IP "\fBsched-spec-state-edge-prob-cutoff\fR" 4
+.IX Item "sched-spec-state-edge-prob-cutoff"
+The minimum probability an edge must have for the scheduler to save its
+state across it.
+The default value is 10.
.IP "\fBsched-mem-true-dep-cost\fR" 4
.IX Item "sched-mem-true-dep-cost"
Minimal distance (in \s-1CPU\s0 cycles) between store and load targeting same
The default value is 50.
.IP "\fBselsched-max-sched-times\fR" 4
.IX Item "selsched-max-sched-times"
-The maximum number of times that an instruction will be scheduled during
+The maximum number of times that an instruction is scheduled during
selective scheduling. This is the limit on the number of iterations
through which the instruction may be pipelined. The default value is 2.
.IP "\fBselsched-max-insns-to-rename\fR" 4
for renaming in the selective scheduler. The default value is 2.
.IP "\fBsms-min-sc\fR" 4
.IX Item "sms-min-sc"
-The minimum value of stage count that swing modulo scheduler will
-generate. The default value is 2.
+The minimum value of stage count that swing modulo scheduler
+generates. The default value is 2.
.IP "\fBmax-last-value-rtl\fR" 4
.IX Item "max-last-value-rtl"
The maximum size measured as number of RTLs that can be recorded in an expression
Small integer constants can use a shared data structure, reducing the
compiler's memory usage and increasing its speed. This sets the maximum
value of a shared integer constant. The default value is 256.
-.IP "\fBmin-virtual-mappings\fR" 4
-.IX Item "min-virtual-mappings"
-Specifies the minimum number of virtual mappings in the incremental
-\&\s-1SSA\s0 updater that should be registered to trigger the virtual mappings
-heuristic defined by virtual-mappings-ratio. The default value is
-100.
-.IP "\fBvirtual-mappings-ratio\fR" 4
-.IX Item "virtual-mappings-ratio"
-If the number of virtual mappings is virtual-mappings-ratio bigger
-than the number of virtual symbols to be updated, then the incremental
-\&\s-1SSA\s0 updater switches to a full update for those symbols. The default
-ratio is 3.
.IP "\fBssp-buffer-size\fR" 4
.IX Item "ssp-buffer-size"
-The minimum size of buffers (i.e. arrays) that will receive stack smashing
+The minimum size of buffers (i.e. arrays) that receive stack smashing
protection when \fB\-fstack\-protection\fR is used.
.IP "\fBmax-jump-thread-duplication-stmts\fR" 4
.IX Item "max-jump-thread-duplication-stmts"
duplicated when threading jumps.
.IP "\fBmax-fields-for-field-sensitive\fR" 4
.IX Item "max-fields-for-field-sensitive"
-Maximum number of fields in a structure we will treat in
+Maximum number of fields in a structure treated in
a field sensitive manner during pointer analysis. The default is zero
-for \-O0, and \-O1 and 100 for \-Os, \-O2, and \-O3.
+for \fB\-O0\fR and \fB\-O1\fR,
+and 100 for \fB\-Os\fR, \fB\-O2\fR, and \fB\-O3\fR.
.IP "\fBprefetch-latency\fR" 4
.IX Item "prefetch-latency"
Estimate on average number of instructions that are executed before
-prefetch finishes. The distance we prefetch ahead is proportional
+prefetch finishes. The distance prefetched ahead is proportional
to this constant. Increasing this number may also lead to less
streams being prefetched (see \fBsimultaneous-prefetches\fR).
.IP "\fBsimultaneous-prefetches\fR" 4
set this value to 0 to disable canonical types.
.IP "\fBswitch-conversion-max-branch-ratio\fR" 4
.IX Item "switch-conversion-max-branch-ratio"
-Switch initialization conversion will refuse to create arrays that are
+Switch initialization conversion refuses to create arrays that are
bigger than \fBswitch-conversion-max-branch-ratio\fR times the number of
branches in the switch.
.IP "\fBmax-partial-antic-length\fR" 4
consuming all of the memory available on the host machine. This
parameter sets a limit on the length of the sets that are computed,
which prevents the runaway behavior. Setting a value of 0 for
-this parameter will allow an unlimited set length.
+this parameter allows an unlimited set length.
.IP "\fBsccvn-max-scc-size\fR" 4
.IX Item "sccvn-max-scc-size"
Maximum size of a strongly connected component (\s-1SCC\s0) during \s-1SCCVN\s0
processing. If this limit is hit, \s-1SCCVN\s0 processing for the whole
-function will not be done and optimizations depending on it will
-be disabled. The default maximum \s-1SCC\s0 size is 10000.
+function is not done and optimizations depending on it are
+disabled. The default maximum \s-1SCC\s0 size is 10000.
+.IP "\fBsccvn-max-alias-queries-per-access\fR" 4
+.IX Item "sccvn-max-alias-queries-per-access"
+Maximum number of alias-oracle queries we perform when looking for
+redundancies for loads and stores. If this limit is hit the search
+is aborted and the load or store is not considered redundant. The
+number of queries is algorithmically limited to the number of
+stores on all paths from the load to the function entry.
+The default maxmimum number of queries is 1000.
.IP "\fBira-max-loops-num\fR" 4
.IX Item "ira-max-loops-num"
\&\s-1IRA\s0 uses regional register allocation by default. If a function
in amount of needed compile-time memory, with very large loops. Loops
with more basic blocks than this parameter won't have loop invariant
motion optimization performed on them. The default value of the
-parameter is 1000 for \-O1 and 10000 for \-O2 and above.
+parameter is 1000 for \fB\-O1\fR and 10000 for \fB\-O2\fR and above.
.IP "\fBloop-max-datarefs-for-datadeps\fR" 4
.IX Item "loop-max-datarefs-for-datadeps"
Building data dapendencies is expensive for very large loops. This
parameter limits the number of data references in loops that are
-considered for data dependence analysis. These large loops will not
-be handled then by the optimizations using loop data dependencies.
+considered for data dependence analysis. These large loops are no
+handled by the optimizations using loop data dependencies.
The default value is 1000.
.IP "\fBmax-vartrack-size\fR" 4
.IX Item "max-vartrack-size"
(non-overlapping) uids above it if the reserved range is exhausted.
.IP "\fBipa-sra-ptr-growth-factor\fR" 4
.IX Item "ipa-sra-ptr-growth-factor"
-IPA-SRA will replace a pointer to an aggregate with one or more new
+IPA-SRA replaces a pointer to an aggregate with one or more new
parameters only when their cumulative size is less or equal to
\&\fBipa-sra-ptr-growth-factor\fR times the size of the original
pointer parameter.
.IP "\fBtm-max-aggregate-size\fR" 4
.IX Item "tm-max-aggregate-size"
When making copies of thread-local variables in a transaction, this
-parameter specifies the size in bytes after which variables will be
+parameter specifies the size in bytes after which variables are
saved with the logging functions as opposed to save/restore code
sequence pairs. This option only applies when using
\&\fB\-fgnu\-tm\fR.
Set the maximum number of instructions executed in parallel in
reassociated tree. This parameter overrides target dependent
heuristics used by default if has non zero value.
+.IP "\fBsched-pressure-algorithm\fR" 4
+.IX Item "sched-pressure-algorithm"
+Choose between the two available implementations of
+\&\fB\-fsched\-pressure\fR. Algorithm 1 is the original implementation
+and is the more likely to prevent instructions from being reordered.
+Algorithm 2 was designed to be a compromise between the relatively
+conservative approach taken by algorithm 1 and the rather aggressive
+approach taken by the default scheduler. It relies more heavily on
+having a regular register file and accurate register pressure classes.
+See \fIhaifa\-sched.c\fR in the \s-1GCC\s0 sources for more details.
+.Sp
+The default choice depends on the target.
+.IP "\fBmax-slsr-cand-scan\fR" 4
+.IX Item "max-slsr-cand-scan"
+Set the maximum number of existing candidates that will be considered when
+seeking a basis for a new straight-line strength reduction candidate.
.RE
.RS 4
.RE
-.Sh "Options Controlling the Preprocessor"
+.SS "Options Controlling the Preprocessor"
.IX Subsection "Options Controlling the Preprocessor"
These options control the C preprocessor, which is run on each C source
file before actual compilation.
.IP "\fB\-Xpreprocessor\fR \fIoption\fR" 4
.IX Item "-Xpreprocessor option"
Pass \fIoption\fR as an option to the preprocessor. You can use this to
-supply system-specific preprocessor options that \s-1GCC\s0 does not know how to
+supply system-specific preprocessor options that \s-1GCC\s0 does not
recognize.
.Sp
If you want to pass an option that takes an argument, you must use
\&\fB\-Xpreprocessor\fR twice, once for the option and once for the argument.
+.IP "\fB\-no\-integrated\-cpp\fR" 4
+.IX Item "-no-integrated-cpp"
+Perform preprocessing as a separate pass before compilation.
+By default, \s-1GCC\s0 performs preprocessing as an integrated part of
+input tokenization and parsing.
+If this option is provided, the appropriate language front end
+(\fBcc1\fR, \fBcc1plus\fR, or \fBcc1obj\fR for C, \*(C+,
+and Objective-C, respectively) is instead invoked twice,
+once for preprocessing only and once for actual compilation
+of the preprocessed input.
+This option may be useful in conjunction with the \fB\-B\fR or
+\&\fB\-wrapper\fR options to specify an alternate preprocessor or
+perform additional processing of the program source between
+normal preprocessing and compilation.
.IP "\fB\-D\fR \fIname\fR" 4
.IX Item "-D name"
Predefine \fIname\fR as a macro, with definition \f(CW1\fR.
Accept universal character names in identifiers. This option is
experimental; in a future version of \s-1GCC\s0, it will be enabled by
default for C99 and \*(C+.
+.IP "\fB\-fno\-canonical\-system\-headers\fR" 4
+.IX Item "-fno-canonical-system-headers"
+When preprocessing, do not shorten system header paths with canonicalization.
.IP "\fB\-fpreprocessed\fR" 4
.IX Item "-fpreprocessed"
Indicate to the preprocessor that the input file has already been
tokens locations completely. This value is the most memory hungry.
When this option is given no argument, the default parameter value is
\&\fB2\fR.
+.Sp
+Note that \-ftrack\-macro\-expansion=2 is activated by default.
.IP "\fB\-fexec\-charset=\fR\fIcharset\fR" 4
.IX Item "-fexec-charset=charset"
Set the execution character set, used for string and character
.PD
Print out \s-1GNU\s0 \s-1CPP\s0's version number. With one dash, proceed to
preprocess as normal. With two dashes, exit immediately.
-.Sh "Passing Options to the Assembler"
+.SS "Passing Options to the Assembler"
.IX Subsection "Passing Options to the Assembler"
You can pass options to the assembler.
.IP "\fB\-Wa,\fR\fIoption\fR" 4
.IP "\fB\-Xassembler\fR \fIoption\fR" 4
.IX Item "-Xassembler option"
Pass \fIoption\fR as an option to the assembler. You can use this to
-supply system-specific assembler options that \s-1GCC\s0 does not know how to
+supply system-specific assembler options that \s-1GCC\s0 does not
recognize.
.Sp
If you want to pass an option that takes an argument, you must use
\&\fB\-Xassembler\fR twice, once for the option and once for the argument.
-.Sh "Options for Linking"
+.SS "Options for Linking"
.IX Subsection "Options for Linking"
These options come into play when the compiler links object files into
an executable output file. They are meaningless if the compiler is
.IP "\fB\-nodefaultlibs\fR" 4
.IX Item "-nodefaultlibs"
Do not use the standard system libraries when linking.
-Only the libraries you specify will be passed to the linker, options
+Only the libraries you specify are passed to the linker, and options
specifying linkage of the system libraries, such as \f(CW\*(C`\-static\-libgcc\*(C'\fR
-or \f(CW\*(C`\-shared\-libgcc\*(C'\fR, will be ignored.
+or \f(CW\*(C`\-shared\-libgcc\*(C'\fR, are ignored.
The standard startup files are used normally, unless \fB\-nostartfiles\fR
-is used. The compiler may generate calls to \f(CW\*(C`memcmp\*(C'\fR,
+is used.
+.Sp
+The compiler may generate calls to \f(CW\*(C`memcmp\*(C'\fR,
\&\f(CW\*(C`memset\*(C'\fR, \f(CW\*(C`memcpy\*(C'\fR and \f(CW\*(C`memmove\*(C'\fR.
These entries are usually resolved by entries in
libc. These entry points should be supplied through some other
.IP "\fB\-nostdlib\fR" 4
.IX Item "-nostdlib"
Do not use the standard system startup files or libraries when linking.
-No startup files and only the libraries you specify will be passed to
-the linker, options specifying linkage of the system libraries, such as
-\&\f(CW\*(C`\-static\-libgcc\*(C'\fR or \f(CW\*(C`\-shared\-libgcc\*(C'\fR, will be ignored.
+No startup files and only the libraries you specify are passed to
+the linker, and options specifying linkage of the system libraries, such as
+\&\f(CW\*(C`\-static\-libgcc\*(C'\fR or \f(CW\*(C`\-shared\-libgcc\*(C'\fR, are ignored.
+.Sp
The compiler may generate calls to \f(CW\*(C`memcmp\*(C'\fR, \f(CW\*(C`memset\*(C'\fR,
\&\f(CW\*(C`memcpy\*(C'\fR and \f(CW\*(C`memmove\*(C'\fR.
These entries are usually resolved by entries in
other standard libraries. In other words, when you specify \fB\-nostdlib\fR
or \fB\-nodefaultlibs\fR you should usually specify \fB\-lgcc\fR as well.
This ensures that you have no unresolved references to internal \s-1GCC\s0
-library subroutines. (For example, \fB_\|_main\fR, used to ensure \*(C+
-constructors will be called.)
+library subroutines.
+(An example of such an internal subroutine is \fB_\|_main\fR, used to ensure \*(C+
+constructors are called.)
.IP "\fB\-pie\fR" 4
.IX Item "-pie"
Produce a position independent executable on targets that support it.
For predictable results, you must also specify the same set of options
-that were used to generate code (\fB\-fpie\fR, \fB\-fPIE\fR,
-or model suboptions) when you specify this option.
+used for compilation (\fB\-fpie\fR, \fB\-fPIE\fR,
+or model suboptions) when you specify this linker option.
.IP "\fB\-rdynamic\fR" 4
.IX Item "-rdynamic"
Pass the flag \fB\-export\-dynamic\fR to the \s-1ELF\s0 linker, on targets
.IX Item "-shared"
Produce a shared object which can then be linked with other objects to
form an executable. Not all systems support this option. For predictable
-results, you must also specify the same set of options that were used to
-generate code (\fB\-fpic\fR, \fB\-fPIC\fR, or model suboptions)
-when you specify this option.[1]
+results, you must also specify the same set of options used for compilation
+(\fB\-fpic\fR, \fB\-fPIC\fR, or model suboptions) when
+you specify this linker option.[1]
.IP "\fB\-shared\-libgcc\fR" 4
.IX Item "-shared-libgcc"
.PD 0
.IX Item "-static-libgcc"
.PD
On systems that provide \fIlibgcc\fR as a shared library, these options
-force the use of either the shared or static version respectively.
+force the use of either the shared or static version, respectively.
If no shared version of \fIlibgcc\fR was built when the compiler was
configured, these options have no effect.
.Sp
this is the right thing to do.
.Sp
If, instead, you use the \s-1GCC\s0 driver to create shared libraries, you may
-find that they will not always be linked with the shared \fIlibgcc\fR.
+find that they are not always linked with the shared \fIlibgcc\fR.
If \s-1GCC\s0 finds, at its configuration time, that you have a non-GNU linker
or a \s-1GNU\s0 linker that does not support option \fB\-\-eh\-frame\-hdr\fR,
-it will link the shared version of \fIlibgcc\fR into shared libraries
-by default. Otherwise, it will take advantage of the linker and optimize
+it links the shared version of \fIlibgcc\fR into shared libraries
+by default. Otherwise, it takes advantage of the linker and optimizes
away the linking with the shared version of \fIlibgcc\fR, linking with
the static version of libgcc by default. This allows exceptions to
propagate through such shared libraries, without incurring relocation
for the languages used in the program, or using the option
\&\fB\-shared\-libgcc\fR, such that it is linked with the shared
\&\fIlibgcc\fR.
+.IP "\fB\-static\-libasan\fR" 4
+.IX Item "-static-libasan"
+When the \fB\-fsanitize=address\fR option is used to link a program,
+the \s-1GCC\s0 driver automatically links against \fBlibasan\fR. If
+\&\fIlibasan\fR is available as a shared library, and the \fB\-static\fR
+option is not used, then this links against the shared version of
+\&\fIlibasan\fR. The \fB\-static\-libasan\fR option directs the \s-1GCC\s0
+driver to link \fIlibasan\fR statically, without necessarily linking
+other libraries statically.
+.IP "\fB\-static\-libtsan\fR" 4
+.IX Item "-static-libtsan"
+When the \fB\-fsanitize=thread\fR option is used to link a program,
+the \s-1GCC\s0 driver automatically links against \fBlibtsan\fR. If
+\&\fIlibtsan\fR is available as a shared library, and the \fB\-static\fR
+option is not used, then this links against the shared version of
+\&\fIlibtsan\fR. The \fB\-static\-libtsan\fR option directs the \s-1GCC\s0
+driver to link \fIlibtsan\fR statically, without necessarily linking
+other libraries statically.
.IP "\fB\-static\-libstdc++\fR" 4
.IX Item "-static-libstdc++"
-When the \fBg++\fR program is used to link a \*(C+ program, it will
-normally automatically link against \fBlibstdc++\fR. If
+When the \fBg++\fR program is used to link a \*(C+ program, it
+normally automatically links against \fBlibstdc++\fR. If
\&\fIlibstdc++\fR is available as a shared library, and the
-\&\fB\-static\fR option is not used, then this will link against the
+\&\fB\-static\fR option is not used, then this links against the
shared version of \fIlibstdc++\fR. That is normally fine. However, it
is sometimes useful to freeze the version of \fIlibstdc++\fR used by
the program without going all the way to a fully static link. The
Pretend the symbol \fIsymbol\fR is undefined, to force linking of
library modules to define it. You can use \fB\-u\fR multiple times with
different symbols to force loading of additional library modules.
-.Sh "Options for Directory Search"
+.SS "Options for Directory Search"
.IX Subsection "Options for Directory Search"
These options specify directories to search for header files, for
libraries and for parts of the compiler:
.Sp
If a standard system include directory, or a directory specified with
\&\fB\-isystem\fR, is also specified with \fB\-I\fR, the \fB\-I\fR
-option will be ignored. The directory will still be searched but as a
+option is ignored. The directory is still searched but as a
system directory at its normal position in the system include chain.
This is to ensure that \s-1GCC\s0's procedure to fix buggy system headers and
-the ordering for the include_next directive are not inadvertently changed.
+the ordering for the \f(CW\*(C`include_next\*(C'\fR directive are not inadvertently changed.
If you really need to change the search order for system directories,
use the \fB\-nostdinc\fR and/or \fB\-isystem\fR options.
.IP "\fB\-iplugindir=\fR\fIdir\fR" 4
include files, and data files of the compiler itself.
.Sp
The compiler driver program runs one or more of the subprograms
-\&\fIcpp\fR, \fIcc1\fR, \fIas\fR and \fIld\fR. It tries
+\&\fBcpp\fR, \fBcc1\fR, \fBas\fR and \fBld\fR. It tries
\&\fIprefix\fR as a prefix for each program it tries to run, both with and
without \fImachine\fR\fB/\fR\fIversion\fR\fB/\fR.
.Sp
For each subprogram to be run, the compiler driver first tries the
\&\fB\-B\fR prefix, if any. If that name is not found, or if \fB\-B\fR
-was not specified, the driver tries two standard prefixes,
+is not specified, the driver tries two standard prefixes,
\&\fI/usr/lib/gcc/\fR and \fI/usr/local/lib/gcc/\fR. If neither of
those results in a file name that is found, the unmodified program
name is searched for using the directories specified in your
\&\fB\s-1PATH\s0\fR environment variable.
.Sp
-The compiler will check to see if the path provided by the \fB\-B\fR
-refers to a directory, and if necessary it will add a directory
+The compiler checks to see if the path provided by the \fB\-B\fR
+refers to a directory, and if necessary it adds a directory
separator character at the end of the path.
.Sp
\&\fB\-B\fR prefixes that effectively specify directory names also apply
.Sp
As a special kludge, if the path provided by \fB\-B\fR is
\&\fI[dir/]stage\fIN\fI/\fR, where \fIN\fR is a number in the range 0 to
-9, then it will be replaced by \fI[dir/]include\fR. This is to help
+9, then it is replaced by \fI[dir/]include\fR. This is to help
with boot-strapping the compiler.
.IP "\fB\-specs=\fR\fIfile\fR" 4
.IX Item "-specs=file"
Process \fIfile\fR after the compiler reads in the standard \fIspecs\fR
-file, in order to override the defaults which the \fIgcc\fR driver
-program uses when determining what switches to pass to \fIcc1\fR,
-\&\fIcc1plus\fR, \fIas\fR, \fIld\fR, etc. More than one
+file, in order to override the defaults which the \fBgcc\fR driver
+program uses when determining what switches to pass to \fBcc1\fR,
+\&\fBcc1plus\fR, \fBas\fR, \fBld\fR, etc. More than one
\&\fB\-specs=\fR\fIfile\fR can be specified on the command line, and they
are processed in order, from left to right.
.IP "\fB\-\-sysroot=\fR\fIdir\fR" 4
.IX Item "--sysroot=dir"
Use \fIdir\fR as the logical root directory for headers and libraries.
-For example, if the compiler would normally search for headers in
-\&\fI/usr/include\fR and libraries in \fI/usr/lib\fR, it will instead
-search \fI\fIdir\fI/usr/include\fR and \fI\fIdir\fI/usr/lib\fR.
+For example, if the compiler normally searches for headers in
+\&\fI/usr/include\fR and libraries in \fI/usr/lib\fR, it instead
+searches \fI\fIdir\fI/usr/include\fR and \fI\fIdir\fI/usr/lib\fR.
.Sp
If you use both this option and the \fB\-isysroot\fR option, then
-the \fB\-\-sysroot\fR option will apply to libraries, but the
-\&\fB\-isysroot\fR option will apply to header files.
+the \fB\-\-sysroot\fR option applies to libraries, but the
+\&\fB\-isysroot\fR option applies to header files.
.Sp
The \s-1GNU\s0 linker (beginning with version 2.16) has the necessary support
for this option. If your linker does not support this option, the
-header file aspect of \fB\-\-sysroot\fR will still work, but the
-library aspect will not.
+header file aspect of \fB\-\-sysroot\fR still works, but the
+library aspect does not.
+.IP "\fB\-\-no\-sysroot\-suffix\fR" 4
+.IX Item "--no-sysroot-suffix"
+For some targets, a suffix is added to the root directory specified
+with \fB\-\-sysroot\fR, depending on the other options used, so that
+headers may for example be found in
+\&\fI\fIdir\fI/\fIsuffix\fI/usr/include\fR instead of
+\&\fI\fIdir\fI/usr/include\fR. This option disables the addition of
+such a suffix.
.IP "\fB\-I\-\fR" 4
.IX Item "-I-"
This option has been deprecated. Please use \fB\-iquote\fR instead for
directory (where the current input file came from) as the first search
directory for \fB#include "\fR\fIfile\fR\fB"\fR. There is no way to
override this effect of \fB\-I\-\fR. With \fB\-I.\fR you can specify
-searching the directory that was current when the compiler was
+searching the directory that is current when the compiler is
invoked. That is not exactly the same as what the preprocessor does
by default, but it is often satisfactory.
.Sp
\&\fB\-I\-\fR does not inhibit the use of the standard system directories
for header files. Thus, \fB\-I\-\fR and \fB\-nostdinc\fR are
independent.
-.Sh "Specifying Target Machine and Compiler Version"
+.SS "Specifying Target Machine and Compiler Version"
.IX Subsection "Specifying Target Machine and Compiler Version"
The usual way to run \s-1GCC\s0 is to run the executable called \fBgcc\fR, or
\&\fImachine\fR\fB\-gcc\fR when cross-compiling, or
\&\fImachine\fR\fB\-gcc\-\fR\fIversion\fR to run a version other than the
one that was installed last.
-.Sh "Hardware Models and Configurations"
+.SS "Hardware Models and Configurations"
.IX Subsection "Hardware Models and Configurations"
Each target machine types can have its own
special options, starting with \fB\-m\fR, to choose among various
options, usually for compatibility with other compilers on the same
platform.
.PP
+\fIAArch64 Options\fR
+.IX Subsection "AArch64 Options"
+.PP
+These options are defined for AArch64 implementations:
+.IP "\fB\-mbig\-endian\fR" 4
+.IX Item "-mbig-endian"
+Generate big-endian code. This is the default when \s-1GCC\s0 is configured for an
+\&\fBaarch64_be\-*\-*\fR target.
+.IP "\fB\-mgeneral\-regs\-only\fR" 4
+.IX Item "-mgeneral-regs-only"
+Generate code which uses only the general registers.
+.IP "\fB\-mlittle\-endian\fR" 4
+.IX Item "-mlittle-endian"
+Generate little-endian code. This is the default when \s-1GCC\s0 is configured for an
+\&\fBaarch64\-*\-*\fR but not an \fBaarch64_be\-*\-*\fR target.
+.IP "\fB\-mcmodel=tiny\fR" 4
+.IX Item "-mcmodel=tiny"
+Generate code for the tiny code model. The program and its statically defined
+symbols must be within 1GB of each other. Pointers are 64 bits. Programs can
+be statically or dynamically linked. This model is not fully implemented and
+mostly treated as \fBsmall\fR.
+.IP "\fB\-mcmodel=small\fR" 4
+.IX Item "-mcmodel=small"
+Generate code for the small code model. The program and its statically defined
+symbols must be within 4GB of each other. Pointers are 64 bits. Programs can
+be statically or dynamically linked. This is the default code model.
+.IP "\fB\-mcmodel=large\fR" 4
+.IX Item "-mcmodel=large"
+Generate code for the large code model. This makes no assumptions about
+addresses and sizes of sections. Pointers are 64 bits. Programs can be
+statically linked only.
+.IP "\fB\-mstrict\-align\fR" 4
+.IX Item "-mstrict-align"
+Do not assume that unaligned memory references will be handled by the system.
+.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4
+.IX Item "-momit-leaf-frame-pointer"
+.PD 0
+.IP "\fB\-mno\-omit\-leaf\-frame\-pointer\fR" 4
+.IX Item "-mno-omit-leaf-frame-pointer"
+.PD
+Omit or keep the frame pointer in leaf functions. The former behaviour is the
+default.
+.IP "\fB\-mtls\-dialect=desc\fR" 4
+.IX Item "-mtls-dialect=desc"
+Use \s-1TLS\s0 descriptors as the thread-local storage mechanism for dynamic accesses
+of \s-1TLS\s0 variables. This is the default.
+.IP "\fB\-mtls\-dialect=traditional\fR" 4
+.IX Item "-mtls-dialect=traditional"
+Use traditional \s-1TLS\s0 as the thread-local storage mechanism for dynamic accesses
+of \s-1TLS\s0 variables.
+.IP "\fB\-march=\fR\fIname\fR" 4
+.IX Item "-march=name"
+Specify the name of the target architecture, optionally suffixed by one or
+more feature modifiers. This option has the form
+\&\fB\-march=\fR\fIarch\fR{\fB+\fR[\fBno\fR]\fIfeature\fR}*, where the
+only value for \fIarch\fR is \fBarmv8\-a\fR. The possible values for
+\&\fIfeature\fR are documented in the sub-section below.
+.Sp
+Where conflicting feature modifiers are specified, the right-most feature is
+used.
+.Sp
+\&\s-1GCC\s0 uses this name to determine what kind of instructions it can emit when
+generating assembly code. This option can be used in conjunction with or
+instead of the \fB\-mcpu=\fR option.
+.IP "\fB\-mcpu=\fR\fIname\fR" 4
+.IX Item "-mcpu=name"
+Specify the name of the target processor, optionally suffixed by one or more
+feature modifiers. This option has the form
+\&\fB\-mcpu=\fR\fIcpu\fR{\fB+\fR[\fBno\fR]\fIfeature\fR}*, where the
+possible values for \fIcpu\fR are \fBgeneric\fR, \fBlarge\fR. The
+possible values for \fIfeature\fR are documented in the sub-section
+below.
+.Sp
+Where conflicting feature modifiers are specified, the right-most feature is
+used.
+.Sp
+\&\s-1GCC\s0 uses this name to determine what kind of instructions it can emit when
+generating assembly code.
+.IP "\fB\-mtune=\fR\fIname\fR" 4
+.IX Item "-mtune=name"
+Specify the name of the processor to tune the performance for. The code will
+be tuned as if the target processor were of the type specified in this option,
+but still using instructions compatible with the target processor specified
+by a \fB\-mcpu=\fR option. This option cannot be suffixed by feature
+modifiers.
+.PP
+\fB\-march\fR and \fB\-mcpu\fR feature modifiers
+.IX Subsection "-march and -mcpu feature modifiers"
+.PP
+Feature modifiers used with \fB\-march\fR and \fB\-mcpu\fR can be one
+the following:
+.IP "\fBcrypto\fR" 4
+.IX Item "crypto"
+Enable Crypto extension. This implies Advanced \s-1SIMD\s0 is enabled.
+.IP "\fBfp\fR" 4
+.IX Item "fp"
+Enable floating-point instructions.
+.IP "\fBsimd\fR" 4
+.IX Item "simd"
+Enable Advanced \s-1SIMD\s0 instructions. This implies floating-point instructions
+are enabled. This is the default for all current possible values for options
+\&\fB\-march\fR and \fB\-mcpu=\fR.
+.PP
\fIAdapteva Epiphany Options\fR
.IX Subsection "Adapteva Epiphany Options"
.PP
.IP "\fB\-mprefer\-short\-insn\-regs\fR" 4
.IX Item "-mprefer-short-insn-regs"
Preferrentially allocate registers that allow short instruction generation.
-This can result in increasesd instruction count, so if this reduces or
-increases code size might vary from case to case.
+This can result in increased instruction count, so this may either reduce or
+increase overall code size.
.IP "\fB\-mbranch\-cost=\fR\fInum\fR" 4
.IX Item "-mbranch-cost=num"
Set the cost of branches to roughly \fInum\fR \*(L"simple\*(R" instructions.
Enable the generation of conditional moves.
.IP "\fB\-mnops=\fR\fInum\fR" 4
.IX Item "-mnops=num"
-Emit \fInum\fR nops before every other generated instruction.
+Emit \fInum\fR NOPs before every other generated instruction.
.IP "\fB\-mno\-soft\-cmpsf\fR" 4
.IX Item "-mno-soft-cmpsf"
-For single-precision floating-point comparisons, emit an fsub instruction
+For single-precision floating-point comparisons, emit an \f(CW\*(C`fsub\*(C'\fR instruction
and test the flags. This is faster than a software comparison, but can
get incorrect results in the presence of NaNs, or when two different small
numbers are compared such that their difference is calculated as zero.
.IP "\fB\-mstack\-offset=\fR\fInum\fR" 4
.IX Item "-mstack-offset=num"
Set the offset between the top of the stack and the stack pointer.
-E.g., a value of 8 means that the eight bytes in the range sp+0...sp+7
+E.g., a value of 8 means that the eight bytes in the range \f(CW\*(C`sp+0...sp+7\*(C'\fR
can be used by leaf functions without stack allocation.
Values other than \fB8\fR or \fB16\fR are untested and unlikely to work.
-Note also that this option changes the \s-1ABI\s0, compiling a program with a
+Note also that this option changes the \s-1ABI\s0; compiling a program with a
different stack offset than the libraries have been compiled with
-will generally not work.
+generally does not work.
This option can be useful if you want to evaluate if a different stack
offset would give you better code, but to actually use a different stack
offset to build working programs, it is recommended to configure the
.IP "\fB\-mlong\-calls\fR" 4
.IX Item "-mlong-calls"
If not otherwise specified by an attribute, assume all calls might be beyond
-the offset range of the b / bl instructions, and therefore load the
+the offset range of the \f(CW\*(C`b\*(C'\fR / \f(CW\*(C`bl\*(C'\fR instructions, and therefore load the
function address into a register before performing a (otherwise direct) call.
This is the default.
.IP "\fB\-mshort\-calls\fR" 4
.IX Item "-mshort-calls"
If not otherwise specified by an attribute, assume all direct calls are
-in the range of the b / bl instructions, so use these instructions
+in the range of the \f(CW\*(C`b\*(C'\fR / \f(CW\*(C`bl\*(C'\fR instructions, so use these instructions
for direct calls. The default is \fB\-mlong\-calls\fR.
.IP "\fB\-msmall16\fR" 4
.IX Item "-msmall16"
The maximum alignment for \s-1SIMD\s0 vector mode types.
\&\fInum\fR may be 4 or 8. The default is 8.
Note that this is an \s-1ABI\s0 change, even though many library function
-interfaces will be unaffected, if they don't use \s-1SIMD\s0 vector modes
-in places where they affect size and/or alignment of relevant types.
+interfaces are unaffected if they don't use \s-1SIMD\s0 vector modes
+in places that affect size and/or alignment of relevant types.
.IP "\fB\-msplit\-vecmove\-early\fR" 4
.IX Item "-msplit-vecmove-early"
Split vector moves into single word moves before reload. In theory this
-could give better register allocation, but so far the reverse seems to be
+can give better register allocation, but so far the reverse seems to be
generally the case.
.IP "\fB\-m1reg\-\fR\fIreg\fR" 4
.IX Item "-m1reg-reg"
Specify a register to hold the constant \-1, which makes loading small negative
constants and certain bitmasks faster.
-Allowable values for reg are r43 and r63, which specify to use that register
-as a fixed register, and none, which means that no register is used for this
+Allowable values for \fIreg\fR are \fBr43\fR and \fBr63\fR,
+which specify use of that register as a fixed register,
+and \fBnone\fR, which means that no register is used for this
purpose. The default is \fB\-m1reg\-none\fR.
.PP
\fI\s-1ARM\s0 Options\fR
Generate a stack frame that is compliant with the \s-1ARM\s0 Procedure Call
Standard for all functions, even if this is not strictly necessary for
correct execution of the code. Specifying \fB\-fomit\-frame\-pointer\fR
-with this option will cause the stack frames not to be generated for
+with this option causes the stack frames not to be generated for
leaf functions. The default is \fB\-mno\-apcs\-frame\fR.
.IP "\fB\-mapcs\fR" 4
.IX Item "-mapcs"
.IX Item "-mno-sched-prolog"
Prevent the reordering of instructions in the function prologue, or the
merging of those instruction with the instructions in the function's
-body. This means that all functions will start with a recognizable set
+body. This means that all functions start with a recognizable set
of instructions (or in fact one of a choice from a small set of
different function prologues), and this information can be used to
-locate the start if functions inside an executable piece of code. The
+locate the start of functions inside an executable piece of code. The
default is \fB\-msched\-prolog\fR.
.IP "\fB\-mfloat\-abi=\fR\fIname\fR" 4
.IX Item "-mfloat-abi=name"
\&\fBcortex\-m4\fR, \fBcortex\-m3\fR,
\&\fBcortex\-m1\fR,
\&\fBcortex\-m0\fR,
+\&\fBcortex\-m0plus\fR,
+\&\fBmarvell\-pj4\fR,
\&\fBxscale\fR, \fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR,
\&\fBfa526\fR, \fBfa626\fR,
\&\fBfa606te\fR, \fBfa626te\fR, \fBfmp626\fR, \fBfa726te\fR.
instead of specifying the actual target processor type, and hence
restricting which instructions can be used, it specifies that \s-1GCC\s0 should
tune the performance of the code as if the target were of the type
-specified in this option, but still choosing the instructions that it
-will generate based on the \s-1CPU\s0 specified by a \fB\-mcpu=\fR option.
+specified in this option, but still choosing the instructions it
+generates based on the \s-1CPU\s0 specified by a \fB\-mcpu=\fR option.
For some \s-1ARM\s0 implementations better performance can be obtained by using
this option.
.Sp
\&\fBarmv6\fR, \fBarmv6j\fR,
\&\fBarmv6t2\fR, \fBarmv6z\fR, \fBarmv6zk\fR, \fBarmv6\-m\fR,
\&\fBarmv7\fR, \fBarmv7\-a\fR, \fBarmv7\-r\fR, \fBarmv7\-m\fR,
+\&\fBarmv8\-a\fR,
\&\fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR.
.Sp
\&\fB\-march=native\fR causes the compiler to auto-detect the architecture
unsuccessful the option has no effect.
.IP "\fB\-mfpu=\fR\fIname\fR" 4
.IX Item "-mfpu=name"
-.PD 0
-.IP "\fB\-mfpe=\fR\fInumber\fR" 4
-.IX Item "-mfpe=number"
-.IP "\fB\-mfp=\fR\fInumber\fR" 4
-.IX Item "-mfp=number"
-.PD
This specifies what floating-point hardware (or hardware emulation) is
-available on the target. Permissible names are: \fBfpa\fR, \fBfpe2\fR,
-\&\fBfpe3\fR, \fBmaverick\fR, \fBvfp\fR, \fBvfpv3\fR, \fBvfpv3\-fp16\fR,
-\&\fBvfpv3\-d16\fR, \fBvfpv3\-d16\-fp16\fR, \fBvfpv3xd\fR, \fBvfpv3xd\-fp16\fR,
-\&\fBneon\fR, \fBneon\-fp16\fR, \fBvfpv4\fR, \fBvfpv4\-d16\fR,
-\&\fBfpv4\-sp\-d16\fR and \fBneon\-vfpv4\fR.
-\&\fB\-mfp\fR and \fB\-mfpe\fR are synonyms for
-\&\fB\-mfpu\fR=\fBfpe\fR\fInumber\fR, for compatibility with older versions
-of \s-1GCC\s0.
+available on the target. Permissible names are: \fBvfp\fR, \fBvfpv3\fR,
+\&\fBvfpv3\-fp16\fR, \fBvfpv3\-d16\fR, \fBvfpv3\-d16\-fp16\fR, \fBvfpv3xd\fR,
+\&\fBvfpv3xd\-fp16\fR, \fBneon\fR, \fBneon\-fp16\fR, \fBvfpv4\fR,
+\&\fBvfpv4\-d16\fR, \fBfpv4\-sp\-d16\fR, \fBneon\-vfpv4\fR,
+\&\fBfp\-armv8\fR, \fBneon\-fp\-armv8\fR, and \fBcrypto\-neon\-fp\-armv8\fR.
.Sp
If \fB\-msoft\-float\fR is specified this specifies the format of
floating-point values.
.Sp
If the selected floating-point hardware includes the \s-1NEON\s0 extension
(e.g. \fB\-mfpu\fR=\fBneon\fR), note that floating-point
-operations will not be used by \s-1GCC\s0's auto-vectorization pass unless
+operations are not generated by \s-1GCC\s0's auto-vectorization pass unless
\&\fB\-funsafe\-math\-optimizations\fR is also specified. This is
because \s-1NEON\s0 hardware does not fully implement the \s-1IEEE\s0 754 standard for
floating-point arithmetic (in particular denormal values are treated as
defined.
.IP "\fB\-mstructure\-size\-boundary=\fR\fIn\fR" 4
.IX Item "-mstructure-size-boundary=n"
-The size of all structures and unions will be rounded up to a multiple
+The sizes of all structures and unions are rounded up to a multiple
of the number of bits set by this option. Permissible values are 8, 32
and 64. The default value varies for different toolchains. For the \s-1COFF\s0
targeted toolchain the default value is 8. A value of 64 is only allowed
if the underlying \s-1ABI\s0 supports it.
.Sp
-Specifying the larger number can produce faster, more efficient code, but
+Specifying a larger number can produce faster, more efficient code, but
can also increase the size of the program. Different values are potentially
incompatible. Code compiled with one value cannot necessarily expect to
work with code or libraries compiled with another value, if they exchange
.IP "\fB\-mabort\-on\-noreturn\fR" 4
.IX Item "-mabort-on-noreturn"
Generate a call to the function \f(CW\*(C`abort\*(C'\fR at the end of a
-\&\f(CW\*(C`noreturn\*(C'\fR function. It will be executed if the function tries to
+\&\f(CW\*(C`noreturn\*(C'\fR function. It is executed if the function tries to
return.
.IP "\fB\-mlong\-calls\fR" 4
.IX Item "-mlong-calls"
Tells the compiler to perform function calls by first loading the
address of the function into a register and then performing a subroutine
call on this register. This switch is needed if the target function
-will lie outside of the 64 megabyte addressing range of the offset based
+lies outside of the 64\-megabyte addressing range of the offset-based
version of subroutine call instruction.
.Sp
-Even if this switch is enabled, not all function calls will be turned
+Even if this switch is enabled, not all function calls are turned
into long calls. The heuristic is that static functions, functions
that have the \fBshort-call\fR attribute, functions that are inside
-the scope of a \fB#pragma no_long_calls\fR directive and functions whose
+the scope of a \fB#pragma no_long_calls\fR directive, and functions whose
definitions have already been compiled within the current compilation
-unit, will not be turned into long calls. The exception to this rule is
+unit are not turned into long calls. The exceptions to this rule are
that weak function definitions, functions with the \fBlong-call\fR
attribute or the \fBsection\fR attribute, and functions that are within
-the scope of a \fB#pragma long_calls\fR directive, will always be
+the scope of a \fB#pragma long_calls\fR directive are always
turned into long calls.
.Sp
This feature is not enabled by default. Specifying
-\&\fB\-mno\-long\-calls\fR will restore the default behavior, as will
+\&\fB\-mno\-long\-calls\fR restores the default behavior, as does
placing the function calls within the scope of a \fB#pragma
long_calls_off\fR directive. Note these switches have no effect on how
the compiler generates code to handle function calls via function
.IX Item "-mpic-register=reg"
Specify the register to be used for \s-1PIC\s0 addressing. The default is R10
unless stack-checking is enabled, when R9 is used.
-.IP "\fB\-mcirrus\-fix\-invalid\-insns\fR" 4
-.IX Item "-mcirrus-fix-invalid-insns"
-Insert NOPs into the instruction stream to in order to work around
-problems with invalid Maverick instruction combinations. This option
-is only valid if the \fB\-mcpu=ep9312\fR option has been used to
-enable generation of instructions for the Cirrus Maverick floating-point
-co-processor. This option is not enabled by default, since the
-problem is only present in older Maverick implementations. The default
-can be re-enabled by use of the \fB\-mno\-cirrus\-fix\-invalid\-insns\fR
-switch.
.IP "\fB\-mpoke\-function\-name\fR" 4
.IX Item "-mpoke-function-name"
Write the name of each function into the text section, directly
.IP "\fB\-mtls\-dialect=\fR\fIdialect\fR" 4
.IX Item "-mtls-dialect=dialect"
Specify the dialect to use for accessing thread local storage. Two
-dialects are supported \-\-\- \fBgnu\fR and \fBgnu2\fR. The
+\&\fIdialect\fRs are supported\-\-\-\fBgnu\fR and \fBgnu2\fR. The
\&\fBgnu\fR dialect selects the original \s-1GNU\s0 scheme for supporting
local and global dynamic \s-1TLS\s0 models. The \fBgnu2\fR dialect
selects the \s-1GNU\s0 descriptor scheme, which provides better performance
.PP
\fI\s-1AVR\s0 Options\fR
.IX Subsection "AVR Options"
+.PP
+These options are defined for \s-1AVR\s0 implementations:
.IP "\fB\-mmcu=\fR\fImcu\fR" 4
.IX Item "-mmcu=mcu"
Specify Atmel \s-1AVR\s0 instruction set architectures (\s-1ISA\s0) or \s-1MCU\s0 type.
.el .IP "\f(CWavr2\fR" 4
.IX Item "avr2"
\&\*(L"Classic\*(R" devices with up to 8@tie{}KiB of program memory.
-\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`attiny22\*(C'\fR, \f(CW\*(C`attiny26\*(C'\fR, \f(CW\*(C`at90c8534\*(C'\fR,
-\&\f(CW\*(C`at90s2313\*(C'\fR, \f(CW\*(C`at90s2323\*(C'\fR, \f(CW\*(C`at90s2333\*(C'\fR,
-\&\f(CW\*(C`at90s2343\*(C'\fR, \f(CW\*(C`at90s4414\*(C'\fR, \f(CW\*(C`at90s4433\*(C'\fR,
-\&\f(CW\*(C`at90s4434\*(C'\fR, \f(CW\*(C`at90s8515\*(C'\fR, \f(CW\*(C`at90s8535\*(C'\fR.
+\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`attiny22\*(C'\fR, \f(CW\*(C`attiny26\*(C'\fR, \f(CW\*(C`at90c8534\*(C'\fR, \f(CW\*(C`at90s2313\*(C'\fR, \f(CW\*(C`at90s2323\*(C'\fR, \f(CW\*(C`at90s2333\*(C'\fR, \f(CW\*(C`at90s2343\*(C'\fR, \f(CW\*(C`at90s4414\*(C'\fR, \f(CW\*(C`at90s4433\*(C'\fR, \f(CW\*(C`at90s4434\*(C'\fR, \f(CW\*(C`at90s8515\*(C'\fR, \f(CW\*(C`at90s8535\*(C'\fR.
.ie n .IP """avr25""" 4
.el .IP "\f(CWavr25\fR" 4
.IX Item "avr25"
-\&\*(L"Classic\*(R" devices with up to 8@tie{}KiB of program memory and with
-the \f(CW\*(C`MOVW\*(C'\fR instruction.
-\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`ata6289\*(C'\fR, \f(CW\*(C`attiny13\*(C'\fR, \f(CW\*(C`attiny13a\*(C'\fR,
-\&\f(CW\*(C`attiny2313\*(C'\fR, \f(CW\*(C`attiny2313a\*(C'\fR, \f(CW\*(C`attiny24\*(C'\fR,
-\&\f(CW\*(C`attiny24a\*(C'\fR, \f(CW\*(C`attiny25\*(C'\fR, \f(CW\*(C`attiny261\*(C'\fR,
-\&\f(CW\*(C`attiny261a\*(C'\fR, \f(CW\*(C`attiny43u\*(C'\fR, \f(CW\*(C`attiny4313\*(C'\fR,
-\&\f(CW\*(C`attiny44\*(C'\fR, \f(CW\*(C`attiny44a\*(C'\fR, \f(CW\*(C`attiny45\*(C'\fR, \f(CW\*(C`attiny461\*(C'\fR,
-\&\f(CW\*(C`attiny461a\*(C'\fR, \f(CW\*(C`attiny48\*(C'\fR, \f(CW\*(C`attiny84\*(C'\fR, \f(CW\*(C`attiny84a\*(C'\fR,
-\&\f(CW\*(C`attiny85\*(C'\fR, \f(CW\*(C`attiny861\*(C'\fR, \f(CW\*(C`attiny861a\*(C'\fR, \f(CW\*(C`attiny87\*(C'\fR,
-\&\f(CW\*(C`attiny88\*(C'\fR, \f(CW\*(C`at86rf401\*(C'\fR.
+\&\*(L"Classic\*(R" devices with up to 8@tie{}KiB of program memory and with the \f(CW\*(C`MOVW\*(C'\fR instruction.
+\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`ata5272\*(C'\fR, \f(CW\*(C`ata6289\*(C'\fR, \f(CW\*(C`attiny13\*(C'\fR, \f(CW\*(C`attiny13a\*(C'\fR, \f(CW\*(C`attiny2313\*(C'\fR, \f(CW\*(C`attiny2313a\*(C'\fR, \f(CW\*(C`attiny24\*(C'\fR, \f(CW\*(C`attiny24a\*(C'\fR, \f(CW\*(C`attiny25\*(C'\fR, \f(CW\*(C`attiny261\*(C'\fR, \f(CW\*(C`attiny261a\*(C'\fR, \f(CW\*(C`attiny43u\*(C'\fR, \f(CW\*(C`attiny4313\*(C'\fR, \f(CW\*(C`attiny44\*(C'\fR, \f(CW\*(C`attiny44a\*(C'\fR, \f(CW\*(C`attiny45\*(C'\fR, \f(CW\*(C`attiny461\*(C'\fR, \f(CW\*(C`attiny461a\*(C'\fR, \f(CW\*(C`attiny48\*(C'\fR, \f(CW\*(C`attiny84\*(C'\fR, \f(CW\*(C`attiny84a\*(C'\fR, \f(CW\*(C`attiny85\*(C'\fR, \f(CW\*(C`attiny861\*(C'\fR, \f(CW\*(C`attiny861a\*(C'\fR, \f(CW\*(C`attiny87\*(C'\fR, \f(CW\*(C`attiny88\*(C'\fR, \f(CW\*(C`at86rf401\*(C'\fR.
.ie n .IP """avr3""" 4
.el .IP "\f(CWavr3\fR" 4
.IX Item "avr3"
.ie n .IP """avr35""" 4
.el .IP "\f(CWavr35\fR" 4
.IX Item "avr35"
-\&\*(L"Classic\*(R" devices with 16@tie{}KiB up to 64@tie{}KiB of program
-memory and with the \f(CW\*(C`MOVW\*(C'\fR instruction.
-\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atmega16u2\*(C'\fR, \f(CW\*(C`atmega32u2\*(C'\fR,
-\&\f(CW\*(C`atmega8u2\*(C'\fR, \f(CW\*(C`attiny167\*(C'\fR, \f(CW\*(C`at90usb162\*(C'\fR,
-\&\f(CW\*(C`at90usb82\*(C'\fR.
+\&\*(L"Classic\*(R" devices with 16@tie{}KiB up to 64@tie{}KiB of program memory and with the \f(CW\*(C`MOVW\*(C'\fR instruction.
+\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`ata5505\*(C'\fR, \f(CW\*(C`atmega16u2\*(C'\fR, \f(CW\*(C`atmega32u2\*(C'\fR, \f(CW\*(C`atmega8u2\*(C'\fR, \f(CW\*(C`attiny1634\*(C'\fR, \f(CW\*(C`attiny167\*(C'\fR, \f(CW\*(C`at90usb162\*(C'\fR, \f(CW\*(C`at90usb82\*(C'\fR.
.ie n .IP """avr4""" 4
.el .IP "\f(CWavr4\fR" 4
.IX Item "avr4"
\&\*(L"Enhanced\*(R" devices with up to 8@tie{}KiB of program memory.
-\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atmega48\*(C'\fR, \f(CW\*(C`atmega48a\*(C'\fR,
-\&\f(CW\*(C`atmega48p\*(C'\fR, \f(CW\*(C`atmega8\*(C'\fR, \f(CW\*(C`atmega8hva\*(C'\fR,
-\&\f(CW\*(C`atmega8515\*(C'\fR, \f(CW\*(C`atmega8535\*(C'\fR, \f(CW\*(C`atmega88\*(C'\fR,
-\&\f(CW\*(C`atmega88a\*(C'\fR, \f(CW\*(C`atmega88p\*(C'\fR, \f(CW\*(C`atmega88pa\*(C'\fR,
-\&\f(CW\*(C`at90pwm1\*(C'\fR, \f(CW\*(C`at90pwm2\*(C'\fR, \f(CW\*(C`at90pwm2b\*(C'\fR, \f(CW\*(C`at90pwm3\*(C'\fR,
-\&\f(CW\*(C`at90pwm3b\*(C'\fR, \f(CW\*(C`at90pwm81\*(C'\fR.
+\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`ata6285\*(C'\fR, \f(CW\*(C`ata6286\*(C'\fR, \f(CW\*(C`atmega48\*(C'\fR, \f(CW\*(C`atmega48a\*(C'\fR, \f(CW\*(C`atmega48p\*(C'\fR, \f(CW\*(C`atmega48pa\*(C'\fR, \f(CW\*(C`atmega8\*(C'\fR, \f(CW\*(C`atmega8a\*(C'\fR, \f(CW\*(C`atmega8hva\*(C'\fR, \f(CW\*(C`atmega8515\*(C'\fR, \f(CW\*(C`atmega8535\*(C'\fR, \f(CW\*(C`atmega88\*(C'\fR, \f(CW\*(C`atmega88a\*(C'\fR, \f(CW\*(C`atmega88p\*(C'\fR, \f(CW\*(C`atmega88pa\*(C'\fR, \f(CW\*(C`at90pwm1\*(C'\fR, \f(CW\*(C`at90pwm2\*(C'\fR, \f(CW\*(C`at90pwm2b\*(C'\fR, \f(CW\*(C`at90pwm3\*(C'\fR, \f(CW\*(C`at90pwm3b\*(C'\fR, \f(CW\*(C`at90pwm81\*(C'\fR.
.ie n .IP """avr5""" 4
.el .IP "\f(CWavr5\fR" 4
.IX Item "avr5"
\&\*(L"Enhanced\*(R" devices with 16@tie{}KiB up to 64@tie{}KiB of program memory.
-\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atmega16\*(C'\fR, \f(CW\*(C`atmega16a\*(C'\fR,
-\&\f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR,
-\&\f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega161\*(C'\fR,
-\&\f(CW\*(C`atmega162\*(C'\fR, \f(CW\*(C`atmega163\*(C'\fR, \f(CW\*(C`atmega164a\*(C'\fR,
-\&\f(CW\*(C`atmega164p\*(C'\fR, \f(CW\*(C`atmega165\*(C'\fR, \f(CW\*(C`atmega165a\*(C'\fR,
-\&\f(CW\*(C`atmega165p\*(C'\fR, \f(CW\*(C`atmega168\*(C'\fR, \f(CW\*(C`atmega168a\*(C'\fR,
-\&\f(CW\*(C`atmega168p\*(C'\fR, \f(CW\*(C`atmega169\*(C'\fR, \f(CW\*(C`atmega169a\*(C'\fR,
-\&\f(CW\*(C`atmega169p\*(C'\fR, \f(CW\*(C`atmega169pa\*(C'\fR, \f(CW\*(C`atmega32\*(C'\fR,
-\&\f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR,
-\&\f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega323\*(C'\fR,
-\&\f(CW\*(C`atmega324a\*(C'\fR, \f(CW\*(C`atmega324p\*(C'\fR, \f(CW\*(C`atmega324pa\*(C'\fR,
-\&\f(CW\*(C`atmega325\*(C'\fR, \f(CW\*(C`atmega325a\*(C'\fR, \f(CW\*(C`atmega325p\*(C'\fR,
-\&\f(CW\*(C`atmega3250\*(C'\fR, \f(CW\*(C`atmega3250a\*(C'\fR, \f(CW\*(C`atmega3250p\*(C'\fR,
-\&\f(CW\*(C`atmega328\*(C'\fR, \f(CW\*(C`atmega328p\*(C'\fR, \f(CW\*(C`atmega329\*(C'\fR,
-\&\f(CW\*(C`atmega329a\*(C'\fR, \f(CW\*(C`atmega329p\*(C'\fR, \f(CW\*(C`atmega329pa\*(C'\fR,
-\&\f(CW\*(C`atmega3290\*(C'\fR, \f(CW\*(C`atmega3290a\*(C'\fR, \f(CW\*(C`atmega3290p\*(C'\fR,
-\&\f(CW\*(C`atmega406\*(C'\fR, \f(CW\*(C`atmega64\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR,
-\&\f(CW\*(C`atmega64hve\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega640\*(C'\fR,
-\&\f(CW\*(C`atmega644\*(C'\fR, \f(CW\*(C`atmega644a\*(C'\fR, \f(CW\*(C`atmega644p\*(C'\fR,
-\&\f(CW\*(C`atmega644pa\*(C'\fR, \f(CW\*(C`atmega645\*(C'\fR, \f(CW\*(C`atmega645a\*(C'\fR,
-\&\f(CW\*(C`atmega645p\*(C'\fR, \f(CW\*(C`atmega6450\*(C'\fR, \f(CW\*(C`atmega6450a\*(C'\fR,
-\&\f(CW\*(C`atmega6450p\*(C'\fR, \f(CW\*(C`atmega649\*(C'\fR, \f(CW\*(C`atmega649a\*(C'\fR,
-\&\f(CW\*(C`atmega649p\*(C'\fR, \f(CW\*(C`atmega6490\*(C'\fR, \f(CW\*(C`at90can32\*(C'\fR,
-\&\f(CW\*(C`at90can64\*(C'\fR, \f(CW\*(C`at90pwm216\*(C'\fR, \f(CW\*(C`at90pwm316\*(C'\fR,
-\&\f(CW\*(C`at90scr100\*(C'\fR, \f(CW\*(C`at90usb646\*(C'\fR, \f(CW\*(C`at90usb647\*(C'\fR, \f(CW\*(C`at94k\*(C'\fR,
-\&\f(CW\*(C`m3000\*(C'\fR.
+\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`ata5790\*(C'\fR, \f(CW\*(C`ata5790n\*(C'\fR, \f(CW\*(C`ata5795\*(C'\fR, \f(CW\*(C`atmega16\*(C'\fR, \f(CW\*(C`atmega16a\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvbrevb\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega161\*(C'\fR, \f(CW\*(C`atmega162\*(C'\fR, \f(CW\*(C`atmega163\*(C'\fR, \f(CW\*(C`atmega164a\*(C'\fR, \f(CW\*(C`atmega164p\*(C'\fR, \f(CW\*(C`atmega164pa\*(C'\fR, \f(CW\*(C`atmega165\*(C'\fR, \f(CW\*(C`atmega165a\*(C'\fR, \f(CW\*(C`atmega165p\*(C'\fR, \f(CW\*(C`atmega165pa\*(C'\fR, \f(CW\*(C`atmega168\*(C'\fR, \f(CW\*(C`atmega168a\*(C'\fR, \f(CW\*(C`atmega168p\*(C'\fR, \f(CW\*(C`atmega168pa\*(C'\fR, \f(CW\*(C`atmega169\*(C'\fR, \f(CW\*(C`atmega169a\*(C'\fR, \f(CW\*(C`atmega169p\*(C'\fR, \f(CW\*(C`atmega169pa\*(C'\fR, \f(CW\*(C`atmega26hvg\*(C'\fR, \f(CW\*(C`atmega32\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvbrevb\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega323\*(C'\fR, \f(CW\*(C`atmega324a\*(C'\fR, \f(CW\*(C`atmega324p\*(C'\fR, \f(CW\*(C`atmega324pa\*(C'\fR, \f(CW\*(C`atmega325\*(C'\fR, \f(CW\*(C`atmega325a\*(C'\fR, \f(CW\*(C`atmega325p\*(C'\fR, \f(CW\*(C`atmega3250\*(C'\fR, \f(CW\*(C`atmega3250a\*(C'\fR, \f(CW\*(C`atmega3250p\*(C'\fR, \f(CW\*(C`atmega3250pa\*(C'\fR, \f(CW\*(C`atmega328\*(C'\fR, \f(CW\*(C`atmega328p\*(C'\fR, \f(CW\*(C`atmega329\*(C'\fR, \f(CW\*(C`atmega329a\*(C'\fR, \f(CW\*(C`atmega329p\*(C'\fR, \f(CW\*(C`atmega329pa\*(C'\fR, \f(CW\*(C`atmega3290\*(C'\fR, \f(CW\*(C`atmega3290a\*(C'\fR, \f(CW\*(C`atmega3290p\*(C'\fR, \f(CW\*(C`atmega3290pa\*(C'\fR, \f(CW\*(C`atmega406\*(C'\fR, \f(CW\*(C`atmega48hvf\*(C'\fR, \f(CW\*(C`atmega64\*(C'\fR, \f(CW\*(C`atmega64a\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64hve\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64rfa2\*(C'\fR, \f(CW\*(C`atmega64rfr2\*(C'\fR, \f(CW\*(C`atmega640\*(C'\fR, \f(CW\*(C`atmega644\*(C'\fR, \f(CW\*(C`atmega644a\*(C'\fR, \f(CW\*(C`atmega644p\*(C'\fR, \f(CW\*(C`atmega644pa\*(C'\fR, \f(CW\*(C`atmega645\*(C'\fR, \f(CW\*(C`atmega645a\*(C'\fR, \f(CW\*(C`atmega645p\*(C'\fR, \f(CW\*(C`atmega6450\*(C'\fR, \f(CW\*(C`atmega6450a\*(C'\fR, \f(CW\*(C`atmega6450p\*(C'\fR, \f(CW\*(C`atmega649\*(C'\fR, \f(CW\*(C`atmega649a\*(C'\fR, \f(CW\*(C`atmega649p\*(C'\fR, \f(CW\*(C`atmega6490\*(C'\fR, \f(CW\*(C`atmega6490a\*(C'\fR, \f(CW\*(C`atmega6490p\*(C'\fR, \f(CW\*(C`at90can32\*(C'\fR, \f(CW\*(C`at90can64\*(C'\fR, \f(CW\*(C`at90pwm161\*(C'\fR, \f(CW\*(C`at90pwm216\*(C'\fR, \f(CW\*(C`at90pwm316\*(C'\fR, \f(CW\*(C`at90scr100\*(C'\fR, \f(CW\*(C`at90usb646\*(C'\fR, \f(CW\*(C`at90usb647\*(C'\fR, \f(CW\*(C`at94k\*(C'\fR, \f(CW\*(C`m3000\*(C'\fR.
.ie n .IP """avr51""" 4
.el .IP "\f(CWavr51\fR" 4
.IX Item "avr51"
\&\*(L"Enhanced\*(R" devices with 128@tie{}KiB of program memory.
-\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atmega128\*(C'\fR, \f(CW\*(C`atmega128rfa1\*(C'\fR,
-\&\f(CW\*(C`atmega1280\*(C'\fR, \f(CW\*(C`atmega1281\*(C'\fR, \f(CW\*(C`atmega1284p\*(C'\fR,
-\&\f(CW\*(C`at90can128\*(C'\fR, \f(CW\*(C`at90usb1286\*(C'\fR, \f(CW\*(C`at90usb1287\*(C'\fR.
+\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atmega128\*(C'\fR, \f(CW\*(C`atmega128a\*(C'\fR, \f(CW\*(C`atmega128rfa1\*(C'\fR, \f(CW\*(C`atmega1280\*(C'\fR, \f(CW\*(C`atmega1281\*(C'\fR, \f(CW\*(C`atmega1284\*(C'\fR, \f(CW\*(C`atmega1284p\*(C'\fR, \f(CW\*(C`at90can128\*(C'\fR, \f(CW\*(C`at90usb1286\*(C'\fR, \f(CW\*(C`at90usb1287\*(C'\fR.
.ie n .IP """avr6""" 4
.el .IP "\f(CWavr6\fR" 4
.IX Item "avr6"
-\&\*(L"Enhanced\*(R" devices with 3\-byte \s-1PC\s0, i.e. with more than
-128@tie{}KiB of program memory.
+\&\*(L"Enhanced\*(R" devices with 3\-byte \s-1PC\s0, i.e. with more than 128@tie{}KiB of program memory.
\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atmega2560\*(C'\fR, \f(CW\*(C`atmega2561\*(C'\fR.
.ie n .IP """avrxmega2""" 4
.el .IP "\f(CWavrxmega2\fR" 4
.IX Item "avrxmega2"
-\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 8@tie{}KiB and up to 64@tie{}KiB of
-program memory.
-\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega16a4\*(C'\fR, \f(CW\*(C`atxmega16d4\*(C'\fR,
-\&\f(CW\*(C`atxmega16x1\*(C'\fR, \f(CW\*(C`atxmega32a4\*(C'\fR, \f(CW\*(C`atxmega32d4\*(C'\fR,
-\&\f(CW\*(C`atxmega32x1\*(C'\fR.
+\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 8@tie{}KiB and up to 64@tie{}KiB of program memory.
+\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atmxt112sl\*(C'\fR, \f(CW\*(C`atmxt224\*(C'\fR, \f(CW\*(C`atmxt224e\*(C'\fR, \f(CW\*(C`atmxt336s\*(C'\fR, \f(CW\*(C`atxmega16a4\*(C'\fR, \f(CW\*(C`atxmega16a4u\*(C'\fR, \f(CW\*(C`atxmega16c4\*(C'\fR, \f(CW\*(C`atxmega16d4\*(C'\fR, \f(CW\*(C`atxmega16x1\*(C'\fR, \f(CW\*(C`atxmega32a4\*(C'\fR, \f(CW\*(C`atxmega32a4u\*(C'\fR, \f(CW\*(C`atxmega32c4\*(C'\fR, \f(CW\*(C`atxmega32d4\*(C'\fR, \f(CW\*(C`atxmega32e5\*(C'\fR, \f(CW\*(C`atxmega32x1\*(C'\fR.
.ie n .IP """avrxmega4""" 4
.el .IP "\f(CWavrxmega4\fR" 4
.IX Item "avrxmega4"
-\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 64@tie{}KiB and up to 128@tie{}KiB of
-program memory.
-\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega64a3\*(C'\fR, \f(CW\*(C`atxmega64d3\*(C'\fR.
+\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory.
+\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega64a3\*(C'\fR, \f(CW\*(C`atxmega64a3u\*(C'\fR, \f(CW\*(C`atxmega64a4u\*(C'\fR, \f(CW\*(C`atxmega64b1\*(C'\fR, \f(CW\*(C`atxmega64b3\*(C'\fR, \f(CW\*(C`atxmega64c3\*(C'\fR, \f(CW\*(C`atxmega64d3\*(C'\fR, \f(CW\*(C`atxmega64d4\*(C'\fR.
.ie n .IP """avrxmega5""" 4
.el .IP "\f(CWavrxmega5\fR" 4
.IX Item "avrxmega5"
-\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 64@tie{}KiB and up to 128@tie{}KiB of
-program memory and more than 64@tie{}KiB of \s-1RAM\s0.
+\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory and more than 64@tie{}KiB of \s-1RAM\s0.
\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega64a1\*(C'\fR, \f(CW\*(C`atxmega64a1u\*(C'\fR.
.ie n .IP """avrxmega6""" 4
.el .IP "\f(CWavrxmega6\fR" 4
.IX Item "avrxmega6"
\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 128@tie{}KiB of program memory.
-\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega128a3\*(C'\fR, \f(CW\*(C`atxmega128d3\*(C'\fR,
-\&\f(CW\*(C`atxmega192a3\*(C'\fR, \f(CW\*(C`atxmega192d3\*(C'\fR, \f(CW\*(C`atxmega256a3\*(C'\fR,
-\&\f(CW\*(C`atxmega256a3b\*(C'\fR, \f(CW\*(C`atxmega256a3bu\*(C'\fR, \f(CW\*(C`atxmega256d3\*(C'\fR.
+\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atmxt540s\*(C'\fR, \f(CW\*(C`atmxt540sreva\*(C'\fR, \f(CW\*(C`atxmega128a3\*(C'\fR, \f(CW\*(C`atxmega128a3u\*(C'\fR, \f(CW\*(C`atxmega128b1\*(C'\fR, \f(CW\*(C`atxmega128b3\*(C'\fR, \f(CW\*(C`atxmega128c3\*(C'\fR, \f(CW\*(C`atxmega128d3\*(C'\fR, \f(CW\*(C`atxmega128d4\*(C'\fR, \f(CW\*(C`atxmega192a3\*(C'\fR, \f(CW\*(C`atxmega192a3u\*(C'\fR, \f(CW\*(C`atxmega192c3\*(C'\fR, \f(CW\*(C`atxmega192d3\*(C'\fR, \f(CW\*(C`atxmega256a3\*(C'\fR, \f(CW\*(C`atxmega256a3b\*(C'\fR, \f(CW\*(C`atxmega256a3bu\*(C'\fR, \f(CW\*(C`atxmega256a3u\*(C'\fR, \f(CW\*(C`atxmega256c3\*(C'\fR, \f(CW\*(C`atxmega256d3\*(C'\fR, \f(CW\*(C`atxmega384c3\*(C'\fR, \f(CW\*(C`atxmega384d3\*(C'\fR.
.ie n .IP """avrxmega7""" 4
.el .IP "\f(CWavrxmega7\fR" 4
.IX Item "avrxmega7"
-\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 128@tie{}KiB of program memory and
-more than 64@tie{}KiB of \s-1RAM\s0.
-\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega128a1\*(C'\fR, \f(CW\*(C`atxmega128a1u\*(C'\fR.
+\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 128@tie{}KiB of program memory and more than 64@tie{}KiB of \s-1RAM\s0.
+\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega128a1\*(C'\fR, \f(CW\*(C`atxmega128a1u\*(C'\fR, \f(CW\*(C`atxmega128a4u\*(C'\fR.
.ie n .IP """avr1""" 4
.el .IP "\f(CWavr1\fR" 4
.IX Item "avr1"
-This \s-1ISA\s0 is implemented by the minimal \s-1AVR\s0 core and supported for
-assembler only.
-\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`attiny11\*(C'\fR, \f(CW\*(C`attiny12\*(C'\fR, \f(CW\*(C`attiny15\*(C'\fR,
-\&\f(CW\*(C`attiny28\*(C'\fR, \f(CW\*(C`at90s1200\*(C'\fR.
+This \s-1ISA\s0 is implemented by the minimal \s-1AVR\s0 core and supported for assembler only.
+\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`attiny11\*(C'\fR, \f(CW\*(C`attiny12\*(C'\fR, \f(CW\*(C`attiny15\*(C'\fR, \f(CW\*(C`attiny28\*(C'\fR, \f(CW\*(C`at90s1200\*(C'\fR.
.RE
.RS 4
.RE
.Sp
Relaxing must be turned on if linker stubs are needed, see the
section on \f(CW\*(C`EIND\*(C'\fR and linker stubs below.
-.IP "\fB\-mshort\-calls\fR" 4
-.IX Item "-mshort-calls"
-This option has been deprecated and will be removed in \s-1GCC\s0 4.8.
-See \f(CW\*(C`\-mrelax\*(C'\fR for a replacement.
-.Sp
-Use \f(CW\*(C`RCALL\*(C'\fR/\f(CW\*(C`RJMP\*(C'\fR instructions even on devices with
-16@tie{}KiB or more of program memory, i.e. on devices that
-have the \f(CW\*(C`CALL\*(C'\fR and \f(CW\*(C`JMP\*(C'\fR instructions.
.IP "\fB\-msp8\fR" 4
.IX Item "-msp8"
Treat the stack pointer register as an 8\-bit register,
.IP "\fB\-mtiny\-stack\fR" 4
.IX Item "-mtiny-stack"
Only change the lower 8@tie{}bits of the stack pointer.
+.IP "\fB\-Waddr\-space\-convert\fR" 4
+.IX Item "-Waddr-space-convert"
+Warn about conversions between address spaces in the case where the
+resulting address space is not contained in the incoming address space.
.PP
\f(CW\*(C`EIND\*(C'\fR and Devices with more than 128 Ki Bytes of Flash
.IX Subsection "EIND and Devices with more than 128 Ki Bytes of Flash"
.ie n .IP """_\|_AVR_XMEGA_\|_""" 4
.el .IP "\f(CW_\|_AVR_XMEGA_\|_\fR" 4
.IX Item "__AVR_XMEGA__"
-The device/architecture belongs to the \s-1XMEGA\s0 family of devices.
+The device / architecture belongs to the \s-1XMEGA\s0 family of devices.
.ie n .IP """_\|_AVR_HAVE_ELPM_\|_""" 4
.el .IP "\f(CW_\|_AVR_HAVE_ELPM_\|_\fR" 4
.IX Item "__AVR_HAVE_ELPM__"
.IX Item "__AVR_HAVE_JMP_CALL__"
The device has the \f(CW\*(C`JMP\*(C'\fR and \f(CW\*(C`CALL\*(C'\fR instructions.
This is the case for devices with at least 16@tie{}KiB of program
-memory and if \f(CW\*(C`\-mshort\-calls\*(C'\fR is not set.
+memory.
.ie n .IP """_\|_AVR_HAVE_EIJMP_EICALL_\|_""" 4
.el .IP "\f(CW_\|_AVR_HAVE_EIJMP_EICALL_\|_\fR" 4
.IX Item "__AVR_HAVE_EIJMP_EICALL__"
\&\fBbf542\fR, \fBbf544\fR, \fBbf547\fR, \fBbf548\fR, \fBbf549\fR,
\&\fBbf542m\fR, \fBbf544m\fR, \fBbf547m\fR, \fBbf548m\fR, \fBbf549m\fR,
\&\fBbf561\fR, \fBbf592\fR.
+.Sp
The optional \fIsirevision\fR specifies the silicon revision of the target
Blackfin processor. Any workarounds available for the targeted silicon revision
-will be enabled. If \fIsirevision\fR is \fBnone\fR, no workarounds are enabled.
+are enabled. If \fIsirevision\fR is \fBnone\fR, no workarounds are enabled.
If \fIsirevision\fR is \fBany\fR, all workarounds for the targeted processor
-will be enabled. The \f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR macro is defined to two
+are enabled. The \f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR macro is defined to two
hexadecimal digits representing the major and minor numbers in the silicon
revision. If \fIsirevision\fR is \fBnone\fR, the \f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR
is not defined. If \fIsirevision\fR is \fBany\fR, the
If this optional \fIsirevision\fR is not used, \s-1GCC\s0 assumes the latest known
silicon revision of the targeted Blackfin processor.
.Sp
-Support for \fBbf561\fR is incomplete. For \fBbf561\fR,
-Only the processor macro is defined.
-Without this option, \fBbf532\fR is used as the processor by default.
-The corresponding predefined processor macros for \fIcpu\fR is to
-be defined. And for \fBbfin-elf\fR toolchain, this causes the hardware \s-1BSP\s0
+\&\s-1GCC\s0 defines a preprocessor macro for the specified \fIcpu\fR.
+For the \fBbfin-elf\fR toolchain, this option causes the hardware \s-1BSP\s0
provided by libgloss to be linked in if \fB\-msim\fR is not given.
+.Sp
+Without this option, \fBbf532\fR is used as the processor by default.
+.Sp
+Note that support for \fBbf561\fR is incomplete. For \fBbf561\fR,
+only the preprocessor macro is defined.
.IP "\fB\-msim\fR" 4
.IX Item "-msim"
Specifies that the program will be run on the simulator. This causes
which might make debugging harder.
.IP "\fB\-mspecld\-anomaly\fR" 4
.IX Item "-mspecld-anomaly"
-When enabled, the compiler will ensure that the generated code does not
+When enabled, the compiler ensures that the generated code does not
contain speculative loads after jump instructions. If this option is used,
\&\f(CW\*(C`_\|_WORKAROUND_SPECULATIVE_LOADS\*(C'\fR is defined.
.IP "\fB\-mno\-specld\-anomaly\fR" 4
Don't generate extra code to prevent speculative loads from occurring.
.IP "\fB\-mcsync\-anomaly\fR" 4
.IX Item "-mcsync-anomaly"
-When enabled, the compiler will ensure that the generated code does not
+When enabled, the compiler ensures that the generated code does not
contain \s-1CSYNC\s0 or \s-1SSYNC\s0 instructions too soon after conditional branches.
If this option is used, \f(CW\*(C`_\|_WORKAROUND_SPECULATIVE_SYNCS\*(C'\fR is defined.
.IP "\fB\-mno\-csync\-anomaly\fR" 4
With a \fBbfin-elf\fR target, this option implies \fB\-msim\fR.
.IP "\fB\-mno\-id\-shared\-library\fR" 4
.IX Item "-mno-id-shared-library"
-Generate code that doesn't assume \s-1ID\s0 based shared libraries are being used.
+Generate code that doesn't assume ID-based shared libraries are being used.
This is the default.
.IP "\fB\-mleaf\-id\-shared\-library\fR" 4
.IX Item "-mleaf-id-shared-library"
.IP "\fB\-mno\-leaf\-id\-shared\-library\fR" 4
.IX Item "-mno-leaf-id-shared-library"
Do not assume that the code being compiled won't link against any \s-1ID\s0 shared
-libraries. Slower code will be generated for jump and call insns.
+libraries. Slower code is generated for jump and call insns.
.IP "\fB\-mshared\-library\-id=n\fR" 4
.IX Item "-mshared-library-id=n"
-Specified the identification number of the \s-1ID\s0 based shared library being
-compiled. Specifying a value of 0 will generate more compact code, specifying
-other values will force the allocation of that number to the current
-library but is no more space or time efficient than omitting this option.
+Specifies the identification number of the ID-based shared library being
+compiled. Specifying a value of 0 generates more compact code; specifying
+other values forces the allocation of that number to the current
+library but is no more space\- or time-efficient than omitting this option.
.IP "\fB\-msep\-data\fR" 4
.IX Item "-msep-data"
Generate code that allows the data segment to be located in a different
version of subroutine call instruction.
.Sp
This feature is not enabled by default. Specifying
-\&\fB\-mno\-long\-calls\fR will restore the default behavior. Note these
+\&\fB\-mno\-long\-calls\fR restores the default behavior. Note these
switches have no effect on how the compiler generates code to handle
function calls via function pointers.
.IP "\fB\-mfast\-fp\fR" 4
not known to bind locally. It has no effect without \fB\-mfdpic\fR.
.IP "\fB\-mmulticore\fR" 4
.IX Item "-mmulticore"
-Build standalone application for multicore Blackfin processor. Proper
-start files and link scripts will be used to support multicore.
-This option defines \f(CW\*(C`_\|_BFIN_MULTICORE\*(C'\fR. It can only be used with
-\&\fB\-mcpu=bf561\fR[\fB\-\fR\fIsirevision\fR]. It can be used with
-\&\fB\-mcorea\fR or \fB\-mcoreb\fR. If it's used without
-\&\fB\-mcorea\fR or \fB\-mcoreb\fR, single application/dual core
+Build a standalone application for multicore Blackfin processors.
+This option causes proper start files and link scripts supporting
+multicore to be used, and defines the macro \f(CW\*(C`_\|_BFIN_MULTICORE\*(C'\fR.
+It can only be used with \fB\-mcpu=bf561\fR[\fB\-\fR\fIsirevision\fR].
+.Sp
+This option can be used with \fB\-mcorea\fR or \fB\-mcoreb\fR, which
+selects the one-application-per-core programming model. Without
+\&\fB\-mcorea\fR or \fB\-mcoreb\fR, the single\-application/dual\-core
programming model is used. In this model, the main function of Core B
-should be named as coreb_main. If it's used with \fB\-mcorea\fR or
-\&\fB\-mcoreb\fR, one application per core programming model is used.
-If this option is not used, single core application programming
+should be named as \f(CW\*(C`coreb_main\*(C'\fR.
+.Sp
+If this option is not used, the single-core application programming
model is used.
.IP "\fB\-mcorea\fR" 4
.IX Item "-mcorea"
-Build standalone application for Core A of \s-1BF561\s0 when using
-one application per core programming model. Proper start files
-and link scripts will be used to support Core A. This option
-defines \f(CW\*(C`_\|_BFIN_COREA\*(C'\fR. It must be used with \fB\-mmulticore\fR.
+Build a standalone application for Core A of \s-1BF561\s0 when using
+the one-application-per-core programming model. Proper start files
+and link scripts are used to support Core A, and the macro
+\&\f(CW\*(C`_\|_BFIN_COREA\*(C'\fR is defined.
+This option can only be used in conjunction with \fB\-mmulticore\fR.
.IP "\fB\-mcoreb\fR" 4
.IX Item "-mcoreb"
-Build standalone application for Core B of \s-1BF561\s0 when using
-one application per core programming model. Proper start files
-and link scripts will be used to support Core B. This option
-defines \f(CW\*(C`_\|_BFIN_COREB\*(C'\fR. When this option is used, coreb_main
-should be used instead of main. It must be used with
-\&\fB\-mmulticore\fR.
+Build a standalone application for Core B of \s-1BF561\s0 when using
+the one-application-per-core programming model. Proper start files
+and link scripts are used to support Core B, and the macro
+\&\f(CW\*(C`_\|_BFIN_COREB\*(C'\fR is defined. When this option is used, \f(CW\*(C`coreb_main\*(C'\fR
+should be used instead of \f(CW\*(C`main\*(C'\fR.
+This option can only be used in conjunction with \fB\-mmulticore\fR.
.IP "\fB\-msdram\fR" 4
.IX Item "-msdram"
-Build standalone application for \s-1SDRAM\s0. Proper start files and
-link scripts will be used to put the application into \s-1SDRAM\s0.
-Loader should initialize \s-1SDRAM\s0 before loading the application
-into \s-1SDRAM\s0. This option defines \f(CW\*(C`_\|_BFIN_SDRAM\*(C'\fR.
+Build a standalone application for \s-1SDRAM\s0. Proper start files and
+link scripts are used to put the application into \s-1SDRAM\s0, and the macro
+\&\f(CW\*(C`_\|_BFIN_SDRAM\*(C'\fR is defined.
+The loader should initialize \s-1SDRAM\s0 before loading the application.
.IP "\fB\-micplb\fR" 4
.IX Item "-micplb"
Assume that ICPLBs are enabled at run time. This has an effect on certain
pieces of data are \fB.fardata\fR, \fB.far\fR and \fB.const\fR.
.IP "\fB\-msdata=all\fR" 4
.IX Item "-msdata=all"
-Put all data, not just small objets, into the sections reserved for
+Put all data, not just small objects, into the sections reserved for
small data, and use addressing relative to the \f(CW\*(C`B14\*(C'\fR register to
access them.
.IP "\fB\-msdata=none\fR" 4
.IP "\fB\-mpdebug\fR" 4
.IX Item "-mpdebug"
Enable CRIS-specific verbose debug-related information in the assembly
-code. This option also has the effect to turn off the \fB#NO_APP\fR
+code. This option also has the effect of turning off the \fB#NO_APP\fR
formatted-code indicator to the assembler at the beginning of the
assembly file.
.IP "\fB\-mcc\-init\fR" 4
compare and test instructions before use of condition codes.
.IP "\fB\-mno\-side\-effects\fR" 4
.IX Item "-mno-side-effects"
-Do not emit instructions with side-effects in addressing modes other than
+Do not emit instructions with side effects in addressing modes other than
post-increment.
.IP "\fB\-mstack\-align\fR" 4
.IX Item "-mstack-align"
.IP "\fB\-mno\-const\-align\fR" 4
.IX Item "-mno-const-align"
.PD
-These options (no-options) arranges (eliminate arrangements) for the
-stack-frame, individual data and constants to be aligned for the maximum
+These options (\fBno\-\fR options) arrange (eliminate arrangements) for the
+stack frame, individual data and constants to be aligned for the maximum
single data access size for the chosen \s-1CPU\s0 model. The default is to
arrange for 32\-bit alignment. \s-1ABI\s0 details such as structure layout are
not affected by these options.
.IX Item "-m8-bit"
.PD
Similar to the stack\- data\- and const-align options above, these options
-arrange for stack-frame, writable data and constants to all be 32\-bit,
+arrange for stack frame, writable data and constants to all be 32\-bit,
16\-bit or 8\-bit aligned. The default is 32\-bit alignment.
.IP "\fB\-mno\-prologue\-epilogue\fR" 4
.IX Item "-mno-prologue-epilogue"
instructions or return sequences are generated in the code. Use this
option only together with visual inspection of the compiled code: no
warnings or errors are generated when call-saved registers must be saved,
-or storage for local variable needs to be allocated.
+or storage for local variables needs to be allocated.
.IP "\fB\-mno\-gotplt\fR" 4
.IX Item "-mno-gotplt"
.PD 0
Legacy no-op option only recognized with the cris-axis-linux-gnu target.
.IP "\fB\-sim\fR" 4
.IX Item "-sim"
-This option, recognized for the cris-axis-elf arranges
+This option, recognized for the cris-axis-elf, arranges
to link with input-output functions from a simulator library. Code,
initialized data and zero-initialized data are allocated consecutively.
.IP "\fB\-sim2\fR" 4
.IP "\fB\-msim\fR" 4
.IX Item "-msim"
Links the library libsim.a which is in compatible with simulator. Applicable
-to elf compiler only.
+to \s-1ELF\s0 compiler only.
.IP "\fB\-mint32\fR" 4
.IX Item "-mint32"
Choose integer type as 32\-bit wide.
.IP "\fB\-mbit\-ops\fR" 4
.IX Item "-mbit-ops"
-Generates sbit/cbit instructions for bit manipulations.
+Generates \f(CW\*(C`sbit\*(C'\fR/\f(CW\*(C`cbit\*(C'\fR instructions for bit manipulations.
.IP "\fB\-mdata\-model=\fR\fImodel\fR" 4
.IX Item "-mdata-model=model"
Choose a data model. The choices for \fImodel\fR are \fBnear\fR,
\&\fBfar\fR or \fBmedium\fR. \fBmedium\fR is default.
-However, \fBfar\fR is not valid when \-mcr16c option is chosen as
-\&\s-1CR16C\s0 architecture does not support far data model.
+However, \fBfar\fR is not valid with \fB\-mcr16c\fR, as the
+\&\s-1CR16C\s0 architecture does not support the far data model.
.PP
\fIDarwin Options\fR
.IX Subsection "Darwin Options"
These options are defined for all architectures running the Darwin operating
system.
.PP
-\&\s-1FSF\s0 \s-1GCC\s0 on Darwin does not create \*(L"fat\*(R" object files; it will create
-an object file for the single architecture that it was built to
+\&\s-1FSF\s0 \s-1GCC\s0 on Darwin does not create \*(L"fat\*(R" object files; it creates
+an object file for the single architecture that \s-1GCC\s0 was built to
target. Apple's \s-1GCC\s0 on Darwin does create \*(L"fat\*(R" files if multiple
\&\fB\-arch\fR options are used; it does so by running the compiler or
linker multiple times and joining the results together with
.PP
The subtype of the file created (like \fBppc7400\fR or \fBppc970\fR or
\&\fBi686\fR) is determined by the flags that specify the \s-1ISA\s0
-that \s-1GCC\s0 is targetting, like \fB\-mcpu\fR or \fB\-march\fR. The
+that \s-1GCC\s0 is targeting, like \fB\-mcpu\fR or \fB\-march\fR. The
\&\fB\-force_cpusubtype_ALL\fR option can be used to override this.
.PP
The Darwin tools vary in their behavior when presented with an \s-1ISA\s0
-mismatch. The assembler, \fIas\fR, will only permit instructions to
+mismatch. The assembler, \fIas\fR, only permits instructions to
be used that are valid for the subtype of the file it is generating,
so you cannot put 64\-bit instructions in a \fBppc750\fR object file.
-The linker for shared libraries, \fI/usr/bin/libtool\fR, will fail
-and print an error if asked to create a shared library with a less
+The linker for shared libraries, \fI/usr/bin/libtool\fR, fails
+and prints an error if asked to create a shared library with a less
restrictive subtype than its input files (for instance, trying to put
a \fBppc970\fR object file in a \fBppc7400\fR library). The linker
-for executables, \fIld\fR, will quietly give the executable the most
+for executables, \fBld\fR, quietly gives the executable the most
restrictive subtype of any of its input files.
.IP "\fB\-F\fR\fIdir\fR" 4
.IX Item "-Fdir"
scanned in a left-to-right order.
.Sp
A framework directory is a directory with frameworks in it. A
-framework is a directory with a \fB\*(L"Headers\*(R"\fR and/or
-\&\fB\*(L"PrivateHeaders\*(R"\fR directory contained directly in it that ends
-in \fB\*(L".framework\*(R"\fR. The name of a framework is the name of this
-directory excluding the \fB\*(L".framework\*(R"\fR. Headers associated with
+framework is a directory with a \fIHeaders\fR and/or
+\&\fIPrivateHeaders\fR directory contained directly in it that ends
+in \fI.framework\fR. The name of a framework is the name of this
+directory excluding the \fI.framework\fR. Headers associated with
the framework are found in one of those two directories, with
-\&\fB\*(L"Headers\*(R"\fR being searched first. A subframework is a framework
-directory that is in a framework's \fB\*(L"Frameworks\*(R"\fR directory.
+\&\fIHeaders\fR being searched first. A subframework is a framework
+directory that is in a framework's \fIFrameworks\fR directory.
Includes of subframework headers can only appear in a header of a
framework that contains the subframework, or in a sibling subframework
header. Two subframeworks are siblings if they occur in the same
framework. A subframework should not have the same name as a
-framework, a warning will be issued if this is violated. Currently a
-subframework cannot have subframeworks, in the future, the mechanism
+framework; a warning is issued if this is violated. Currently a
+subframework cannot have subframeworks; in the future, the mechanism
may be extended to support this. The standard frameworks can be found
-in \fB\*(L"/System/Library/Frameworks\*(R"\fR and
-\&\fB\*(L"/Library/Frameworks\*(R"\fR. An example include looks like
-\&\f(CW\*(C`#include <Framework/header.h>\*(C'\fR, where \fBFramework\fR denotes
-the name of the framework and header.h is found in the
-\&\fB\*(L"PrivateHeaders\*(R"\fR or \fB\*(L"Headers\*(R"\fR directory.
+in \fI/System/Library/Frameworks\fR and
+\&\fI/Library/Frameworks\fR. An example include looks like
+\&\f(CW\*(C`#include <Framework/header.h>\*(C'\fR, where \fIFramework\fR denotes
+the name of the framework and \fIheader.h\fR is found in the
+\&\fIPrivateHeaders\fR or \fIHeaders\fR directory.
.IP "\fB\-iframework\fR\fIdir\fR" 4
.IX Item "-iframeworkdir"
Like \fB\-F\fR except the directory is a treated as a system
\&\fIdir\fR. This option is valid only for the C family of languages.
.IP "\fB\-gused\fR" 4
.IX Item "-gused"
-Emit debugging information for symbols that are used. For \s-1STABS\s0
+Emit debugging information for symbols that are used. For stabs
debugging format, this enables \fB\-feliminate\-unused\-debug\-symbols\fR.
This is by default \s-1ON\s0.
.IP "\fB\-gfull\fR" 4
.IP "\fB\-findirect\-data\fR" 4
.IX Item "-findirect-data"
.PD
-Generate code suitable for fast turn around development. Needed to
-enable gdb to dynamically load \f(CW\*(C`.o\*(C'\fR files into already running
+Generate code suitable for fast turnaround development, such as to
+allow \s-1GDB\s0 to dynamically load \f(CW\*(C`.o\*(C'\fR files into already-running
programs. \fB\-findirect\-data\fR and \fB\-ffix\-and\-continue\fR
are provided for backwards compatibility.
.IP "\fB\-all_load\fR" 4
See man \fIld\fR\|(1) for more information.
.IP "\fB\-bundle_loader\fR \fIexecutable\fR" 4
.IX Item "-bundle_loader executable"
-This option specifies the \fIexecutable\fR that will be loading the build
+This option specifies the \fIexecutable\fR that will load the build
output file being linked. See man \fIld\fR\|(1) for more information.
.IP "\fB\-dynamiclib\fR" 4
.IX Item "-dynamiclib"
-When passed this option, \s-1GCC\s0 will produce a dynamic library instead of
+When passed this option, \s-1GCC\s0 produces a dynamic library instead of
an executable when linking, using the Darwin \fIlibtool\fR command.
.IP "\fB\-force_cpusubtype_ALL\fR" 4
.IX Item "-force_cpusubtype_ALL"
.PD
Use (do not use) the hardware floating-point instructions for
floating-point operations. When \fB\-msoft\-float\fR is specified,
-functions in \fIlibgcc.a\fR will be used to perform floating-point
+functions in \fIlibgcc.a\fR are used to perform floating-point
operations. Unless they are replaced by routines that emulate the
floating-point operations, or compiled in such a way as to call such
-emulations routines, these routines will issue floating-point
+emulations routines, these routines issue floating-point
operations. If you are compiling for an Alpha without floating-point
operations, you must ensure that the library is built so as not to call
them.
use this option unless you also specify \fB\-mtrap\-precision=i\fR and either
\&\fB\-mfp\-trap\-mode=su\fR or \fB\-mfp\-trap\-mode=sui\fR. Its only effect
is to emit the line \fB.eflag 48\fR in the function prologue of the
-generated assembly file. Under \s-1DEC\s0 Unix, this has the effect that
-IEEE-conformant math library routines will be linked in.
+generated assembly file.
.IP "\fB\-mbuild\-constants\fR" 4
.IX Item "-mbuild-constants"
Normally \s-1GCC\s0 examines a 32\- or 64\-bit integer constant to
see if it can construct it from smaller constants in two or three
-instructions. If it cannot, it will output the constant as a literal and
-generate code to load it from the data segment at run time.
+instructions. If it cannot, it outputs the constant as a literal and
+generates code to load it from the data segment at run time.
.Sp
Use this option to require \s-1GCC\s0 to construct \fIall\fR integer constants
using code, even if it takes more instructions (the maximum is six).
.Sp
-You would typically use this option to build a shared library dynamic
+You typically use this option to build a shared library dynamic
loader. Itself a shared library, it must relocate itself in memory
before it can find the variables and constants in its own data segment.
-.IP "\fB\-malpha\-as\fR" 4
-.IX Item "-malpha-as"
-.PD 0
-.IP "\fB\-mgas\fR" 4
-.IX Item "-mgas"
-.PD
-Select whether to generate code to be assembled by the vendor-supplied
-assembler (\fB\-malpha\-as\fR) or by the \s-1GNU\s0 assembler \fB\-mgas\fR.
.IP "\fB\-mbwx\fR" 4
.IX Item "-mbwx"
.PD 0
Indicate whether \s-1GCC\s0 should generate code to use the optional \s-1BWX\s0,
\&\s-1CIX\s0, \s-1FIX\s0 and \s-1MAX\s0 instruction sets. The default is to use the instruction
sets supported by the \s-1CPU\s0 type specified via \fB\-mcpu=\fR option or that
-of the \s-1CPU\s0 on which \s-1GCC\s0 was built if none was specified.
+of the \s-1CPU\s0 on which \s-1GCC\s0 was built if none is specified.
.IP "\fB\-mfloat\-vax\fR" 4
.IX Item "-mfloat-vax"
.PD 0
Set the instruction set and instruction scheduling parameters for
machine type \fIcpu_type\fR. You can specify either the \fB\s-1EV\s0\fR
style name or the corresponding chip number. \s-1GCC\s0 supports scheduling
-parameters for the \s-1EV4\s0, \s-1EV5\s0 and \s-1EV6\s0 family of processors and will
-choose the default values for the instruction set from the processor
-you specify. If you do not specify a processor type, \s-1GCC\s0 will default
+parameters for the \s-1EV4\s0, \s-1EV5\s0 and \s-1EV6\s0 family of processors and
+chooses the default values for the instruction set from the processor
+you specify. If you do not specify a processor type, \s-1GCC\s0 defaults
to the processor on which the compiler was built.
.Sp
Supported values for \fIcpu_type\fR are
.RS 4
.RE
.PP
-\fI\s-1DEC\s0 Alpha/VMS Options\fR
-.IX Subsection "DEC Alpha/VMS Options"
-.PP
-These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha/VMS implementations:
-.IP "\fB\-mvms\-return\-codes\fR" 4
-.IX Item "-mvms-return-codes"
-Return \s-1VMS\s0 condition codes from main. The default is to return \s-1POSIX\s0
-style condition (e.g. error) codes.
-.IP "\fB\-mdebug\-main=\fR\fIprefix\fR" 4
-.IX Item "-mdebug-main=prefix"
-Flag the first routine whose name starts with \fIprefix\fR as the main
-routine for the debugger.
-.IP "\fB\-mmalloc64\fR" 4
-.IX Item "-mmalloc64"
-Default to 64\-bit memory allocation routines.
-.PP
\fI\s-1FR30\s0 Options\fR
.IX Subsection "FR30 Options"
.PP
.IP "\fB\-msmall\-model\fR" 4
.IX Item "-msmall-model"
Use the small address space model. This can produce smaller code, but
-it does assume that all symbolic values and addresses will fit into a
+it does assume that all symbolic values and addresses fit into a
20\-bit range.
.IP "\fB\-mno\-lsim\fR" 4
.IX Item "-mno-lsim"
within the 32\-bit address space.
.IP "\fB\-malign\-labels\fR" 4
.IX Item "-malign-labels"
-Try to align labels to an 8\-byte boundary by inserting nops into the
+Try to align labels to an 8\-byte boundary by inserting NOPs into the
previous packet. This option only has an effect when \s-1VLIW\s0 packing
-is enabled. It doesn't create new packets; it merely adds nops to
+is enabled. It doesn't create new packets; it merely adds NOPs to
existing ones.
.IP "\fB\-mlibrary\-pic\fR" 4
.IX Item "-mlibrary-pic"
.IP "\fB\-moptimize\-membar\fR" 4
.IX Item "-moptimize-membar"
This switch removes redundant \f(CW\*(C`membar\*(C'\fR instructions from the
-compiler generated code. It is enabled by default.
+compiler-generated code. It is enabled by default.
.IP "\fB\-mno\-optimize\-membar\fR" 4
.IX Item "-mno-optimize-membar"
This switch disables the automatic removal of redundant \f(CW\*(C`membar\*(C'\fR
.IP "\fB\-ms2600\fR" 4
.IX Item "-ms2600"
Generate code for the H8S/2600. This switch must be used with \fB\-ms\fR.
+.IP "\fB\-mexr\fR" 4
+.IX Item "-mexr"
+Extended registers are stored on stack before execution of function
+with monitor attribute. Default option is \fB\-mexr\fR.
+This option is valid only for H8S targets.
+.IP "\fB\-mno\-exr\fR" 4
+.IX Item "-mno-exr"
+Extended registers are not stored on stack before execution of function
+with monitor attribute. Default option is \fB\-mno\-exr\fR.
+This option is valid only for H8S targets.
.IP "\fB\-mint32\fR" 4
.IX Item "-mint32"
Make \f(CW\*(C`int\*(C'\fR data 32 bits by default.
1.1, and \fB2.0\fR for \s-1PA\s0 2.0 processors. Refer to
\&\fI/usr/lib/sched.models\fR on an HP-UX system to determine the proper
architecture option for your machine. Code compiled for lower numbered
-architectures will run on higher numbered architectures, but not the
+architectures runs on higher numbered architectures, but not the
other way around.
.IP "\fB\-mpa\-risc\-1\-0\fR" 4
.IX Item "-mpa-risc-1-0"
.IP "\fB\-mbig\-switch\fR" 4
.IX Item "-mbig-switch"
Generate code suitable for big switch tables. Use this option only if
-the assembler/linker complain about out of range branches within a switch
+the assembler/linker complain about out-of-range branches within a switch
table.
.IP "\fB\-mjump\-in\-delay\fR" 4
.IX Item "-mjump-in-delay"
Generate code that assumes calls never cross space boundaries. This
allows \s-1GCC\s0 to emit code that performs faster indirect calls.
.Sp
-This option will not work in the presence of shared libraries or nested
+This option does not work in the presence of shared libraries or nested
functions.
.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4
.IX Item "-mfixed-range=register-range"
Generate code treating the given register range as fixed registers.
-A fixed register is one that the register allocator can not use. This is
+A fixed register is one that the register allocator cannot use. This is
useful when compiling kernel code. A register range is specified as
two registers separated by a dash. Multiple register ranges can be
specified separated by a comma.
options are available under HP-UX and HI-UX.
.IP "\fB\-mgnu\-ld\fR" 4
.IX Item "-mgnu-ld"
-Use \s-1GNU\s0 ld specific options. This passes \fB\-shared\fR to ld when
+Use options specific to \s-1GNU\s0 \fBld\fR.
+This passes \fB\-shared\fR to \fBld\fR when
building a shared library. It is the default when \s-1GCC\s0 is configured,
explicitly or implicitly, with the \s-1GNU\s0 linker. This option does not
-have any affect on which ld is called, it only changes what parameters
-are passed to that ld. The ld that is called is determined by the
+affect which \fBld\fR is called; it only changes what parameters
+are passed to that \fBld\fR.
+The \fBld\fR that is called is determined by the
\&\fB\-\-with\-ld\fR configure option, \s-1GCC\s0's program search path, and
finally by the user's \fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed
using \fBwhich `gcc \-print\-prog\-name=ld`\fR. This option is only available
on the 64\-bit HP-UX \s-1GCC\s0, i.e. configured with \fBhppa*64*\-*\-hpux*\fR.
.IP "\fB\-mhp\-ld\fR" 4
.IX Item "-mhp-ld"
-Use \s-1HP\s0 ld specific options. This passes \fB\-b\fR to ld when building
-a shared library and passes \fB+Accept TypeMismatch\fR to ld on all
+Use options specific to \s-1HP\s0 \fBld\fR.
+This passes \fB\-b\fR to \fBld\fR when building
+a shared library and passes \fB+Accept TypeMismatch\fR to \fBld\fR on all
links. It is the default when \s-1GCC\s0 is configured, explicitly or
-implicitly, with the \s-1HP\s0 linker. This option does not have any affect on
-which ld is called, it only changes what parameters are passed to that
-ld. The ld that is called is determined by the \fB\-\-with\-ld\fR
+implicitly, with the \s-1HP\s0 linker. This option does not affect
+which \fBld\fR is called; it only changes what parameters are passed to that
+\&\fBld\fR.
+The \fBld\fR that is called is determined by the \fB\-\-with\-ld\fR
configure option, \s-1GCC\s0's program search path, and finally by the user's
\&\fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed using \fBwhich
`gcc \-print\-prog\-name=ld`\fR. This option is only available on the 64\-bit
and \fB\-mno\-portable\-runtime\fR options together under HP-UX with
the \s-1SOM\s0 linker.
.Sp
-It is normally not desirable to use this option as it will degrade
+It is normally not desirable to use this option as it degrades
performance. However, it may be useful in large applications,
particularly when partial linking is used to build the application.
.Sp
.PP
These \fB\-m\fR options are defined for the i386 and x86\-64 family of
computers:
-.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4
-.IX Item "-mtune=cpu-type"
-Tune to \fIcpu-type\fR everything applicable about the generated code, except
-for the \s-1ABI\s0 and the set of available instructions. The choices for
-\&\fIcpu-type\fR are:
+.IP "\fB\-march=\fR\fIcpu-type\fR" 4
+.IX Item "-march=cpu-type"
+Generate instructions for the machine type \fIcpu-type\fR. In contrast to
+\&\fB\-mtune=\fR\fIcpu-type\fR, which merely tunes the generated code
+for the specified \fIcpu-type\fR, \fB\-march=\fR\fIcpu-type\fR allows \s-1GCC\s0
+to generate code that may not run at all on processors other than the one
+indicated. Specifying \fB\-march=\fR\fIcpu-type\fR implies
+\&\fB\-mtune=\fR\fIcpu-type\fR.
+.Sp
+The choices for \fIcpu-type\fR are:
.RS 4
-.IP "\fIgeneric\fR" 4
-.IX Item "generic"
-Produce code optimized for the most common \s-1IA32/AMD64/EM64T\s0 processors.
-If you know the \s-1CPU\s0 on which your code will run, then you should use
-the corresponding \fB\-mtune\fR option instead of
-\&\fB\-mtune=generic\fR. But, if you do not know exactly what \s-1CPU\s0 users
-of your application will have, then you should use this option.
-.Sp
-As new processors are deployed in the marketplace, the behavior of this
-option will change. Therefore, if you upgrade to a newer version of
-\&\s-1GCC\s0, the code generated option will change to reflect the processors
-that were most common when that version of \s-1GCC\s0 was released.
-.Sp
-There is no \fB\-march=generic\fR option because \fB\-march\fR
-indicates the instruction set the compiler can use, and there is no
-generic instruction set applicable to all processors. In contrast,
-\&\fB\-mtune\fR indicates the processor (or, in this case, collection of
-processors) for which the code is optimized.
-.IP "\fInative\fR" 4
+.IP "\fBnative\fR" 4
.IX Item "native"
-This selects the \s-1CPU\s0 to tune for at compilation time by determining
-the processor type of the compiling machine. Using \fB\-mtune=native\fR
-will produce code optimized for the local machine under the constraints
-of the selected instruction set. Using \fB\-march=native\fR will
-enable all instruction subsets supported by the local machine (hence
-the result might not run on different machines).
-.IP "\fIi386\fR" 4
+This selects the \s-1CPU\s0 to generate code for at compilation time by determining
+the processor type of the compiling machine. Using \fB\-march=native\fR
+enables all instruction subsets supported by the local machine (hence
+the result might not run on different machines). Using \fB\-mtune=native\fR
+produces code optimized for the local machine under the constraints
+of the selected instruction set.
+.IP "\fBi386\fR" 4
.IX Item "i386"
-Original Intel's i386 \s-1CPU\s0.
-.IP "\fIi486\fR" 4
+Original Intel i386 \s-1CPU\s0.
+.IP "\fBi486\fR" 4
.IX Item "i486"
-Intel's i486 \s-1CPU\s0. (No scheduling is implemented for this chip.)
-.IP "\fIi586, pentium\fR" 4
-.IX Item "i586, pentium"
+Intel i486 \s-1CPU\s0. (No scheduling is implemented for this chip.)
+.IP "\fBi586\fR" 4
+.IX Item "i586"
+.PD 0
+.IP "\fBpentium\fR" 4
+.IX Item "pentium"
+.PD
Intel Pentium \s-1CPU\s0 with no \s-1MMX\s0 support.
-.IP "\fIpentium-mmx\fR" 4
+.IP "\fBpentium-mmx\fR" 4
.IX Item "pentium-mmx"
-Intel PentiumMMX \s-1CPU\s0 based on Pentium core with \s-1MMX\s0 instruction set support.
-.IP "\fIpentiumpro\fR" 4
+Intel Pentium \s-1MMX\s0 \s-1CPU\s0, based on Pentium core with \s-1MMX\s0 instruction set support.
+.IP "\fBpentiumpro\fR" 4
.IX Item "pentiumpro"
-Intel PentiumPro \s-1CPU\s0.
-.IP "\fIi686\fR" 4
+Intel Pentium Pro \s-1CPU\s0.
+.IP "\fBi686\fR" 4
.IX Item "i686"
-Same as \f(CW\*(C`generic\*(C'\fR, but when used as \f(CW\*(C`march\*(C'\fR option, PentiumPro
-instruction set will be used, so the code will run on all i686 family chips.
-.IP "\fIpentium2\fR" 4
+When used with \fB\-march\fR, the Pentium Pro
+instruction set is used, so the code runs on all i686 family chips.
+When used with \fB\-mtune\fR, it has the same meaning as \fBgeneric\fR.
+.IP "\fBpentium2\fR" 4
.IX Item "pentium2"
-Intel Pentium2 \s-1CPU\s0 based on PentiumPro core with \s-1MMX\s0 instruction set support.
-.IP "\fIpentium3, pentium3m\fR" 4
-.IX Item "pentium3, pentium3m"
-Intel Pentium3 \s-1CPU\s0 based on PentiumPro core with \s-1MMX\s0 and \s-1SSE\s0 instruction set
+Intel Pentium \s-1II\s0 \s-1CPU\s0, based on Pentium Pro core with \s-1MMX\s0 instruction set
support.
-.IP "\fIpentium-m\fR" 4
+.IP "\fBpentium3\fR" 4
+.IX Item "pentium3"
+.PD 0
+.IP "\fBpentium3m\fR" 4
+.IX Item "pentium3m"
+.PD
+Intel Pentium \s-1III\s0 \s-1CPU\s0, based on Pentium Pro core with \s-1MMX\s0 and \s-1SSE\s0 instruction
+set support.
+.IP "\fBpentium-m\fR" 4
.IX Item "pentium-m"
-Low power version of Intel Pentium3 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set
-support. Used by Centrino notebooks.
-.IP "\fIpentium4, pentium4m\fR" 4
-.IX Item "pentium4, pentium4m"
-Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set support.
-.IP "\fIprescott\fR" 4
+Intel Pentium M; low-power version of Intel Pentium \s-1III\s0 \s-1CPU\s0
+with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set support. Used by Centrino notebooks.
+.IP "\fBpentium4\fR" 4
+.IX Item "pentium4"
+.PD 0
+.IP "\fBpentium4m\fR" 4
+.IX Item "pentium4m"
+.PD
+Intel Pentium 4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set support.
+.IP "\fBprescott\fR" 4
.IX Item "prescott"
-Improved version of Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0 and \s-1SSE3\s0 instruction
+Improved version of Intel Pentium 4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0 and \s-1SSE3\s0 instruction
set support.
-.IP "\fInocona\fR" 4
+.IP "\fBnocona\fR" 4
.IX Item "nocona"
-Improved version of Intel Pentium4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0,
+Improved version of Intel Pentium 4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0,
\&\s-1SSE2\s0 and \s-1SSE3\s0 instruction set support.
-.IP "\fIcore2\fR" 4
+.IP "\fBcore2\fR" 4
.IX Item "core2"
-Intel Core2 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0
+Intel Core 2 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0
instruction set support.
-.IP "\fIcorei7\fR" 4
+.IP "\fBcorei7\fR" 4
.IX Item "corei7"
Intel Core i7 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1
and \s-1SSE4\s0.2 instruction set support.
-.IP "\fIcorei7\-avx\fR" 4
+.IP "\fBcorei7\-avx\fR" 4
.IX Item "corei7-avx"
Intel Core i7 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0,
\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1AVX\s0, \s-1AES\s0 and \s-1PCLMUL\s0 instruction set support.
-.IP "\fIcore-avx-i\fR" 4
+.IP "\fBcore-avx-i\fR" 4
.IX Item "core-avx-i"
Intel Core \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0,
\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1AVX\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0 and F16C instruction
set support.
-.IP "\fIatom\fR" 4
+.IP "\fBatom\fR" 4
.IX Item "atom"
Intel Atom \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0
instruction set support.
-.IP "\fIk6\fR" 4
+.IP "\fBk6\fR" 4
.IX Item "k6"
\&\s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 instruction set support.
-.IP "\fIk6\-2, k6\-3\fR" 4
-.IX Item "k6-2, k6-3"
+.IP "\fBk6\-2\fR" 4
+.IX Item "k6-2"
+.PD 0
+.IP "\fBk6\-3\fR" 4
+.IX Item "k6-3"
+.PD
Improved versions of \s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support.
-.IP "\fIathlon, athlon-tbird\fR" 4
-.IX Item "athlon, athlon-tbird"
+.IP "\fBathlon\fR" 4
+.IX Item "athlon"
+.PD 0
+.IP "\fBathlon-tbird\fR" 4
+.IX Item "athlon-tbird"
+.PD
\&\s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3dNOW!, enhanced 3DNow! and \s-1SSE\s0 prefetch instructions
support.
-.IP "\fIathlon\-4, athlon-xp, athlon-mp\fR" 4
-.IX Item "athlon-4, athlon-xp, athlon-mp"
+.IP "\fBathlon\-4\fR" 4
+.IX Item "athlon-4"
+.PD 0
+.IP "\fBathlon-xp\fR" 4
+.IX Item "athlon-xp"
+.IP "\fBathlon-mp\fR" 4
+.IX Item "athlon-mp"
+.PD
Improved \s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3DNow!, enhanced 3DNow! and full \s-1SSE\s0
instruction set support.
-.IP "\fIk8, opteron, athlon64, athlon-fx\fR" 4
-.IX Item "k8, opteron, athlon64, athlon-fx"
-\&\s-1AMD\s0 K8 core based CPUs with x86\-64 instruction set support. (This supersets
-\&\s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, 3DNow!, enhanced 3DNow! and 64\-bit instruction set extensions.)
-.IP "\fIk8\-sse3, opteron\-sse3, athlon64\-sse3\fR" 4
-.IX Item "k8-sse3, opteron-sse3, athlon64-sse3"
-Improved versions of k8, opteron and athlon64 with \s-1SSE3\s0 instruction set support.
-.IP "\fIamdfam10, barcelona\fR" 4
-.IX Item "amdfam10, barcelona"
-\&\s-1AMD\s0 Family 10h core based CPUs with x86\-64 instruction set support. (This
+.IP "\fBk8\fR" 4
+.IX Item "k8"
+.PD 0
+.IP "\fBopteron\fR" 4
+.IX Item "opteron"
+.IP "\fBathlon64\fR" 4
+.IX Item "athlon64"
+.IP "\fBathlon-fx\fR" 4
+.IX Item "athlon-fx"
+.PD
+Processors based on the \s-1AMD\s0 K8 core with x86\-64 instruction set support,
+including the \s-1AMD\s0 Opteron, Athlon 64, and Athlon 64 \s-1FX\s0 processors.
+(This supersets \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, 3DNow!, enhanced 3DNow! and 64\-bit
+instruction set extensions.)
+.IP "\fBk8\-sse3\fR" 4
+.IX Item "k8-sse3"
+.PD 0
+.IP "\fBopteron\-sse3\fR" 4
+.IX Item "opteron-sse3"
+.IP "\fBathlon64\-sse3\fR" 4
+.IX Item "athlon64-sse3"
+.PD
+Improved versions of \s-1AMD\s0 K8 cores with \s-1SSE3\s0 instruction set support.
+.IP "\fBamdfam10\fR" 4
+.IX Item "amdfam10"
+.PD 0
+.IP "\fBbarcelona\fR" 4
+.IX Item "barcelona"
+.PD
+CPUs based on \s-1AMD\s0 Family 10h cores with x86\-64 instruction set support. (This
supersets \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, 3DNow!, enhanced 3DNow!, \s-1ABM\s0 and 64\-bit
instruction set extensions.)
-.IP "\fIbdver1\fR" 4
+.IP "\fBbdver1\fR" 4
.IX Item "bdver1"
-\&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This
+CPUs based on \s-1AMD\s0 Family 15h cores with x86\-64 instruction set support. (This
supersets \s-1FMA4\s0, \s-1AVX\s0, \s-1XOP\s0, \s-1LWP\s0, \s-1AES\s0, \s-1PCL_MUL\s0, \s-1CX16\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0,
\&\s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1ABM\s0 and 64\-bit instruction set extensions.)
-.IP "\fIbdver2\fR" 4
+.IP "\fBbdver2\fR" 4
.IX Item "bdver2"
\&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This
supersets \s-1BMI\s0, \s-1TBM\s0, F16C, \s-1FMA\s0, \s-1AVX\s0, \s-1XOP\s0, \s-1LWP\s0, \s-1AES\s0, \s-1PCL_MUL\s0, \s-1CX16\s0, \s-1MMX\s0, \s-1SSE\s0,
\&\s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1ABM\s0 and 64\-bit instruction set
extensions.)
-.IP "\fIbtver1\fR" 4
+.IP "\fBbdver3\fR" 4
+.IX Item "bdver3"
+\&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This
+supersets \s-1BMI\s0, \s-1TBM\s0, F16C, \s-1FMA\s0, \s-1AVX\s0, \s-1XOP\s0, \s-1LWP\s0, \s-1AES\s0, \s-1PCL_MUL\s0, \s-1CX16\s0, \s-1MMX\s0, \s-1SSE\s0,
+\&\s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1ABM\s0 and 64\-bit instruction set
+extensions.
+.IP "\fBbtver1\fR" 4
.IX Item "btver1"
-\&\s-1AMD\s0 Family 14h core based CPUs with x86\-64 instruction set support. (This
+CPUs based on \s-1AMD\s0 Family 14h cores with x86\-64 instruction set support. (This
supersets \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \s-1SSE4A\s0, \s-1CX16\s0, \s-1ABM\s0 and 64\-bit
instruction set extensions.)
-.IP "\fIwinchip\-c6\fR" 4
+.IP "\fBbtver2\fR" 4
+.IX Item "btver2"
+CPUs based on \s-1AMD\s0 Family 16h cores with x86\-64 instruction set support. This
+includes \s-1MOVBE\s0, F16C, \s-1BMI\s0, \s-1AVX\s0, \s-1PCL_MUL\s0, \s-1AES\s0, \s-1SSE4\s0.2, \s-1SSE4\s0.1, \s-1CX16\s0, \s-1ABM\s0,
+\&\s-1SSE4A\s0, \s-1SSSE3\s0, \s-1SSE3\s0, \s-1SSE2\s0, \s-1SSE\s0, \s-1MMX\s0 and 64\-bit instruction set extensions.
+.IP "\fBwinchip\-c6\fR" 4
.IX Item "winchip-c6"
-\&\s-1IDT\s0 Winchip C6 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 instruction
+\&\s-1IDT\s0 WinChip C6 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 instruction
set support.
-.IP "\fIwinchip2\fR" 4
+.IP "\fBwinchip2\fR" 4
.IX Item "winchip2"
-\&\s-1IDT\s0 Winchip2 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 and 3DNow!
+\&\s-1IDT\s0 WinChip 2 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 and 3DNow!
instruction set support.
-.IP "\fIc3\fR" 4
+.IP "\fBc3\fR" 4
.IX Item "c3"
-Via C3 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. (No scheduling is
+\&\s-1VIA\s0 C3 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. (No scheduling is
implemented for this chip.)
-.IP "\fIc3\-2\fR" 4
+.IP "\fBc3\-2\fR" 4
.IX Item "c3-2"
-Via C3\-2 \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. (No scheduling is
+\&\s-1VIA\s0 C3\-2 (Nehemiah/C5XL) \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support.
+(No scheduling is
implemented for this chip.)
-.IP "\fIgeode\fR" 4
+.IP "\fBgeode\fR" 4
.IX Item "geode"
-Embedded \s-1AMD\s0 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support.
+\&\s-1AMD\s0 Geode embedded processor with \s-1MMX\s0 and 3DNow! instruction set support.
.RE
.RS 4
+.RE
+.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4
+.IX Item "-mtune=cpu-type"
+Tune to \fIcpu-type\fR everything applicable about the generated code, except
+for the \s-1ABI\s0 and the set of available instructions.
+While picking a specific \fIcpu-type\fR schedules things appropriately
+for that particular chip, the compiler does not generate any code that
+cannot run on the default machine type unless you use a
+\&\fB\-march=\fR\fIcpu-type\fR option.
+For example, if \s-1GCC\s0 is configured for i686\-pc\-linux\-gnu
+then \fB\-mtune=pentium4\fR generates code that is tuned for Pentium 4
+but still runs on i686 machines.
+.Sp
+The choices for \fIcpu-type\fR are the same as for \fB\-march\fR.
+In addition, \fB\-mtune\fR supports an extra choice for \fIcpu-type\fR:
+.RS 4
+.IP "\fBgeneric\fR" 4
+.IX Item "generic"
+Produce code optimized for the most common \s-1IA32/AMD64/EM64T\s0 processors.
+If you know the \s-1CPU\s0 on which your code will run, then you should use
+the corresponding \fB\-mtune\fR or \fB\-march\fR option instead of
+\&\fB\-mtune=generic\fR. But, if you do not know exactly what \s-1CPU\s0 users
+of your application will have, then you should use this option.
+.Sp
+As new processors are deployed in the marketplace, the behavior of this
+option will change. Therefore, if you upgrade to a newer version of
+\&\s-1GCC\s0, code generation controlled by this option will change to reflect
+the processors
+that are most common at the time that version of \s-1GCC\s0 is released.
.Sp
-While picking a specific \fIcpu-type\fR will schedule things appropriately
-for that particular chip, the compiler will not generate any code that
-does not run on the default machine type without the \fB\-march=\fR\fIcpu-type\fR
-option being used. For example, if \s-1GCC\s0 is configured for i686\-pc\-linux\-gnu
-then \fB\-mtune=pentium4\fR will generate code that is tuned for Pentium4
-but will still run on i686 machines.
+There is no \fB\-march=generic\fR option because \fB\-march\fR
+indicates the instruction set the compiler can use, and there is no
+generic instruction set applicable to all processors. In contrast,
+\&\fB\-mtune\fR indicates the processor (or, in this case, collection of
+processors) for which the code is optimized.
+.RE
+.RS 4
.RE
-.IP "\fB\-march=\fR\fIcpu-type\fR" 4
-.IX Item "-march=cpu-type"
-Generate instructions for the machine type \fIcpu-type\fR. The choices
-for \fIcpu-type\fR are the same as for \fB\-mtune\fR. Moreover,
-specifying \fB\-march=\fR\fIcpu-type\fR implies \fB\-mtune=\fR\fIcpu-type\fR.
.IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4
.IX Item "-mcpu=cpu-type"
A deprecated synonym for \fB\-mtune\fR.
.IP "\fBsse\fR" 4
.IX Item "sse"
Use scalar floating-point instructions present in the \s-1SSE\s0 instruction set.
-This instruction set is supported by Pentium3 and newer chips, in the \s-1AMD\s0 line
-by Athlon\-4, Athlon-xp and Athlon-mp chips. The earlier version of \s-1SSE\s0
+This instruction set is supported by Pentium \s-1III\s0 and newer chips,
+and in the \s-1AMD\s0 line
+by Athlon\-4, Athlon \s-1XP\s0 and Athlon \s-1MP\s0 chips. The earlier version of the \s-1SSE\s0
instruction set supports only single-precision arithmetic, thus the double and
extended-precision arithmetic are still done using 387. A later version, present
-only in Pentium4 and the future \s-1AMD\s0 x86\-64 chips, supports double-precision
+only in Pentium 4 and \s-1AMD\s0 x86\-64 chips, supports double-precision
arithmetic too.
.Sp
-For the i386 compiler, you need to use \fB\-march=\fR\fIcpu-type\fR, \fB\-msse\fR
+For the i386 compiler, you must use \fB\-march=\fR\fIcpu-type\fR, \fB\-msse\fR
or \fB\-msse2\fR switches to enable \s-1SSE\s0 extensions and make this option
effective. For the x86\-64 compiler, these extensions are enabled by default.
.Sp
.IP "\fBboth\fR" 4
.IX Item "both"
.PD
-Attempt to utilize both instruction sets at once. This effectively double the
-amount of available registers and on chips with separate execution units for
+Attempt to utilize both instruction sets at once. This effectively doubles the
+amount of available registers, and on chips with separate execution units for
387 and \s-1SSE\s0 the execution resources too. Use this option with care, as it is
still experimental, because the \s-1GCC\s0 register allocator does not model separate
-functional units well resulting in instable performance.
+functional units well, resulting in unstable performance.
.RE
.RS 4
.RE
.IP "\fB\-masm=\fR\fIdialect\fR" 4
.IX Item "-masm=dialect"
-Output asm instructions using selected \fIdialect\fR. Supported
-choices are \fBintel\fR or \fBatt\fR (the default one). Darwin does
+Output assembly instructions using selected \fIdialect\fR. Supported
+choices are \fBintel\fR or \fBatt\fR (the default). Darwin does
not support \fBintel\fR.
.IP "\fB\-mieee\-fp\fR" 4
.IX Item "-mieee-fp"
.IX Item "-mno-ieee-fp"
.PD
Control whether or not the compiler uses \s-1IEEE\s0 floating-point
-comparisons. These handle correctly the case where the result of a
+comparisons. These correctly handle the case where the result of a
comparison is unordered.
.IP "\fB\-msoft\-float\fR" 4
.IX Item "-msoft-float"
Generate output containing library calls for floating point.
+.Sp
\&\fBWarning:\fR the requisite libraries are not part of \s-1GCC\s0.
Normally the facilities of the machine's usual C compiler are used, but
this can't be done directly in cross-compilation. You must make your
\&\f(CW\*(C`sqrt\*(C'\fR instructions for the 387. Specify this option to avoid
generating those instructions. This option is the default on FreeBSD,
OpenBSD and NetBSD. This option is overridden when \fB\-march\fR
-indicates that the target \s-1CPU\s0 will always have an \s-1FPU\s0 and so the
-instruction will not need emulation. As of revision 2.6.1, these
+indicates that the target \s-1CPU\s0 always has an \s-1FPU\s0 and so the
+instruction does not need emulation. These
instructions are not generated unless you also use the
\&\fB\-funsafe\-math\-optimizations\fR switch.
.IP "\fB\-malign\-double\fR" 4
Control whether \s-1GCC\s0 aligns \f(CW\*(C`double\*(C'\fR, \f(CW\*(C`long double\*(C'\fR, and
\&\f(CW\*(C`long long\*(C'\fR variables on a two-word boundary or a one-word
boundary. Aligning \f(CW\*(C`double\*(C'\fR variables on a two-word boundary
-produces code that runs somewhat faster on a \fBPentium\fR at the
+produces code that runs somewhat faster on a Pentium at the
expense of more memory.
.Sp
On x86\-64, \fB\-malign\-double\fR is enabled by default.
.Sp
\&\fBWarning:\fR if you use the \fB\-malign\-double\fR switch,
-structures containing the above types will be aligned differently than
+structures containing the above types are aligned differently than
the published application binary interface specifications for the 386
-and will not be binary compatible with structures in code compiled
+and are not binary compatible with structures in code compiled
without that switch.
.IP "\fB\-m96bit\-long\-double\fR" 4
.IX Item "-m96bit-long-double"
32\-bit zero.
.Sp
In the x86\-64 compiler, \fB\-m128bit\-long\-double\fR is the default choice as
-its \s-1ABI\s0 specifies that \f(CW\*(C`long double\*(C'\fR is to be aligned on 16\-byte boundary.
+its \s-1ABI\s0 specifies that \f(CW\*(C`long double\*(C'\fR is aligned on 16\-byte boundary.
.Sp
Notice that neither of these options enable any extra precision over the x87
standard of 80 bits for a \f(CW\*(C`long double\*(C'\fR.
.Sp
-\&\fBWarning:\fR if you override the default value for your target \s-1ABI\s0, the
-structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables will change
-their size as well as function calling convention for function taking
-\&\f(CW\*(C`long double\*(C'\fR will be modified. Hence they will not be binary
-compatible with arrays or structures in code compiled without that switch.
-.IP "\fB\-mlarge\-data\-threshold=\fR\fInumber\fR" 4
-.IX Item "-mlarge-data-threshold=number"
-When \fB\-mcmodel=medium\fR is specified, the data greater than
-\&\fIthreshold\fR are placed in large data section. This value must be the
-same across all object linked into the binary and defaults to 65535.
+\&\fBWarning:\fR if you override the default value for your target \s-1ABI\s0, this
+changes the size of
+structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables,
+as well as modifying the function calling convention for functions taking
+\&\f(CW\*(C`long double\*(C'\fR. Hence they are not binary-compatible
+with code compiled without that switch.
+.IP "\fB\-mlong\-double\-64\fR" 4
+.IX Item "-mlong-double-64"
+.PD 0
+.IP "\fB\-mlong\-double\-80\fR" 4
+.IX Item "-mlong-double-80"
+.PD
+These switches control the size of \f(CW\*(C`long double\*(C'\fR type. A size
+of 64 bits makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the \f(CW\*(C`double\*(C'\fR
+type. This is the default for Bionic C library.
+.Sp
+\&\fBWarning:\fR if you override the default value for your target \s-1ABI\s0, this
+changes the size of
+structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables,
+as well as modifying the function calling convention for functions taking
+\&\f(CW\*(C`long double\*(C'\fR. Hence they are not binary-compatible
+with code compiled without that switch.
+.IP "\fB\-mlarge\-data\-threshold=\fR\fIthreshold\fR" 4
+.IX Item "-mlarge-data-threshold=threshold"
+When \fB\-mcmodel=medium\fR is specified, data objects larger than
+\&\fIthreshold\fR are placed in the large data section. This value must be the
+same across all objects linked into the binary, and defaults to 65535.
.IP "\fB\-mrtd\fR" 4
.IX Item "-mrtd"
Use a different function-calling convention, in which functions that
-take a fixed number of arguments return with the \f(CW\*(C`ret\*(C'\fR \fInum\fR
+take a fixed number of arguments return with the \f(CW\*(C`ret \f(CInum\f(CW\*(C'\fR
instruction, which pops their arguments while returning. This saves one
instruction in the caller since there is no need to pop the arguments
there.
.Sp
Also, you must provide function prototypes for all functions that
take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR);
-otherwise incorrect code will be generated for calls to those
+otherwise incorrect code is generated for calls to those
functions.
.Sp
-In addition, seriously incorrect code will result if you call a
+In addition, seriously incorrect code results if you call a
function with too many arguments. (Normally, extra arguments are
harmlessly ignored.)
.IP "\fB\-mregparm=\fR\fInum\fR" 4
.IP "\fB\-mstackrealign\fR" 4
.IX Item "-mstackrealign"
Realign the stack at entry. On the Intel x86, the \fB\-mstackrealign\fR
-option will generate an alternate prologue and epilogue that realigns the
+option generates an alternate prologue and epilogue that realigns the
run-time stack if necessary. This supports mixing legacy codes that keep
-a 4\-byte aligned stack with modern codes that keep a 16\-byte stack for
+4\-byte stack alignment with modern codes that keep 16\-byte stack alignment for
\&\s-1SSE\s0 compatibility. See also the attribute \f(CW\*(C`force_align_arg_pointer\*(C'\fR,
applicable to individual functions.
.IP "\fB\-mpreferred\-stack\-boundary=\fR\fInum\fR" 4
Attempt to keep the stack boundary aligned to a 2 raised to \fInum\fR
byte boundary. If \fB\-mpreferred\-stack\-boundary\fR is not specified,
the default is 4 (16 bytes or 128 bits).
+.Sp
+\&\fBWarning:\fR When generating code for the x86\-64 architecture with
+\&\s-1SSE\s0 extensions disabled, \fB\-mpreferred\-stack\-boundary=3\fR can be
+used to keep the stack boundary aligned to 8 byte boundary. Since
+x86\-64 \s-1ABI\s0 require 16 byte stack alignment, this is \s-1ABI\s0 incompatible and
+intended to be used in controlled environment where stack space is
+important limitation. This option will lead to wrong code when functions
+compiled with 16 byte stack alignment (such as functions from a standard
+library) are called with misaligned stack. In this case, \s-1SSE\s0
+instructions may lead to misaligned memory access traps. In addition,
+variable arguments will be handled incorrectly for 16 byte aligned
+objects (including x87 long double and _\|_int128), leading to wrong
+results. You must build all modules with
+\&\fB\-mpreferred\-stack\-boundary=3\fR, including any libraries. This
+includes the system libraries and startup modules.
.IP "\fB\-mincoming\-stack\-boundary=\fR\fInum\fR" 4
.IX Item "-mincoming-stack-boundary=num"
Assume the incoming stack is aligned to a 2 raised to \fInum\fR byte
boundary. If \fB\-mincoming\-stack\-boundary\fR is not specified,
-the one specified by \fB\-mpreferred\-stack\-boundary\fR will be used.
+the one specified by \fB\-mpreferred\-stack\-boundary\fR is used.
.Sp
-On Pentium and PentiumPro, \f(CW\*(C`double\*(C'\fR and \f(CW\*(C`long double\*(C'\fR values
+On Pentium and Pentium Pro, \f(CW\*(C`double\*(C'\fR and \f(CW\*(C`long double\*(C'\fR values
should be aligned to an 8\-byte boundary (see \fB\-malign\-double\fR) or
suffer significant run time performance penalties. On Pentium \s-1III\s0, the
Streaming \s-1SIMD\s0 Extension (\s-1SSE\s0) data type \f(CW\*(C`_\|_m128\*(C'\fR may not work
Further, every function must be generated such that it keeps the stack
aligned. Thus calling a function compiled with a higher preferred
stack boundary from a function compiled with a lower preferred stack
-boundary will most likely misalign the stack. It is recommended that
+boundary most likely misaligns the stack. It is recommended that
libraries that use callbacks always use the default setting.
.Sp
This extra alignment does consume extra stack space, and generally
.IX Item "-mlzcnt"
.IP "\fB\-mno\-lzcnt\fR" 4
.IX Item "-mno-lzcnt"
+.IP "\fB\-mrtm\fR" 4
+.IX Item "-mrtm"
.IP "\fB\-mtbm\fR" 4
.IX Item "-mtbm"
.IP "\fB\-mno\-tbm\fR" 4
.PD
These switches enable or disable the use of instructions in the \s-1MMX\s0, \s-1SSE\s0,
\&\s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1AVX\s0, \s-1AVX2\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0, F16C,
-\&\s-1FMA\s0, \s-1SSE4A\s0, \s-1FMA4\s0, \s-1XOP\s0, \s-1LWP\s0, \s-1ABM\s0, \s-1BMI\s0, \s-1BMI2\s0, \s-1LZCNT\s0 or 3DNow!
- extended instruction sets.
+\&\s-1FMA\s0, \s-1SSE4A\s0, \s-1FMA4\s0, \s-1XOP\s0, \s-1LWP\s0, \s-1ABM\s0, \s-1BMI\s0, \s-1BMI2\s0, \s-1LZCNT\s0, \s-1RTM\s0 or 3DNow!
+extended instruction sets.
These extensions are also available as built-in functions: see
\&\fBX86 Built-in Functions\fR, for details of the functions enabled and
disabled by these switches.
.Sp
-To have \s-1SSE/SSE2\s0 instructions generated automatically from floating-point
+To generate \s-1SSE/SSE2\s0 instructions automatically from floating-point
code (as opposed to 387 instructions), see \fB\-mfpmath=sse\fR.
.Sp
\&\s-1GCC\s0 depresses SSEx instructions when \fB\-mavx\fR is used. Instead, it
generates new \s-1AVX\s0 instructions or \s-1AVX\s0 equivalence for all SSEx instructions
when needed.
.Sp
-These options will enable \s-1GCC\s0 to use these extended instructions in
+These options enable \s-1GCC\s0 to use these extended instructions in
generated code, even without \fB\-mfpmath=sse\fR. Applications that
perform run-time \s-1CPU\s0 detection must compile separate files for each
supported architecture, using the appropriate flags. In particular,
.IX Item "-mvzeroupper"
This option instructs \s-1GCC\s0 to emit a \f(CW\*(C`vzeroupper\*(C'\fR instruction
before a transfer of control flow out of the function to minimize
-\&\s-1AVX\s0 to \s-1SSE\s0 transition penalty as well as remove unnecessary zeroupper
+the \s-1AVX\s0 to \s-1SSE\s0 transition penalty as well as remove unnecessary \f(CW\*(C`zeroupper\*(C'\fR
intrinsics.
.IP "\fB\-mprefer\-avx128\fR" 4
.IX Item "-mprefer-avx128"
256\-bit \s-1AVX\s0 instructions in the auto-vectorizer.
.IP "\fB\-mcx16\fR" 4
.IX Item "-mcx16"
-This option will enable \s-1GCC\s0 to use \s-1CMPXCHG16B\s0 instruction in generated code.
-\&\s-1CMPXCHG16B\s0 allows for atomic operations on 128\-bit double quadword (or oword)
-data types. This is useful for high resolution counters that could be updated
+This option enables \s-1GCC\s0 to generate \f(CW\*(C`CMPXCHG16B\*(C'\fR instructions.
+\&\f(CW\*(C`CMPXCHG16B\*(C'\fR allows for atomic operations on 128\-bit double quadword
+(or oword) data types.
+This is useful for high-resolution counters that can be updated
by multiple processors (or cores). This instruction is generated as part of
atomic built-in functions: see \fB_\|_sync Builtins\fR or
\&\fB_\|_atomic Builtins\fR for details.
.IP "\fB\-msahf\fR" 4
.IX Item "-msahf"
-This option will enable \s-1GCC\s0 to use \s-1SAHF\s0 instruction in generated 64\-bit code.
-Early Intel CPUs with Intel 64 lacked \s-1LAHF\s0 and \s-1SAHF\s0 instructions supported
-by \s-1AMD64\s0 until introduction of Pentium 4 G1 step in December 2005. \s-1LAHF\s0 and
-\&\s-1SAHF\s0 are load and store instructions, respectively, for certain status flags.
-In 64\-bit mode, \s-1SAHF\s0 instruction is used to optimize \f(CW\*(C`fmod\*(C'\fR, \f(CW\*(C`drem\*(C'\fR
-or \f(CW\*(C`remainder\*(C'\fR built-in functions: see \fBOther Builtins\fR for details.
+This option enables generation of \f(CW\*(C`SAHF\*(C'\fR instructions in 64\-bit code.
+Early Intel Pentium 4 CPUs with Intel 64 support,
+prior to the introduction of Pentium 4 G1 step in December 2005,
+lacked the \f(CW\*(C`LAHF\*(C'\fR and \f(CW\*(C`SAHF\*(C'\fR instructions
+which were supported by \s-1AMD64\s0.
+These are load and store instructions, respectively, for certain status flags.
+In 64\-bit mode, the \f(CW\*(C`SAHF\*(C'\fR instruction is used to optimize \f(CW\*(C`fmod\*(C'\fR,
+\&\f(CW\*(C`drem\*(C'\fR, and \f(CW\*(C`remainder\*(C'\fR built-in functions;
+see \fBOther Builtins\fR for details.
.IP "\fB\-mmovbe\fR" 4
.IX Item "-mmovbe"
-This option will enable \s-1GCC\s0 to use movbe instruction to implement
+This option enables use of the \f(CW\*(C`movbe\*(C'\fR instruction to implement
\&\f(CW\*(C`_\|_builtin_bswap32\*(C'\fR and \f(CW\*(C`_\|_builtin_bswap64\*(C'\fR.
.IP "\fB\-mcrc32\fR" 4
.IX Item "-mcrc32"
-This option will enable built-in functions, \f(CW\*(C`_\|_builtin_ia32_crc32qi\*(C'\fR,
-\&\f(CW\*(C`_\|_builtin_ia32_crc32hi\*(C'\fR. \f(CW\*(C`_\|_builtin_ia32_crc32si\*(C'\fR and
-\&\f(CW\*(C`_\|_builtin_ia32_crc32di\*(C'\fR to generate the crc32 machine instruction.
+This option enables built-in functions \f(CW\*(C`_\|_builtin_ia32_crc32qi\*(C'\fR,
+\&\f(CW\*(C`_\|_builtin_ia32_crc32hi\*(C'\fR, \f(CW\*(C`_\|_builtin_ia32_crc32si\*(C'\fR and
+\&\f(CW\*(C`_\|_builtin_ia32_crc32di\*(C'\fR to generate the \f(CW\*(C`crc32\*(C'\fR machine instruction.
.IP "\fB\-mrecip\fR" 4
.IX Item "-mrecip"
-This option will enable \s-1GCC\s0 to use \s-1RCPSS\s0 and \s-1RSQRTSS\s0 instructions (and their
-vectorized variants \s-1RCPPS\s0 and \s-1RSQRTPS\s0) with an additional Newton-Raphson step
-to increase precision instead of \s-1DIVSS\s0 and \s-1SQRTSS\s0 (and their vectorized
+This option enables use of \f(CW\*(C`RCPSS\*(C'\fR and \f(CW\*(C`RSQRTSS\*(C'\fR instructions
+(and their vectorized variants \f(CW\*(C`RCPPS\*(C'\fR and \f(CW\*(C`RSQRTPS\*(C'\fR)
+with an additional Newton-Raphson step
+to increase precision instead of \f(CW\*(C`DIVSS\*(C'\fR and \f(CW\*(C`SQRTSS\*(C'\fR
+(and their vectorized
variants) for single-precision floating-point arguments. These instructions
are generated only when \fB\-funsafe\-math\-optimizations\fR is enabled
together with \fB\-finite\-math\-only\fR and \fB\-fno\-trapping\-math\fR.
of the non-reciprocal instruction, the precision of the sequence can be
decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994).
.Sp
-Note that \s-1GCC\s0 implements \f(CW\*(C`1.0f/sqrtf(\f(CIx\f(CW)\*(C'\fR in terms of \s-1RSQRTSS\s0
-(or \s-1RSQRTPS\s0) already with \fB\-ffast\-math\fR (or the above option
+Note that \s-1GCC\s0 implements \f(CW\*(C`1.0f/sqrtf(\f(CIx\f(CW)\*(C'\fR in terms of \f(CW\*(C`RSQRTSS\*(C'\fR
+(or \f(CW\*(C`RSQRTPS\*(C'\fR) already with \fB\-ffast\-math\fR (or the above option
combination), and doesn't need \fB\-mrecip\fR.
.Sp
Also note that \s-1GCC\s0 emits the above sequence with additional Newton-Raphson step
doesn't need \fB\-mrecip\fR.
.IP "\fB\-mrecip=\fR\fIopt\fR" 4
.IX Item "-mrecip=opt"
-This option allows to control which reciprocal estimate instructions
-may be used. \fIopt\fR is a comma separated list of options, which may
-be preceded by a \f(CW\*(C`!\*(C'\fR to invert the option:
-\&\f(CW\*(C`all\*(C'\fR: enable all estimate instructions,
-\&\f(CW\*(C`default\*(C'\fR: enable the default instructions, equivalent to \fB\-mrecip\fR,
-\&\f(CW\*(C`none\*(C'\fR: disable all estimate instructions, equivalent to \fB\-mno\-recip\fR,
-\&\f(CW\*(C`div\*(C'\fR: enable the approximation for scalar division,
-\&\f(CW\*(C`vec\-div\*(C'\fR: enable the approximation for vectorized division,
-\&\f(CW\*(C`sqrt\*(C'\fR: enable the approximation for scalar square root,
-\&\f(CW\*(C`vec\-sqrt\*(C'\fR: enable the approximation for vectorized square root.
+This option controls which reciprocal estimate instructions
+may be used. \fIopt\fR is a comma-separated list of options, which may
+be preceded by a \fB!\fR to invert the option:
+.RS 4
+.IP "\fBall\fR" 4
+.IX Item "all"
+Enable all estimate instructions.
+.IP "\fBdefault\fR" 4
+.IX Item "default"
+Enable the default instructions, equivalent to \fB\-mrecip\fR.
+.IP "\fBnone\fR" 4
+.IX Item "none"
+Disable all estimate instructions, equivalent to \fB\-mno\-recip\fR.
+.IP "\fBdiv\fR" 4
+.IX Item "div"
+Enable the approximation for scalar division.
+.IP "\fBvec-div\fR" 4
+.IX Item "vec-div"
+Enable the approximation for vectorized division.
+.IP "\fBsqrt\fR" 4
+.IX Item "sqrt"
+Enable the approximation for scalar square root.
+.IP "\fBvec-sqrt\fR" 4
+.IX Item "vec-sqrt"
+Enable the approximation for vectorized square root.
+.RE
+.RS 4
.Sp
-So for example, \fB\-mrecip=all,!sqrt\fR would enable
+So, for example, \fB\-mrecip=all,!sqrt\fR enables
all of the reciprocal approximations, except for square root.
+.RE
.IP "\fB\-mveclibabi=\fR\fItype\fR" 4
.IX Item "-mveclibabi=type"
Specifies the \s-1ABI\s0 type to use for vectorizing intrinsics using an
-external library. Supported types are \f(CW\*(C`svml\*(C'\fR for the Intel short
-vector math library and \f(CW\*(C`acml\*(C'\fR for the \s-1AMD\s0 math core library style
-of interfacing. \s-1GCC\s0 will currently emit calls to \f(CW\*(C`vmldExp2\*(C'\fR,
+external library. Supported values for \fItype\fR are \fBsvml\fR
+for the Intel short
+vector math library and \fBacml\fR for the \s-1AMD\s0 math core library.
+To use this option, both \fB\-ftree\-vectorize\fR and
+\&\fB\-funsafe\-math\-optimizations\fR have to be enabled, and an \s-1SVML\s0 or \s-1ACML\s0
+ABI-compatible library must be specified at link time.
+.Sp
+\&\s-1GCC\s0 currently emits calls to \f(CW\*(C`vmldExp2\*(C'\fR,
\&\f(CW\*(C`vmldLn2\*(C'\fR, \f(CW\*(C`vmldLog102\*(C'\fR, \f(CW\*(C`vmldLog102\*(C'\fR, \f(CW\*(C`vmldPow2\*(C'\fR,
\&\f(CW\*(C`vmldTanh2\*(C'\fR, \f(CW\*(C`vmldTan2\*(C'\fR, \f(CW\*(C`vmldAtan2\*(C'\fR, \f(CW\*(C`vmldAtanh2\*(C'\fR,
\&\f(CW\*(C`vmldCbrt2\*(C'\fR, \f(CW\*(C`vmldSinh2\*(C'\fR, \f(CW\*(C`vmldSin2\*(C'\fR, \f(CW\*(C`vmldAsinh2\*(C'\fR,
\&\f(CW\*(C`vmlsAtan4\*(C'\fR, \f(CW\*(C`vmlsAtanh4\*(C'\fR, \f(CW\*(C`vmlsCbrt4\*(C'\fR, \f(CW\*(C`vmlsSinh4\*(C'\fR,
\&\f(CW\*(C`vmlsSin4\*(C'\fR, \f(CW\*(C`vmlsAsinh4\*(C'\fR, \f(CW\*(C`vmlsAsin4\*(C'\fR, \f(CW\*(C`vmlsCosh4\*(C'\fR,
\&\f(CW\*(C`vmlsCos4\*(C'\fR, \f(CW\*(C`vmlsAcosh4\*(C'\fR and \f(CW\*(C`vmlsAcos4\*(C'\fR for corresponding
-function type when \fB\-mveclibabi=svml\fR is used and \f(CW\*(C`_\|_vrd2_sin\*(C'\fR,
+function type when \fB\-mveclibabi=svml\fR is used, and \f(CW\*(C`_\|_vrd2_sin\*(C'\fR,
\&\f(CW\*(C`_\|_vrd2_cos\*(C'\fR, \f(CW\*(C`_\|_vrd2_exp\*(C'\fR, \f(CW\*(C`_\|_vrd2_log\*(C'\fR, \f(CW\*(C`_\|_vrd2_log2\*(C'\fR,
\&\f(CW\*(C`_\|_vrd2_log10\*(C'\fR, \f(CW\*(C`_\|_vrs4_sinf\*(C'\fR, \f(CW\*(C`_\|_vrs4_cosf\*(C'\fR,
\&\f(CW\*(C`_\|_vrs4_expf\*(C'\fR, \f(CW\*(C`_\|_vrs4_logf\*(C'\fR, \f(CW\*(C`_\|_vrs4_log2f\*(C'\fR,
-\&\f(CW\*(C`_\|_vrs4_log10f\*(C'\fR and \f(CW\*(C`_\|_vrs4_powf\*(C'\fR for corresponding function type
-when \fB\-mveclibabi=acml\fR is used. Both \fB\-ftree\-vectorize\fR and
-\&\fB\-funsafe\-math\-optimizations\fR have to be enabled. A \s-1SVML\s0 or \s-1ACML\s0 \s-1ABI\s0
-compatible library will have to be specified at link time.
+\&\f(CW\*(C`_\|_vrs4_log10f\*(C'\fR and \f(CW\*(C`_\|_vrs4_powf\*(C'\fR for the corresponding function type
+when \fB\-mveclibabi=acml\fR is used.
.IP "\fB\-mabi=\fR\fIname\fR" 4
.IX Item "-mabi=name"
Generate code for the specified calling convention. Permissible values
-are: \fBsysv\fR for the \s-1ABI\s0 used on GNU/Linux and other systems and
+are \fBsysv\fR for the \s-1ABI\s0 used on GNU/Linux and other systems, and
\&\fBms\fR for the Microsoft \s-1ABI\s0. The default is to use the Microsoft
-\&\s-1ABI\s0 when targeting Windows. On all other systems, the default is the
-\&\s-1SYSV\s0 \s-1ABI\s0. You can control this behavior for a specific function by
+\&\s-1ABI\s0 when targeting Microsoft Windows and the SysV \s-1ABI\s0 on all other systems.
+You can control this behavior for a specific function by
using the function attribute \fBms_abi\fR/\fBsysv_abi\fR.
.IP "\fB\-mtls\-dialect=\fR\fItype\fR" 4
.IX Item "-mtls-dialect=type"
improved scheduling and reduced dependencies.
.IP "\fB\-maccumulate\-outgoing\-args\fR" 4
.IX Item "-maccumulate-outgoing-args"
-If enabled, the maximum amount of space required for outgoing arguments will be
+If enabled, the maximum amount of space required for outgoing arguments is
computed in the function prologue. This is faster on most modern CPUs
because of reduced dependencies, improved scheduling and reduced stack usage
-when preferred stack boundary is not equal to 2. The drawback is a notable
+when the preferred stack boundary is not equal to 2. The drawback is a notable
increase in code size. This switch implies \fB\-mno\-push\-args\fR.
.IP "\fB\-mthreads\fR" 4
.IX Item "-mthreads"
-Support thread-safe exception handling on \fBMingw32\fR. Code that relies
+Support thread-safe exception handling on MinGW. Programs that rely
on thread-safe exception handling must compile and link all code with the
\&\fB\-mthreads\fR option. When compiling, \fB\-mthreads\fR defines
-\&\fB\-D_MT\fR; when linking, it links in a special thread helper library
-\&\fB\-lmingwthrd\fR which cleans up per thread exception handling data.
+\&\f(CW\*(C`\-D_MT\*(C'\fR; when linking, it links in a special thread helper library
+\&\fB\-lmingwthrd\fR which cleans up per-thread exception-handling data.
.IP "\fB\-mno\-align\-stringops\fR" 4
.IX Item "-mno-align-stringops"
-Do not align destination of inlined string operations. This switch reduces
+Do not align the destination of inlined string operations. This switch reduces
code size and improves performance in case the destination is already aligned,
but \s-1GCC\s0 doesn't know about it.
.IP "\fB\-minline\-all\-stringops\fR" 4
.IX Item "-minline-all-stringops"
By default \s-1GCC\s0 inlines string operations only when the destination is
known to be aligned to least a 4\-byte boundary.
-This enables more inlining, increase code
-size, but may improve performance of code that depends on fast memcpy, strlen
-and memset for short lengths.
+This enables more inlining and increases code
+size, but may improve performance of code that depends on fast
+\&\f(CW\*(C`memcpy\*(C'\fR, \f(CW\*(C`strlen\*(C'\fR,
+and \f(CW\*(C`memset\*(C'\fR for short lengths.
.IP "\fB\-minline\-stringops\-dynamically\fR" 4
.IX Item "-minline-stringops-dynamically"
For string operations of unknown size, use run-time checks with
inline code for small blocks and a library call for large blocks.
.IP "\fB\-mstringop\-strategy=\fR\fIalg\fR" 4
.IX Item "-mstringop-strategy=alg"
-Overwrite internal decision heuristic about particular algorithm to inline
-string operation with. The allowed values are \f(CW\*(C`rep_byte\*(C'\fR,
-\&\f(CW\*(C`rep_4byte\*(C'\fR, \f(CW\*(C`rep_8byte\*(C'\fR for expanding using i386 \f(CW\*(C`rep\*(C'\fR prefix
-of specified size, \f(CW\*(C`byte_loop\*(C'\fR, \f(CW\*(C`loop\*(C'\fR, \f(CW\*(C`unrolled_loop\*(C'\fR for
-expanding inline loop, \f(CW\*(C`libcall\*(C'\fR for always expanding library call.
+Override the internal decision heuristic for the particular algorithm to use
+for inlining string operations. The allowed values for \fIalg\fR are:
+.RS 4
+.IP "\fBrep_byte\fR" 4
+.IX Item "rep_byte"
+.PD 0
+.IP "\fBrep_4byte\fR" 4
+.IX Item "rep_4byte"
+.IP "\fBrep_8byte\fR" 4
+.IX Item "rep_8byte"
+.PD
+Expand using i386 \f(CW\*(C`rep\*(C'\fR prefix of the specified size.
+.IP "\fBbyte_loop\fR" 4
+.IX Item "byte_loop"
+.PD 0
+.IP "\fBloop\fR" 4
+.IX Item "loop"
+.IP "\fBunrolled_loop\fR" 4
+.IX Item "unrolled_loop"
+.PD
+Expand into an inline loop.
+.IP "\fBlibcall\fR" 4
+.IX Item "libcall"
+Always use a library call.
+.RE
+.RS 4
+.RE
.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4
.IX Item "-momit-leaf-frame-pointer"
Don't keep the frame pointer in a register for leaf functions. This
-avoids the instructions to save, set up and restore frame pointers and
+avoids the instructions to save, set up, and restore frame pointers and
makes an extra register available in leaf functions. The option
-\&\fB\-fomit\-frame\-pointer\fR removes the frame pointer for all functions,
+\&\fB\-fomit\-leaf\-frame\-pointer\fR removes the frame pointer for leaf functions,
which might make debugging harder.
.IP "\fB\-mtls\-direct\-seg\-refs\fR" 4
.IX Item "-mtls-direct-seg-refs"
Controls whether \s-1TLS\s0 variables may be accessed with offsets from the
\&\s-1TLS\s0 segment register (\f(CW%gs\fR for 32\-bit, \f(CW%fs\fR for 64\-bit),
or whether the thread base pointer must be added. Whether or not this
-is legal depends on the operating system, and whether it maps the
+is valid depends on the operating system, and whether it maps the
segment to cover the entire \s-1TLS\s0 area.
.Sp
-For systems that use \s-1GNU\s0 libc, the default is on.
+For systems that use the \s-1GNU\s0 C Library, the default is on.
.IP "\fB\-msse2avx\fR" 4
.IX Item "-msse2avx"
.PD 0
.IP "\fB\-mno\-fentry\fR" 4
.IX Item "-mno-fentry"
.PD
-If profiling is active \fB\-pg\fR put the profiling
-counter call before prologue.
+If profiling is active (\fB\-pg\fR), put the profiling
+counter call before the prologue.
Note: On x86 architectures the attribute \f(CW\*(C`ms_hook_prologue\*(C'\fR
isn't possible at the moment for \fB\-mfentry\fR and \fB\-pg\fR.
.IP "\fB\-m8bit\-idiv\fR" 4
Split 32\-byte \s-1AVX\s0 unaligned load and store.
.PP
These \fB\-m\fR switches are supported in addition to the above
-on \s-1AMD\s0 x86\-64 processors in 64\-bit environments.
+on x86\-64 processors in 64\-bit environments.
.IP "\fB\-m32\fR" 4
.IX Item "-m32"
.PD 0
.IX Item "-mx32"
.PD
Generate code for a 32\-bit or 64\-bit environment.
-The \fB\-m32\fR option sets int, long and pointer to 32 bits and
+The \fB\-m32\fR option sets \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, and pointer types
+to 32 bits, and
generates code that runs on any i386 system.
-The \fB\-m64\fR option sets int to 32 bits and long and pointer
-to 64 bits and generates code for \s-1AMD\s0's x86\-64 architecture.
-The \fB\-mx32\fR option sets int, long and pointer to 32 bits and
-generates code for \s-1AMD\s0's x86\-64 architecture.
-For darwin only the \fB\-m64\fR option turns off the \fB\-fno\-pic\fR
+.Sp
+The \fB\-m64\fR option sets \f(CW\*(C`int\*(C'\fR to 32 bits and \f(CW\*(C`long\*(C'\fR and pointer
+types to 64 bits, and generates code for the x86\-64 architecture.
+For Darwin only the \fB\-m64\fR option also turns off the \fB\-fno\-pic\fR
and \fB\-mdynamic\-no\-pic\fR options.
+.Sp
+The \fB\-mx32\fR option sets \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, and pointer types
+to 32 bits, and
+generates code for the x86\-64 architecture.
.IP "\fB\-mno\-red\-zone\fR" 4
.IX Item "-mno-red-zone"
-Do not use a so called red zone for x86\-64 code. The red zone is mandated
-by the x86\-64 \s-1ABI\s0, it is a 128\-byte area beyond the location of the
-stack pointer that will not be modified by signal or interrupt handlers
+Do not use a so-called \*(L"red zone\*(R" for x86\-64 code. The red zone is mandated
+by the x86\-64 \s-1ABI\s0; it is a 128\-byte area beyond the location of the
+stack pointer that is not modified by signal or interrupt handlers
and therefore can be used for temporary data without adjusting the stack
pointer. The flag \fB\-mno\-red\-zone\fR disables this red zone.
.IP "\fB\-mcmodel=small\fR" 4
This model has to be used for Linux kernel code.
.IP "\fB\-mcmodel=medium\fR" 4
.IX Item "-mcmodel=medium"
-Generate code for the medium model: The program is linked in the lower 2
+Generate code for the medium model: the program is linked in the lower 2
\&\s-1GB\s0 of the address space. Small symbols are also placed there. Symbols
with sizes larger than \fB\-mlarge\-data\-threshold\fR are put into
-large data or bss sections and can be located above 2GB. Programs can
+large data or \s-1BSS\s0 sections and can be located above 2GB. Programs can
be statically or dynamically linked.
.IP "\fB\-mcmodel=large\fR" 4
.IX Item "-mcmodel=large"
-Generate code for the large model: This model makes no assumptions
+Generate code for the large model. This model makes no assumptions
about addresses and sizes of sections.
+.IP "\fB\-maddress\-mode=long\fR" 4
+.IX Item "-maddress-mode=long"
+Generate code for long address mode. This is only supported for 64\-bit
+and x32 environments. It is the default address mode for 64\-bit
+environments.
+.IP "\fB\-maddress\-mode=short\fR" 4
+.IX Item "-maddress-mode=short"
+Generate code for short address mode. This is only supported for 32\-bit
+and x32 environments. It is the default address mode for 32\-bit and
+x32 environments.
.PP
\fIi386 and x86\-64 Windows Options\fR
.IX Subsection "i386 and x86-64 Windows Options"
.PP
-These additional options are available for Windows targets:
+These additional options are available for Microsoft Windows targets:
.IP "\fB\-mconsole\fR" 4
.IX Item "-mconsole"
-This option is available for Cygwin and MinGW targets. It
+This option
specifies that a console application is to be generated, by
instructing the linker to set the \s-1PE\s0 header subsystem type
required for console applications.
-This is the default behavior for Cygwin and MinGW targets.
+This option is available for Cygwin and MinGW targets and is
+enabled by default on those targets.
.IP "\fB\-mdll\fR" 4
.IX Item "-mdll"
This option is available for Cygwin and MinGW targets. It
-specifies that a \s-1DLL\s0 \- a dynamic link library \- is to be
+specifies that a DLL\-\-\-a dynamic link library\-\-\-is to be
generated, enabling the selection of the required runtime
startup object and entry point.
.IP "\fB\-mnop\-fun\-dllimport\fR" 4
.IX Item "-mnop-fun-dllimport"
This option is available for Cygwin and MinGW targets. It
-specifies that the dllimport attribute should be ignored.
+specifies that the \f(CW\*(C`dllimport\*(C'\fR attribute should be ignored.
.IP "\fB\-mthread\fR" 4
.IX Item "-mthread"
This option is available for MinGW targets. It specifies
that MinGW-specific thread support is to be used.
.IP "\fB\-municode\fR" 4
.IX Item "-municode"
-This option is available for mingw\-w64 targets. It specifies
-that the \s-1UNICODE\s0 macro is getting pre-defined and that the
-unicode capable runtime startup code is chosen.
+This option is available for MinGW\-w64 targets. It causes
+the \f(CW\*(C`UNICODE\*(C'\fR preprocessor macro to be predefined, and
+chooses Unicode-capable runtime startup code.
.IP "\fB\-mwin32\fR" 4
.IX Item "-mwin32"
This option is available for Cygwin and MinGW targets. It
-specifies that the typical Windows pre-defined macros are to
+specifies that the typical Microsoft Windows predefined macros are to
be set in the pre-processor, but does not influence the choice
of runtime library/startup code.
.IP "\fB\-mwindows\fR" 4
.IP "\fB\-fno\-set\-stack\-executable\fR" 4
.IX Item "-fno-set-stack-executable"
This option is available for MinGW targets. It specifies that
-the executable flag for stack used by nested functions isn't
+the executable flag for the stack used by nested functions isn't
set. This is necessary for binaries running in kernel mode of
-Windows, as there the user32 \s-1API\s0, which is used to set executable
+Microsoft Windows, as there the User32 \s-1API\s0, which is used to set executable
privileges, isn't available.
+.IP "\fB\-fwritable\-relocated\-rdata\fR" 4
+.IX Item "-fwritable-relocated-rdata"
+This option is available for MinGW and Cygwin targets. It specifies
+that relocated-data in read-only section is put into .data
+section. This is a necessary for older runtimes not supporting
+modification of .rdata sections for pseudo-relocation.
.IP "\fB\-mpe\-aligned\-commons\fR" 4
.IX Item "-mpe-aligned-commons"
This option is available for Cygwin and MinGW targets. It
specifies that the \s-1GNU\s0 extension to the \s-1PE\s0 file format that
permits the correct alignment of \s-1COMMON\s0 variables should be
-used when generating code. It will be enabled by default if
+used when generating code. It is enabled by default if
\&\s-1GCC\s0 detects that the target assembler found during configuration
supports the feature.
.PP
using the maximum throughput algorithm.
.IP "\fB\-mno\-inline\-sqrt\fR" 4
.IX Item "-mno-inline-sqrt"
-Do not generate inline code for sqrt.
+Do not generate inline code for \f(CW\*(C`sqrt\*(C'\fR.
.IP "\fB\-mfused\-madd\fR" 4
.IX Item "-mfused-madd"
.PD 0
.IP "\fB\-mdwarf2\-asm\fR" 4
.IX Item "-mdwarf2-asm"
.PD
-Don't (or do) generate assembler code for the \s-1DWARF2\s0 line number debugging
+Don't (or do) generate assembler code for the \s-1DWARF\s0 2 line number debugging
info. This may be useful when not using the \s-1GNU\s0 assembler.
.IP "\fB\-mearly\-stop\-bits\fR" 4
.IX Item "-mearly-stop-bits"
.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4
.IX Item "-mfixed-range=register-range"
Generate code treating the given register range as fixed registers.
-A fixed register is one that the register allocator can not use. This is
+A fixed register is one that the register allocator cannot use. This is
useful when compiling kernel code. A register range is specified as
two registers separated by a dash. Multiple register ranges can be
specified separated by a comma.
.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4
.IX Item "-mtune=cpu-type"
Tune the instruction scheduling for a particular \s-1CPU\s0, Valid values are
-itanium, itanium1, merced, itanium2, and mckinley.
+\&\fBitanium\fR, \fBitanium1\fR, \fBmerced\fR, \fBitanium2\fR,
+and \fBmckinley\fR.
.IP "\fB\-milp32\fR" 4
.IX Item "-milp32"
.PD 0
.IX Item "-msched-br-data-spec"
.PD
(Dis/En)able data speculative scheduling before reload.
-This will result in generation of the ld.a instructions and
-the corresponding check instructions (ld.c / chk.a).
+This results in generation of \f(CW\*(C`ld.a\*(C'\fR instructions and
+the corresponding check instructions (\f(CW\*(C`ld.c\*(C'\fR / \f(CW\*(C`chk.a\*(C'\fR).
The default is 'disable'.
.IP "\fB\-msched\-ar\-data\-spec\fR" 4
.IX Item "-msched-ar-data-spec"
.IX Item "-mno-sched-ar-data-spec"
.PD
(En/Dis)able data speculative scheduling after reload.
-This will result in generation of the ld.a instructions and
-the corresponding check instructions (ld.c / chk.a).
+This results in generation of \f(CW\*(C`ld.a\*(C'\fR instructions and
+the corresponding check instructions (\f(CW\*(C`ld.c\*(C'\fR / \f(CW\*(C`chk.a\*(C'\fR).
The default is 'enable'.
.IP "\fB\-mno\-sched\-control\-spec\fR" 4
.IX Item "-mno-sched-control-spec"
.PD
(Dis/En)able control speculative scheduling. This feature is
available only during region scheduling (i.e. before reload).
-This will result in generation of the ld.s instructions and
-the corresponding check instructions chk.s .
+This results in generation of the \f(CW\*(C`ld.s\*(C'\fR instructions and
+the corresponding check instructions \f(CW\*(C`chk.s\*(C'\fR.
The default is 'disable'.
.IP "\fB\-msched\-br\-in\-data\-spec\fR" 4
.IX Item "-msched-br-in-data-spec"
.IP "\fB\-msched\-prefer\-non\-data\-spec\-insns\fR" 4
.IX Item "-msched-prefer-non-data-spec-insns"
.PD
-If enabled, data speculative instructions will be chosen for schedule
-only if there are no other choices at the moment. This will make
+If enabled, data-speculative instructions are chosen for schedule
+only if there are no other choices at the moment. This makes
the use of the data speculation much more conservative.
The default is 'disable'.
.IP "\fB\-mno\-sched\-prefer\-non\-control\-spec\-insns\fR" 4
.IP "\fB\-msched\-prefer\-non\-control\-spec\-insns\fR" 4
.IX Item "-msched-prefer-non-control-spec-insns"
.PD
-If enabled, control speculative instructions will be chosen for schedule
-only if there are no other choices at the moment. This will make
+If enabled, control-speculative instructions are chosen for schedule
+only if there are no other choices at the moment. This makes
the use of the control speculation much more conservative.
The default is 'disable'.
.IP "\fB\-mno\-sched\-count\-spec\-in\-critical\-path\fR" 4
.IP "\fB\-msched\-count\-spec\-in\-critical\-path\fR" 4
.IX Item "-msched-count-spec-in-critical-path"
.PD
-If enabled, speculative dependencies will be considered during
-computation of the instructions priorities. This will make the use of the
+If enabled, speculative dependencies are considered during
+computation of the instructions priorities. This makes the use of the
speculation a bit more conservative.
The default is 'disable'.
.IP "\fB\-msched\-spec\-ldc\fR" 4
The default value is 1.
.IP "\fB\-msched\-max\-memory\-insns\-hard\-limit\fR" 4
.IX Item "-msched-max-memory-insns-hard-limit"
-Disallow more than `msched\-max\-memory\-insns' in instruction group.
-Otherwise, limit is `soft' meaning that we would prefer non-memory operations
-when limit is reached but may still schedule memory operations.
-.PP
-\fI\s-1IA\-64/VMS\s0 Options\fR
-.IX Subsection "IA-64/VMS Options"
-.PP
-These \fB\-m\fR options are defined for the \s-1IA\-64/VMS\s0 implementations:
-.IP "\fB\-mvms\-return\-codes\fR" 4
-.IX Item "-mvms-return-codes"
-Return \s-1VMS\s0 condition codes from main. The default is to return \s-1POSIX\s0
-style condition (e.g. error) codes.
-.IP "\fB\-mdebug\-main=\fR\fIprefix\fR" 4
-.IX Item "-mdebug-main=prefix"
-Flag the first routine whose name starts with \fIprefix\fR as the main
-routine for the debugger.
-.IP "\fB\-mmalloc64\fR" 4
-.IX Item "-mmalloc64"
-Default to 64\-bit memory allocation routines.
+Makes the limit specified by \fBmsched-max-memory-insns\fR a hard limit,
+disallowing more than that number in an instruction group.
+Otherwise, the limit is \*(L"soft\*(R", meaning that non-memory operations
+are preferred when the limit is reached, but memory operations may still
+be scheduled.
.PP
\fI\s-1LM32\s0 Options\fR
.IX Subsection "LM32 Options"
.PP
-These \fB\-m\fR options are defined for the Lattice Mico32 architecture:
+These \fB\-m\fR options are defined for the LatticeMico32 architecture:
.IP "\fB\-mbarrel\-shift\-enabled\fR" 4
.IX Item "-mbarrel-shift-enabled"
Enable barrel-shift instructions.
runtime library for whatever I/O functions are needed.
.IP "\fB\-memregs=\fR\fInumber\fR" 4
.IX Item "-memregs=number"
-Specifies the number of memory-based pseudo-registers \s-1GCC\s0 will use
-during code generation. These pseudo-registers will be used like real
+Specifies the number of memory-based pseudo-registers \s-1GCC\s0 uses
+during code generation. These pseudo-registers are used like real
registers, so there is a tradeoff between \s-1GCC\s0's ability to fit the
code into available registers, and the performance penalty of using
memory instead of registers. Note that all modules in a program must
be compiled with the same value for this option. Because of that, you
-must not use this option with the default runtime libraries gcc
-builds.
+must not use this option with \s-1GCC\s0's default runtime libraries.
.PP
\fIM32R/D Options\fR
.IX Subsection "M32R/D Options"
.IP "\fB\-mmodel=medium\fR" 4
.IX Item "-mmodel=medium"
Assume objects may be anywhere in the 32\-bit address space (the compiler
-will generate \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and
+generates \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and
assume all subroutines are reachable with the \f(CW\*(C`bl\*(C'\fR instruction.
.IP "\fB\-mmodel=large\fR" 4
.IX Item "-mmodel=large"
Assume objects may be anywhere in the 32\-bit address space (the compiler
-will generate \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and
+generates \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and
assume subroutines may not be reachable with the \f(CW\*(C`bl\*(C'\fR instruction
-(the compiler will generate the much slower \f(CW\*(C`seth/add3/jl\*(C'\fR
+(the compiler generates the much slower \f(CW\*(C`seth/add3/jl\*(C'\fR
instruction sequence).
.IP "\fB\-msdata=none\fR" 4
.IX Item "-msdata=none"
-Disable use of the small data area. Variables will be put into
-one of \fB.data\fR, \fBbss\fR, or \fB.rodata\fR (unless the
+Disable use of the small data area. Variables are put into
+one of \fB.data\fR, \fB.bss\fR, or \fB.rodata\fR (unless the
\&\f(CW\*(C`section\*(C'\fR attribute has been specified).
This is the default.
.Sp
.IP "\fB\-G\fR \fInum\fR" 4
.IX Item "-G num"
Put global and static objects less than or equal to \fInum\fR bytes
-into the small data or bss sections instead of the normal data or bss
+into the small data or \s-1BSS\s0 sections instead of the normal data or \s-1BSS\s0
sections. The default value of \fInum\fR is 8.
The \fB\-msdata\fR option must be set to one of \fBsdata\fR or \fBuse\fR
for this option to have any effect.
.Sp
All modules should be compiled with the same \fB\-G\fR \fInum\fR value.
Compiling with different values of \fInum\fR may or may not work; if it
-doesn't the linker will give an error message\-\-\-incorrect code will not be
+doesn't the linker gives an error message\-\-\-incorrect code is not
generated.
.IP "\fB\-mdebug\fR" 4
.IX Item "-mdebug"
-Makes the M32R specific code in the compiler display some statistics
+Makes the M32R\-specific code in the compiler display some statistics
that might help in debugging programs.
.IP "\fB\-malign\-loops\fR" 4
.IX Item "-malign-loops"
or 2.
.IP "\fB\-mbranch\-cost=\fR\fInumber\fR" 4
.IX Item "-mbranch-cost=number"
-\&\fInumber\fR can only be 1 or 2. If it is 1 then branches will be
-preferred over conditional code, if it is 2, then the opposite will
-apply.
+\&\fInumber\fR can only be 1 or 2. If it is 1 then branches are
+preferred over conditional code, if it is 2, then the opposite applies.
.IP "\fB\-mflush\-trap=\fR\fInumber\fR" 4
.IX Item "-mflush-trap=number"
Specifies the trap number to use to flush the cache. The default is
.IX Item "-mflush-func=name"
Specifies the name of the operating system function to call to flush
the cache. The default is \fI_flush_cache\fR, but a function call
-will only be used if a trap is not available.
+is only used if a trap is not available.
.IP "\fB\-mno\-flush\-func\fR" 4
.IX Item "-mno-flush-func"
Indicates that there is no \s-1OS\s0 function for flushing the cache.
and the permissible values are: \fBisaa\fR, \fBisaaplus\fR,
\&\fBisab\fR and \fBisac\fR.
.Sp
-gcc defines a macro \fB_\|_mcf\fR\fIarch\fR\fB_\|_\fR whenever it is generating
+\&\s-1GCC\s0 defines a macro \fB_\|_mcf\fR\fIarch\fR\fB_\|_\fR whenever it is generating
code for a ColdFire target. The \fIarch\fR in this macro is one of the
\&\fB\-march\fR arguments given above.
.Sp
.IP "Family : \fB\-mcpu\fR arguments" 4
.IX Item "Family : -mcpu arguments"
.PD 0
-.IP "\fB51\fR : \fB51\fR \fB51ac\fR \fB51cn\fR \fB51em\fR \fB51qe\fR" 4
-.IX Item "51 : 51 51ac 51cn 51em 51qe"
+.IP "\fB51\fR : \fB51\fR \fB51ac\fR \fB51ag\fR \fB51cn\fR \fB51em\fR \fB51je\fR \fB51jf\fR \fB51jg\fR \fB51jm\fR \fB51mm\fR \fB51qe\fR \fB51qm\fR" 4
+.IX Item "51 : 51 51ac 51ag 51cn 51em 51je 51jf 51jg 51jm 51mm 51qe 51qm"
.IP "\fB5206\fR : \fB5202\fR \fB5204\fR \fB5206\fR" 4
.IX Item "5206 : 5202 5204 5206"
.IP "\fB5206e\fR : \fB5206e\fR" 4
\&\fIarch\fR is compatible with \fIcpu\fR. Other combinations of
\&\fB\-mcpu\fR and \fB\-march\fR are rejected.
.Sp
-gcc defines the macro \fB_\|_mcf_cpu_\fR\fIcpu\fR when ColdFire target
+\&\s-1GCC\s0 defines the macro \fB_\|_mcf_cpu_\fR\fIcpu\fR when ColdFire target
\&\fIcpu\fR is selected. It also defines \fB_\|_mcf_family_\fR\fIfamily\fR,
where the value of \fIfamily\fR is given by the table above.
.RE
.IP "\fB\-mtune=\fR\fItune\fR" 4
.IX Item "-mtune=tune"
-Tune the code for a particular microarchitecture, within the
+Tune the code for a particular microarchitecture within the
constraints set by \fB\-march\fR and \fB\-mcpu\fR.
The M680x0 microarchitectures are: \fB68000\fR, \fB68010\fR,
\&\fB68020\fR, \fB68030\fR, \fB68040\fR, \fB68060\fR
as well. These two options select the same tuning decisions as
\&\fB\-m68020\-40\fR and \fB\-m68020\-60\fR respectively.
.Sp
-gcc defines the macros \fB_\|_mc\fR\fIarch\fR and \fB_\|_mc\fR\fIarch\fR\fB_\|_\fR
+\&\s-1GCC\s0 defines the macros \fB_\|_mc\fR\fIarch\fR and \fB_\|_mc\fR\fIarch\fR\fB_\|_\fR
when tuning for 680x0 architecture \fIarch\fR. It also defines
\&\fBmc\fR\fIarch\fR unless either \fB\-ansi\fR or a non-GNU \fB\-std\fR
-option is used. If gcc is tuning for a range of architectures,
+option is used. If \s-1GCC\s0 is tuning for a range of architectures,
as selected by \fB\-mtune=68020\-40\fR or \fB\-mtune=68020\-60\fR,
it defines the macros for every architecture in the range.
.Sp
-gcc also defines the macro \fB_\|_m\fR\fIuarch\fR\fB_\|_\fR when tuning for
+\&\s-1GCC\s0 also defines the macro \fB_\|_m\fR\fIuarch\fR\fB_\|_\fR when tuning for
ColdFire microarchitecture \fIuarch\fR, where \fIuarch\fR is one
of the arguments given above.
.IP "\fB\-m68000\fR" 4
example, the default is \*(L"off\*(R" for \fB\-mcpu=5206\fR and \*(L"on\*(R" for
\&\fB\-mcpu=5206e\fR.
.Sp
-gcc defines the macro \fB_\|_mcfhwdiv_\|_\fR when this option is enabled.
+\&\s-1GCC\s0 defines the macro \fB_\|_mcfhwdiv_\|_\fR when this option is enabled.
.IP "\fB\-mshort\fR" 4
.IX Item "-mshort"
Consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide, like \f(CW\*(C`short int\*(C'\fR.
.Sp
Also, you must provide function prototypes for all functions that
take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR);
-otherwise incorrect code will be generated for calls to those
+otherwise incorrect code is generated for calls to those
functions.
.Sp
-In addition, seriously incorrect code will result if you call a
+In addition, seriously incorrect code results if you call a
function with too many arguments. (Normally, extra arguments are
harmlessly ignored.)
.Sp
Aligning variables on 32\-bit boundaries produces code that runs somewhat
faster on processors with 32\-bit busses at the expense of more memory.
.Sp
-\&\fBWarning:\fR if you use the \fB\-malign\-int\fR switch, \s-1GCC\s0 will
-align structures containing the above types differently than
+\&\fBWarning:\fR if you use the \fB\-malign\-int\fR switch, \s-1GCC\s0
+aligns structures containing the above types differently than
most published application binary interface specifications for the m68k.
.IP "\fB\-mpcrel\fR" 4
.IX Item "-mpcrel"
.IP "\fB\-mstrict\-align\fR" 4
.IX Item "-mstrict-align"
.PD
-Do not (do) assume that unaligned memory references will be handled by
+Do not (do) assume that unaligned memory references are handled by
the system.
.IP "\fB\-msep\-data\fR" 4
.IX Item "-msep-data"
Generate code that allows the data segment to be located in a different
-area of memory from the text segment. This allows for execute in place in
+area of memory from the text segment. This allows for execute-in-place in
an environment without virtual memory management. This option implies
\&\fB\-fPIC\fR.
.IP "\fB\-mno\-sep\-data\fR" 4
.IP "\fB\-mid\-shared\-library\fR" 4
.IX Item "-mid-shared-library"
Generate code that supports shared libraries via the library \s-1ID\s0 method.
-This allows for execute in place and shared libraries in an environment
+This allows for execute-in-place and shared libraries in an environment
without virtual memory management. This option implies \fB\-fPIC\fR.
.IP "\fB\-mno\-id\-shared\-library\fR" 4
.IX Item "-mno-id-shared-library"
-Generate code that doesn't assume \s-1ID\s0 based shared libraries are being used.
+Generate code that doesn't assume ID-based shared libraries are being used.
This is the default.
.IP "\fB\-mshared\-library\-id=n\fR" 4
.IX Item "-mshared-library-id=n"
-Specified the identification number of the \s-1ID\s0 based shared library being
-compiled. Specifying a value of 0 will generate more compact code, specifying
-other values will force the allocation of that number to the current
-library but is no more space or time efficient than omitting this option.
+Specifies the identification number of the ID-based shared library being
+compiled. Specifying a value of 0 generates more compact code; specifying
+other values forces the allocation of that number to the current
+library, but is no more space\- or time-efficient than omitting this option.
.IP "\fB\-mxgot\fR" 4
.IX Item "-mxgot"
.PD 0
.IP "\fB\-mno\-relax\-immediate\fR" 4
.IX Item "-mno-relax-immediate"
.PD
-Allow arbitrary sized immediates in bit operations.
+Allow arbitrary-sized immediates in bit operations.
.IP "\fB\-mwide\-bitfields\fR" 4
.IX Item "-mwide-bitfields"
.PD 0
.IP "\fB\-mno\-wide\-bitfields\fR" 4
.IX Item "-mno-wide-bitfields"
.PD
-Always treat bit-fields as int-sized.
+Always treat bit-fields as \f(CW\*(C`int\*(C'\fR\-sized.
.IP "\fB\-m4byte\-functions\fR" 4
.IX Item "-m4byte-functions"
.PD 0
between two registers.
.IP "\fB\-mall\-opts\fR" 4
.IX Item "-mall-opts"
-Enables all the optional instructions \- average, multiply, divide, bit
+Enables all the optional instructions\-\-\-average, multiply, divide, bit
operations, leading zero, absolute difference, min/max, clip, and
saturation.
.IP "\fB\-maverage\fR" 4
registers.
.IP "\fB\-mbased=\fR\fIn\fR" 4
.IX Item "-mbased=n"
-Variables of size \fIn\fR bytes or smaller will be placed in the
+Variables of size \fIn\fR bytes or smaller are placed in the
\&\f(CW\*(C`.based\*(C'\fR section by default. Based variables use the \f(CW$tp\fR
register as a base register, and there is a 128\-byte limit to the
\&\f(CW\*(C`.based\*(C'\fR section.
.IP "\fB\-mbitops\fR" 4
.IX Item "-mbitops"
-Enables the bit operation instructions \- bit test (\f(CW\*(C`btstm\*(C'\fR), set
+Enables the bit operation instructions\-\-\-bit test (\f(CW\*(C`btstm\*(C'\fR), set
(\f(CW\*(C`bsetm\*(C'\fR), clear (\f(CW\*(C`bclrm\*(C'\fR), invert (\f(CW\*(C`bnotm\*(C'\fR), and
test-and-set (\f(CW\*(C`tas\*(C'\fR).
.IP "\fB\-mc=\fR\fIname\fR" 4
.IX Item "-mc=name"
-Selects which section constant data will be placed in. \fIname\fR may
+Selects which section constant data is placed in. \fIname\fR may
be \f(CW\*(C`tiny\*(C'\fR, \f(CW\*(C`near\*(C'\fR, or \f(CW\*(C`far\*(C'\fR.
.IP "\fB\-mclip\fR" 4
.IX Item "-mclip"
useful unless you also provide \f(CW\*(C`\-mminmax\*(C'\fR.
.IP "\fB\-mconfig=\fR\fIname\fR" 4
.IX Item "-mconfig=name"
-Selects one of the build-in core configurations. Each MeP chip has
+Selects one of the built-in core configurations. Each MeP chip has
one or more modules in it; each module has a core \s-1CPU\s0 and a variety of
coprocessors, optional instructions, and peripherals. The
\&\f(CW\*(C`MeP\-Integrator\*(C'\fR tool, not part of \s-1GCC\s0, provides these
this option, functions default to the \f(CW\*(C`.near\*(C'\fR section.
.IP "\fB\-mtiny=\fR\fIn\fR" 4
.IX Item "-mtiny=n"
-Variables that are \fIn\fR bytes or smaller will be allocated to the
+Variables that are \fIn\fR bytes or smaller are allocated to the
\&\f(CW\*(C`.tiny\*(C'\fR section. These variables use the \f(CW$gp\fR base
register. The default for this option is 4, but note that there's a
65536\-byte limit to the \f(CW\*(C`.tiny\*(C'\fR section.
This option is deprecated. Use \fB\-fno\-zero\-initialized\-in\-bss\fR instead.
.IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4
.IX Item "-mcpu=cpu-type"
-Use features of and schedule code for given \s-1CPU\s0.
+Use features of, and schedule code for, the given \s-1CPU\s0.
Supported values are in the format \fBv\fR\fIX\fR\fB.\fR\fI\s-1YY\s0\fR\fB.\fR\fIZ\fR,
where \fIX\fR is a major version, \fI\s-1YY\s0\fR is the minor version, and
\&\fIZ\fR is compatibility code. Example values are \fBv3.00.a\fR,
Use table lookup optimization for small signed integer divisions.
.IP "\fB\-mxl\-stack\-check\fR" 4
.IX Item "-mxl-stack-check"
-This option is deprecated. Use \-fstack\-check instead.
+This option is deprecated. Use \fB\-fstack\-check\fR instead.
.IP "\fB\-mxl\-gp\-opt\fR" 4
.IX Item "-mxl-gp-opt"
-Use \s-1GP\s0 relative sdata/sbss sections.
+Use GP-relative \f(CW\*(C`.sdata\*(C'\fR/\f(CW\*(C`.sbss\*(C'\fR sections.
.IP "\fB\-mxl\-multiply\-high\fR" 4
.IX Item "-mxl-multiply-high"
Use multiply high instructions for high part of 32x32 multiply.
.IP "\fB\-mxl\-float\-sqrt\fR" 4
.IX Item "-mxl-float-sqrt"
Use hardware floating-point square root instruction.
+.IP "\fB\-mbig\-endian\fR" 4
+.IX Item "-mbig-endian"
+Generate code for a big-endian target.
+.IP "\fB\-mlittle\-endian\fR" 4
+.IX Item "-mlittle-endian"
+Generate code for a little-endian target.
+.IP "\fB\-mxl\-reorder\fR" 4
+.IX Item "-mxl-reorder"
+Use reorder instructions (swap and byte reversed load/store).
.IP "\fB\-mxl\-mode\-\fR\fIapp-model\fR" 4
.IX Item "-mxl-mode-app-model"
Select application model \fIapp-model\fR. Valid models are
.IX Item "xmdstub"
for use with Xilinx Microprocessor Debugger (\s-1XMD\s0) based
software intrusive debug agent called xmdstub. This uses startup file
-\&\fIcrt1.o\fR and sets the start address of the program to be 0x800.
+\&\fIcrt1.o\fR and sets the start address of the program to 0x800.
.IP "\fBbootstrap\fR" 4
.IX Item "bootstrap"
for applications that are loaded using a bootloader.
configurations.
.IP "\fB\-march=\fR\fIarch\fR" 4
.IX Item "-march=arch"
-Generate code that will run on \fIarch\fR, which can be the name of a
+Generate code that runs on \fIarch\fR, which can be the name of a
generic \s-1MIPS\s0 \s-1ISA\s0, or the name of a particular processor.
The \s-1ISA\s0 names are:
\&\fBmips1\fR, \fBmips2\fR, \fBmips3\fR, \fBmips4\fR,
\&\fB20kc\fR,
\&\fB24kc\fR, \fB24kf2_1\fR, \fB24kf1_1\fR,
\&\fB24kec\fR, \fB24kef2_1\fR, \fB24kef1_1\fR,
-\&\fB34kc\fR, \fB34kf2_1\fR, \fB34kf1_1\fR,
+\&\fB34kc\fR, \fB34kf2_1\fR, \fB34kf1_1\fR, \fB34kn\fR,
\&\fB74kc\fR, \fB74kf2_1\fR, \fB74kf1_1\fR, \fB74kf3_2\fR,
\&\fB1004kc\fR, \fB1004kf2_1\fR, \fB1004kf1_1\fR,
\&\fBloongson2e\fR, \fBloongson2f\fR, \fBloongson3a\fR,
\&\fBocteon\fR, \fBocteon+\fR, \fBocteon2\fR,
\&\fBorion\fR,
\&\fBr2000\fR, \fBr3000\fR, \fBr3900\fR, \fBr4000\fR, \fBr4400\fR,
-\&\fBr4600\fR, \fBr4650\fR, \fBr6000\fR, \fBr8000\fR,
+\&\fBr4600\fR, \fBr4650\fR, \fBr4700\fR, \fBr6000\fR, \fBr8000\fR,
\&\fBrm7000\fR, \fBrm9000\fR,
\&\fBr10000\fR, \fBr12000\fR, \fBr14000\fR, \fBr16000\fR,
\&\fBsb1\fR,
\&\fBsr71000\fR,
\&\fBvr4100\fR, \fBvr4111\fR, \fBvr4120\fR, \fBvr4130\fR, \fBvr4300\fR,
-\&\fBvr5000\fR, \fBvr5400\fR, \fBvr5500\fR
-and \fBxlr\fR.
+\&\fBvr5000\fR, \fBvr5400\fR, \fBvr5500\fR,
+\&\fBxlr\fR and \fBxlp\fR.
The special value \fBfrom-abi\fR selects the
most compatible architecture for the selected \s-1ABI\s0 (that is,
\&\fBmips1\fR for 32\-bit ABIs and \fBmips3\fR for 64\-bit ABIs).
.Sp
-Native Linux/GNU and \s-1IRIX\s0 toolchains also support the value \fBnative\fR,
+The native Linux/GNU toolchain also supports the value \fBnative\fR,
which selects the best architecture option for the host processor.
\&\fB\-march=native\fR has no effect if \s-1GCC\s0 does not recognize
the processor.
is \fB_MIPS_ARCH\fR, which gives the name of target architecture, as
a string. The second has the form \fB_MIPS_ARCH_\fR\fIfoo\fR,
where \fIfoo\fR is the capitalized value of \fB_MIPS_ARCH\fR.
-For example, \fB\-march=r2000\fR will set \fB_MIPS_ARCH\fR
-to \fB\*(L"r2000\*(R"\fR and define the macro \fB_MIPS_ARCH_R2000\fR.
+For example, \fB\-march=r2000\fR sets \fB_MIPS_ARCH\fR
+to \fB\*(L"r2000\*(R"\fR and defines the macro \fB_MIPS_ARCH_R2000\fR.
.Sp
Note that the \fB_MIPS_ARCH\fR macro uses the processor names given
-above. In other words, it will have the full prefix and will not
+above. In other words, it has the full prefix and does not
abbreviate \fB000\fR as \fBk\fR. In the case of \fBfrom-abi\fR,
the macro names the resolved architecture (either \fB\*(L"mips1\*(R"\fR or
\&\fB\*(L"mips3\*(R"\fR). It names the default architecture when no
operations. The list of \fIarch\fR values is the same as for
\&\fB\-march\fR.
.Sp
-When this option is not used, \s-1GCC\s0 will optimize for the processor
+When this option is not used, \s-1GCC\s0 optimizes for the processor
specified by \fB\-march\fR. By using \fB\-march\fR and
-\&\fB\-mtune\fR together, it is possible to generate code that will
-run on a family of processors, but optimize the code for one
+\&\fB\-mtune\fR together, it is possible to generate code that
+runs on a family of processors, but optimize the code for one
particular member of that family.
.Sp
\&\fB\-mtune\fR defines the macros \fB_MIPS_TUNE\fR and
.IP "\fB\-mno\-mips16\fR" 4
.IX Item "-mno-mips16"
.PD
-Generate (do not generate) \s-1MIPS16\s0 code. If \s-1GCC\s0 is targetting a
-\&\s-1MIPS32\s0 or \s-1MIPS64\s0 architecture, it will make use of the MIPS16e \s-1ASE\s0.
+Generate (do not generate) \s-1MIPS16\s0 code. If \s-1GCC\s0 is targeting a
+\&\s-1MIPS32\s0 or \s-1MIPS64\s0 architecture, it makes use of the MIPS16e \s-1ASE\s0.
.Sp
\&\s-1MIPS16\s0 code generation can also be controlled on a per-function basis
by means of \f(CW\*(C`mips16\*(C'\fR and \f(CW\*(C`nomips16\*(C'\fR attributes.
.Sp
\&\s-1GCC\s0 supports a variant of the o32 \s-1ABI\s0 in which floating-point registers
are 64 rather than 32 bits wide. You can select this combination with
-\&\fB\-mabi=32\fR \fB\-mfp64\fR. This \s-1ABI\s0 relies on the \fBmthc1\fR
-and \fBmfhc1\fR instructions and is therefore only supported for
+\&\fB\-mabi=32\fR \fB\-mfp64\fR. This \s-1ABI\s0 relies on the \f(CW\*(C`mthc1\*(C'\fR
+and \f(CW\*(C`mfhc1\*(C'\fR instructions and is therefore only supported for
\&\s-1MIPS32R2\s0 processors.
.Sp
The register assignments for arguments and return values remain the
\&\fB\-mno\-shared\fR depends on binutils 2.16 or higher and generates
objects that can only be linked by the \s-1GNU\s0 linker. However, the option
does not affect the \s-1ABI\s0 of the final executable; it only affects the \s-1ABI\s0
-of relocatable objects. Using \fB\-mno\-shared\fR will generally make
+of relocatable objects. Using \fB\-mno\-shared\fR generally makes
executables both smaller and quicker.
.Sp
\&\fB\-mshared\fR is the default.
offset table.
.Sp
\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT\s0.
-While this is relatively efficient, it will only work if the \s-1GOT\s0
-is smaller than about 64k. Anything larger will cause the linker
+While this is relatively efficient, it only works if the \s-1GOT\s0
+is smaller than about 64k. Anything larger causes the linker
to report an error such as:
.Sp
.Vb 1
.Ve
.Sp
If this happens, you should recompile your code with \fB\-mxgot\fR.
-It should then work with very large GOTs, although it will also be
-less efficient, since it will take three instructions to fetch the
+This works with very large GOTs, although the code is also
+less efficient, since it takes three instructions to fetch the
value of a global symbol.
.Sp
Note that some linkers can create multiple GOTs. If you have such a
.IX Item "-msoft-float"
Do not use floating-point coprocessor instructions. Implement
floating-point calculations using library calls instead.
+.IP "\fB\-mno\-float\fR" 4
+.IX Item "-mno-float"
+Equivalent to \fB\-msoft\-float\fR, but additionally asserts that the
+program being compiled does not perform any floating-point operations.
+This option is presently supported only by some bare-metal \s-1MIPS\s0
+configurations, where it may select a special set of libraries
+that lack all floating-point support (including, for example, the
+floating-point \f(CW\*(C`printf\*(C'\fR formats).
+If code compiled with \f(CW\*(C`\-mno\-float\*(C'\fR accidentally contains
+floating-point operations, it is likely to suffer a link-time
+or run-time failure.
.IP "\fB\-msingle\-float\fR" 4
.IX Item "-msingle-float"
Assume that the floating-point coprocessor only supports single-precision
.PD
Use (do not use) \fBll\fR, \fBsc\fR, and \fBsync\fR instructions to
implement atomic memory built-in functions. When neither option is
-specified, \s-1GCC\s0 will use the instructions if the target architecture
+specified, \s-1GCC\s0 uses the instructions if the target architecture
supports them.
.Sp
\&\fB\-mllsc\fR is useful if the runtime environment can emulate the
.IX Item "-mno-mt"
.PD
Use (do not use) \s-1MT\s0 Multithreading instructions.
+.IP "\fB\-mmcu\fR" 4
+.IX Item "-mmcu"
+.PD 0
+.IP "\fB\-mno\-mcu\fR" 4
+.IX Item "-mno-mcu"
+.PD
+Use (do not use) the \s-1MIPS\s0 \s-1MCU\s0 \s-1ASE\s0 instructions.
.IP "\fB\-mlong64\fR" 4
.IX Item "-mlong64"
Force \f(CW\*(C`long\*(C'\fR types to be 64 bits wide. See \fB\-mlong32\fR for
.IP "\fB\-G\fR \fInum\fR" 4
.IX Item "-G num"
Put definitions of externally-visible data in a small data section
-if that data is no bigger than \fInum\fR bytes. \s-1GCC\s0 can then access
-the data more efficiently; see \fB\-mgpopt\fR for details.
+if that data is no bigger than \fInum\fR bytes. \s-1GCC\s0 can then generate
+more efficient accesses to the data; see \fB\-mgpopt\fR for details.
.Sp
The default \fB\-G\fR option depends on the configuration.
.IP "\fB\-mlocal\-sdata\fR" 4
.IP "\fB\-mno\-extern\-sdata\fR" 4
.IX Item "-mno-extern-sdata"
.PD
-Assume (do not assume) that externally-defined data will be in
-a small data section if that data is within the \fB\-G\fR limit.
+Assume (do not assume) that externally-defined data is in
+a small data section if the size of that data is within the \fB\-G\fR limit.
\&\fB\-mextern\-sdata\fR is the default for all configurations.
.Sp
If you compile a module \fIMod\fR with \fB\-mextern\-sdata\fR \fB\-G\fR
\&\fB\-mno\-gpopt\fR is useful for cases where the \f(CW$gp\fR register
might not hold the value of \f(CW\*(C`_gp\*(C'\fR. For example, if the code is
part of a library that might be used in a boot monitor, programs that
-call boot monitor routines will pass an unknown value in \f(CW$gp\fR.
-(In such situations, the boot monitor itself would usually be compiled
+call boot monitor routines pass an unknown value in \f(CW$gp\fR.
+(In such situations, the boot monitor itself is usually compiled
with \fB\-G0\fR.)
.Sp
\&\fB\-mno\-gpopt\fR implies \fB\-mno\-local\-sdata\fR and
instructions, when they are available. The default is
\&\fB\-mfused\-madd\fR.
.Sp
-When multiply-accumulate instructions are used, the intermediate
-product is calculated to infinite precision and is not subject to
-the \s-1FCSR\s0 Flush to Zero bit. This may be undesirable in some
-circumstances.
+On the R8000 \s-1CPU\s0 when multiply-accumulate instructions are used,
+the intermediate product is calculated to infinite precision
+and is not subject to the \s-1FCSR\s0 Flush to Zero bit. This may be
+undesirable in some circumstances. On other processors the result
+is numerically identical to the equivalent computation using
+separate multiply, add, subtract and negate instructions.
.IP "\fB\-nocpp\fR" 4
.IX Item "-nocpp"
Tell the \s-1MIPS\s0 assembler to not run its preprocessor over user
\&\fIlibgcc.a\fR. At present, these functions are only provided by
the \f(CW\*(C`mips64vr*\-elf\*(C'\fR configurations.
.Sp
-Other \s-1VR4120\s0 errata require a nop to be inserted between certain pairs of
+Other \s-1VR4120\s0 errata require a \s-1NOP\s0 to be inserted between certain pairs of
instructions. These errata are handled by the assembler, not by \s-1GCC\s0 itself.
.RE
.IP "\fB\-mfix\-vr4130\fR" 4
.IX Item "-mfix-vr4130"
Work around the \s-1VR4130\s0 \f(CW\*(C`mflo\*(C'\fR/\f(CW\*(C`mfhi\*(C'\fR errata. The
workarounds are implemented by the assembler rather than by \s-1GCC\s0,
-although \s-1GCC\s0 will avoid using \f(CW\*(C`mflo\*(C'\fR and \f(CW\*(C`mfhi\*(C'\fR if the
+although \s-1GCC\s0 avoids using \f(CW\*(C`mflo\*(C'\fR and \f(CW\*(C`mfhi\*(C'\fR if the
\&\s-1VR4130\s0 \f(CW\*(C`macc\*(C'\fR, \f(CW\*(C`macchi\*(C'\fR, \f(CW\*(C`dmacc\*(C'\fR and \f(CW\*(C`dmacchi\*(C'\fR
instructions are available instead.
.IP "\fB\-mfix\-sb1\fR" 4
In common with many processors, the R10K tries to predict the outcome
of a conditional branch and speculatively executes instructions from
the \*(L"taken\*(R" branch. It later aborts these instructions if the
-predicted outcome was wrong. However, on the R10K, even aborted
+predicted outcome is wrong. However, on the R10K, even aborted
instructions can have side effects.
.Sp
This problem only affects kernel stores and, depending on the system,
the target memory into cache and mark the cache line as dirty, even if
the store itself is later aborted. If a \s-1DMA\s0 operation writes to the
same area of memory before the \*(L"dirty\*(R" line is flushed, the cached
-data will overwrite the DMA-ed data. See the R10K processor manual
+data overwrites the DMA-ed data. See the R10K processor manual
for a full description, including other potential problems.
.Sp
One workaround is to insert cache barrier instructions before every memory
access that might be speculatively executed and that might have side
effects even if aborted. \fB\-mr10k\-cache\-barrier=\fR\fIsetting\fR
controls \s-1GCC\s0's implementation of this workaround. It assumes that
-aborted accesses to any byte in the following regions will not have
+aborted accesses to any byte in the following regions does not have
side effects:
.RS 4
.IP "1." 4
instructions may be generated if they are supported by the selected
architecture. An exception is for the \s-1MIPS32\s0 and \s-1MIPS64\s0 architectures
and processors that implement those architectures; for those, Branch
-Likely instructions will not be generated by default because the \s-1MIPS32\s0
+Likely instructions are not be generated by default because the \s-1MIPS32\s0
and \s-1MIPS64\s0 architectures specifically deprecate their use.
.IP "\fB\-mfp\-exceptions\fR" 4
.IX Item "-mfp-exceptions"
.IP "\fB\-mno\-fp\-exceptions\fR" 4
.IX Item "-mno-fp-exceptions"
.PD
-Specifies whether \s-1FP\s0 exceptions are enabled. This affects how we schedule
-\&\s-1FP\s0 instructions for some processors. The default is that \s-1FP\s0 exceptions are
+Specifies whether \s-1FP\s0 exceptions are enabled. This affects how
+\&\s-1FP\s0 instructions are scheduled for some processors.
+The default is that \s-1FP\s0 exceptions are
enabled.
.Sp
For instance, on the \s-1SB\-1\s0, if \s-1FP\s0 exceptions are disabled, and we are emitting
.PD
The \s-1VR4130\s0 pipeline is two-way superscalar, but can only issue two
instructions together if the first one is 8\-byte aligned. When this
-option is enabled, \s-1GCC\s0 will align pairs of instructions that it
+option is enabled, \s-1GCC\s0 aligns pairs of instructions that it
thinks should execute in parallel.
.Sp
This option only has an effect when optimizing for the \s-1VR4130\s0.
.PD
Enable (disable) generation of \f(CW\*(C`synci\*(C'\fR instructions on
architectures that support it. The \f(CW\*(C`synci\*(C'\fR instructions (if
-enabled) will be generated when \f(CW\*(C`_\|_builtin_\|_\|_clear_cache()\*(C'\fR is
+enabled) are generated when \f(CW\*(C`_\|_builtin_\|_\|_clear_cache()\*(C'\fR is
compiled.
.Sp
This option defaults to \f(CW\*(C`\-mno\-synci\*(C'\fR, but the default can be
.Sp
When compiling code for single processor systems, it is generally safe
to use \f(CW\*(C`synci\*(C'\fR. However, on many multi-core (\s-1SMP\s0) systems, it
-will not invalidate the instruction caches on all cores and may lead
+does not invalidate the instruction caches on all cores and may lead
to undefined behavior.
.IP "\fB\-mrelax\-pic\-calls\fR" 4
.IX Item "-mrelax-pic-calls"
range for a direct call.
.Sp
\&\fB\-mrelax\-pic\-calls\fR is the default if \s-1GCC\s0 was configured to use
-an assembler and a linker that supports the \f(CW\*(C`.reloc\*(C'\fR assembly
+an assembler and a linker that support the \f(CW\*(C`.reloc\*(C'\fR assembly
directive and \f(CW\*(C`\-mexplicit\-relocs\*(C'\fR is in effect. With
\&\f(CW\*(C`\-mno\-explicit\-relocs\*(C'\fR, this optimization can be performed by the
assembler and the linker alone without help from the compiler.
.IX Item "-mreturn-pointer-on-d0"
When generating a function that returns a pointer, return the pointer
in both \f(CW\*(C`a0\*(C'\fR and \f(CW\*(C`d0\*(C'\fR. Otherwise, the pointer is returned
-only in a0, and attempts to call such functions without a prototype
-would result in errors. Note that this option is on by default; use
+only in \f(CW\*(C`a0\*(C'\fR, and attempts to call such functions without a prototype
+result in errors. Note that this option is on by default; use
\&\fB\-mno\-return\-pointer\-on\-d0\fR to disable it.
.IP "\fB\-mno\-crt0\fR" 4
.IX Item "-mno-crt0"
instructions. This option defines the preprocessor macro
\&\fB_\|_NO_SETLB_\|_\fR.
.PP
+\fIMoxie Options\fR
+.IX Subsection "Moxie Options"
+.IP "\fB\-meb\fR" 4
+.IX Item "-meb"
+Generate big-endian code. This is the default for \fBmoxie\-*\-*\fR
+configurations.
+.IP "\fB\-mel\fR" 4
+.IX Item "-mel"
+Generate little-endian code.
+.IP "\fB\-mno\-crt0\fR" 4
+.IX Item "-mno-crt0"
+Do not link in the C run-time initialization object file.
+.PP
\fI\s-1PDP\-11\s0 Options\fR
.IX Subsection "PDP-11 Options"
.PP
for \fIae_type\fR are \fB\s-1ANY\s0\fR, \fB\s-1MUL\s0\fR, and \fB\s-1MAC\s0\fR.
.Sp
\&\fB\-mae=ANY\fR selects a completely generic \s-1AE\s0 type. Code
-generated with this option will run on any of the other \s-1AE\s0 types. The
-code will not be as efficient as it would be if compiled for a specific
-\&\s-1AE\s0 type, and some types of operation (e.g., multiplication) will not
+generated with this option runs on any of the other \s-1AE\s0 types. The
+code is not as efficient as it would be if compiled for a specific
+\&\s-1AE\s0 type, and some types of operation (e.g., multiplication) do not
work properly on all types of \s-1AE\s0.
.Sp
\&\fB\-mae=MUL\fR selects a \s-1MUL\s0 \s-1AE\s0 type. This is the most useful \s-1AE\s0 type
.IX Item "-msymbol-as-address"
Enable the compiler to directly use a symbol name as an address in a
load/store instruction, without first loading it into a
-register. Typically, the use of this option will generate larger
+register. Typically, the use of this option generates larger
programs, which run faster than when the option isn't used. However, the
results vary from program to program, so it is left as a user option,
rather than being permanently enabled.
performs byte-level memory operations on the \s-1MAC\s0 \s-1AE\s0 type. The \s-1MAC\s0 \s-1AE\s0 has
no hardware support for byte-level memory operations, so all byte
load/stores must be synthesized from word load/store operations. This is
-inefficient and a warning will be generated indicating to the programmer
-that they should rewrite the code to avoid byte operations, or to target
-an \s-1AE\s0 type that has the necessary hardware support. This option enables
-the warning to be turned off.
+inefficient and a warning is generated to indicate
+that you should rewrite the code to avoid byte operations, or to target
+an \s-1AE\s0 type that has the necessary hardware support. This option disables
+these warnings.
.PP
\fIPowerPC Options\fR
.IX Subsection "PowerPC Options"
.IX Subsection "IBM RS/6000 and PowerPC Options"
.PP
These \fB\-m\fR options are defined for the \s-1IBM\s0 \s-1RS/6000\s0 and PowerPC:
-.IP "\fB\-mpower\fR" 4
-.IX Item "-mpower"
-.PD 0
-.IP "\fB\-mno\-power\fR" 4
-.IX Item "-mno-power"
-.IP "\fB\-mpower2\fR" 4
-.IX Item "-mpower2"
-.IP "\fB\-mno\-power2\fR" 4
-.IX Item "-mno-power2"
-.IP "\fB\-mpowerpc\fR" 4
-.IX Item "-mpowerpc"
-.IP "\fB\-mno\-powerpc\fR" 4
-.IX Item "-mno-powerpc"
.IP "\fB\-mpowerpc\-gpopt\fR" 4
.IX Item "-mpowerpc-gpopt"
+.PD 0
.IP "\fB\-mno\-powerpc\-gpopt\fR" 4
.IX Item "-mno-powerpc-gpopt"
.IP "\fB\-mpowerpc\-gfxopt\fR" 4
.IP "\fB\-mno\-hard\-dfp\fR" 4
.IX Item "-mno-hard-dfp"
.PD
-\&\s-1GCC\s0 supports two related instruction set architectures for the
-\&\s-1RS/6000\s0 and PowerPC. The \fI\s-1POWER\s0\fR instruction set are those
-instructions supported by the \fBrios\fR chip set used in the original
-\&\s-1RS/6000\s0 systems and the \fIPowerPC\fR instruction set is the
-architecture of the Freescale MPC5xx, MPC6xx, MPC8xx microprocessors, and
-the \s-1IBM\s0 4xx, 6xx, and follow-on microprocessors.
-.Sp
-Neither architecture is a subset of the other. However there is a
-large common subset of instructions supported by both. An \s-1MQ\s0
-register is included in processors supporting the \s-1POWER\s0 architecture.
-.Sp
You use these options to specify which instructions are available on the
processor you are using. The default value of these options is
determined when configuring \s-1GCC\s0. Specifying the
options. We recommend you use the \fB\-mcpu=\fR\fIcpu_type\fR option
rather than the options listed above.
.Sp
-The \fB\-mpower\fR option allows \s-1GCC\s0 to generate instructions that
-are found only in the \s-1POWER\s0 architecture and to use the \s-1MQ\s0 register.
-Specifying \fB\-mpower2\fR implies \fB\-power\fR and also allows \s-1GCC\s0
-to generate instructions that are present in the \s-1POWER2\s0 architecture but
-not the original \s-1POWER\s0 architecture.
-.Sp
-The \fB\-mpowerpc\fR option allows \s-1GCC\s0 to generate instructions that
-are found only in the 32\-bit subset of the PowerPC architecture.
-Specifying \fB\-mpowerpc\-gpopt\fR implies \fB\-mpowerpc\fR and also allows
+Specifying \fB\-mpowerpc\-gpopt\fR allows
\&\s-1GCC\s0 to use the optional PowerPC architecture instructions in the
General Purpose group, including floating-point square root. Specifying
-\&\fB\-mpowerpc\-gfxopt\fR implies \fB\-mpowerpc\fR and also allows \s-1GCC\s0 to
+\&\fB\-mpowerpc\-gfxopt\fR allows \s-1GCC\s0 to
use the optional PowerPC architecture instructions in the Graphics
group, including floating-point select.
.Sp
64\-bit instructions that are found in the full PowerPC64 architecture
and to treat GPRs as 64\-bit, doubleword quantities. \s-1GCC\s0 defaults to
\&\fB\-mno\-powerpc64\fR.
-.Sp
-If you specify both \fB\-mno\-power\fR and \fB\-mno\-powerpc\fR, \s-1GCC\s0
-will use only the instructions in the common subset of both
-architectures plus some special \s-1AIX\s0 common-mode calls, and will not use
-the \s-1MQ\s0 register. Specifying both \fB\-mpower\fR and \fB\-mpowerpc\fR
-permits \s-1GCC\s0 to use any instruction from either architecture and to
-allow use of the \s-1MQ\s0 register; specify this for the Motorola \s-1MPC601\s0.
-.IP "\fB\-mnew\-mnemonics\fR" 4
-.IX Item "-mnew-mnemonics"
-.PD 0
-.IP "\fB\-mold\-mnemonics\fR" 4
-.IX Item "-mold-mnemonics"
-.PD
-Select which mnemonics to use in the generated assembler code. With
-\&\fB\-mnew\-mnemonics\fR, \s-1GCC\s0 uses the assembler mnemonics defined for
-the PowerPC architecture. With \fB\-mold\-mnemonics\fR it uses the
-assembler mnemonics defined for the \s-1POWER\s0 architecture. Instructions
-defined in only one architecture have only one mnemonic; \s-1GCC\s0 uses that
-mnemonic irrespective of which of these options is specified.
-.Sp
-\&\s-1GCC\s0 defaults to the mnemonics appropriate for the architecture in
-use. Specifying \fB\-mcpu=\fR\fIcpu_type\fR sometimes overrides the
-value of these option. Unless you are building a cross-compiler, you
-should normally not specify either \fB\-mnew\-mnemonics\fR or
-\&\fB\-mold\-mnemonics\fR, but should instead accept the default.
.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4
.IX Item "-mcpu=cpu_type"
-Set architecture type, register usage, choice of mnemonics, and
+Set architecture type, register usage, and
instruction scheduling parameters for machine type \fIcpu_type\fR.
Supported values for \fIcpu_type\fR are \fB401\fR, \fB403\fR,
\&\fB405\fR, \fB405fp\fR, \fB440\fR, \fB440fp\fR, \fB464\fR, \fB464fp\fR,
\&\fB603e\fR, \fB604\fR, \fB604e\fR, \fB620\fR, \fB630\fR, \fB740\fR,
\&\fB7400\fR, \fB7450\fR, \fB750\fR, \fB801\fR, \fB821\fR, \fB823\fR,
\&\fB860\fR, \fB970\fR, \fB8540\fR, \fBa2\fR, \fBe300c2\fR,
-\&\fBe300c3\fR, \fBe500mc\fR, \fBe500mc64\fR, \fBec603e\fR, \fBG3\fR,
-\&\fBG4\fR, \fBG5\fR, \fBtitan\fR, \fBpower\fR, \fBpower2\fR, \fBpower3\fR,
-\&\fBpower4\fR, \fBpower5\fR, \fBpower5+\fR, \fBpower6\fR, \fBpower6x\fR,
-\&\fBpower7\fR, \fBcommon\fR, \fBpowerpc\fR, \fBpowerpc64\fR, \fBrios\fR,
-\&\fBrios1\fR, \fBrios2\fR, \fBrsc\fR, and \fBrs64\fR.
-.Sp
-\&\fB\-mcpu=common\fR selects a completely generic processor. Code
-generated under this option will run on any \s-1POWER\s0 or PowerPC processor.
-\&\s-1GCC\s0 will use only the instructions in the common subset of both
-architectures, and will not use the \s-1MQ\s0 register. \s-1GCC\s0 assumes a generic
-processor model for scheduling purposes.
-.Sp
-\&\fB\-mcpu=power\fR, \fB\-mcpu=power2\fR, \fB\-mcpu=powerpc\fR, and
-\&\fB\-mcpu=powerpc64\fR specify generic \s-1POWER\s0, \s-1POWER2\s0, pure 32\-bit
-PowerPC (i.e., not \s-1MPC601\s0), and 64\-bit PowerPC architecture machine
+\&\fBe300c3\fR, \fBe500mc\fR, \fBe500mc64\fR, \fBe5500\fR,
+\&\fBe6500\fR, \fBec603e\fR, \fBG3\fR, \fBG4\fR, \fBG5\fR,
+\&\fBtitan\fR, \fBpower3\fR, \fBpower4\fR, \fBpower5\fR, \fBpower5+\fR,
+\&\fBpower6\fR, \fBpower6x\fR, \fBpower7\fR, \fBpower8\fR, \fBpowerpc\fR,
+\&\fBpowerpc64\fR, and \fBrs64\fR.
+.Sp
+\&\fB\-mcpu=powerpc\fR, and \fB\-mcpu=powerpc64\fR specify pure 32\-bit
+PowerPC and 64\-bit PowerPC architecture machine
types, with an appropriate, generic processor model assumed for
scheduling purposes.
.Sp
The other options specify a specific processor. Code generated under
-those options will run best on that processor, and may not run at all on
+those options runs best on that processor, and may not run at all on
others.
.Sp
The \fB\-mcpu\fR options automatically enable or disable the
following options:
.Sp
\&\fB\-maltivec \-mfprnd \-mhard\-float \-mmfcrf \-mmultiple
-\&\-mnew\-mnemonics \-mpopcntb \-mpopcntd \-mpower \-mpower2 \-mpowerpc64
+\&\-mpopcntb \-mpopcntd \-mpowerpc64
\&\-mpowerpc\-gpopt \-mpowerpc\-gfxopt \-msingle\-float \-mdouble\-float
\&\-msimple\-fpu \-mstring \-mmulhw \-mdlmzb \-mmfpgpr \-mvsx\fR
.Sp
-The particular options set for any particular \s-1CPU\s0 will vary between
+The particular options set for any particular \s-1CPU\s0 varies between
compiler versions, depending on what setting seems to produce optimal
code for that \s-1CPU\s0; it doesn't necessarily reflect the actual hardware's
capabilities. If you wish to set an individual option to a particular
.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4
.IX Item "-mtune=cpu_type"
Set the instruction scheduling parameters for machine type
-\&\fIcpu_type\fR, but do not set the architecture type, register usage, or
-choice of mnemonics, as \fB\-mcpu=\fR\fIcpu_type\fR would. The same
+\&\fIcpu_type\fR, but do not set the architecture type or register usage,
+as \fB\-mcpu=\fR\fIcpu_type\fR does. The same
values for \fIcpu_type\fR are used for \fB\-mtune\fR as for
-\&\fB\-mcpu\fR. If both are specified, the code generated will use the
-architecture, registers, and mnemonics set by \fB\-mcpu\fR, but the
+\&\fB\-mcpu\fR. If both are specified, the code generated uses the
+architecture and registers set by \fB\-mcpu\fR, but the
scheduling parameters set by \fB\-mtune\fR.
.IP "\fB\-mcmodel=small\fR" 4
.IX Item "-mcmodel=small"
Generate \s-1VRSAVE\s0 instructions when generating AltiVec code.
.IP "\fB\-mgen\-cell\-microcode\fR" 4
.IX Item "-mgen-cell-microcode"
-Generate Cell microcode instructions
+Generate Cell microcode instructions.
.IP "\fB\-mwarn\-cell\-microcode\fR" 4
.IX Item "-mwarn-cell-microcode"
-Warning when a Cell microcode instruction is going to emitted. An example
+Warn when a Cell microcode instruction is emitted. An example
of a Cell microcode instruction is a variable shift.
.IP "\fB\-msecure\-plt\fR" 4
.IX Item "-msecure-plt"
-Generate code that allows ld and ld.so to build executables and shared
-libraries with non-exec .plt and .got sections. This is a PowerPC
+Generate code that allows \fBld\fR and \fBld.so\fR
+to build executables and shared
+libraries with non-executable \f(CW\*(C`.plt\*(C'\fR and \f(CW\*(C`.got\*(C'\fR sections.
+This is a PowerPC
32\-bit \s-1SYSV\s0 \s-1ABI\s0 option.
.IP "\fB\-mbss\-plt\fR" 4
.IX Item "-mbss-plt"
-Generate code that uses a \s-1BSS\s0 .plt section that ld.so fills in, and
-requires .plt and .got sections that are both writable and executable.
+Generate code that uses a \s-1BSS\s0 \f(CW\*(C`.plt\*(C'\fR section that \fBld.so\fR
+fills in, and
+requires \f(CW\*(C`.plt\*(C'\fR and \f(CW\*(C`.got\*(C'\fR
+sections that are both writable and executable.
This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option.
.IP "\fB\-misel\fR" 4
.IX Item "-misel"
.PD
Modify generation of the \s-1TOC\s0 (Table Of Contents), which is created for
every executable file. The \fB\-mfull\-toc\fR option is selected by
-default. In that case, \s-1GCC\s0 will allocate at least one \s-1TOC\s0 entry for
+default. In that case, \s-1GCC\s0 allocates at least one \s-1TOC\s0 entry for
each unique non-automatic variable reference in your program. \s-1GCC\s0
-will also place floating-point constants in the \s-1TOC\s0. However, only
+also places floating-point constants in the \s-1TOC\s0. However, only
16,384 entries are available in the \s-1TOC\s0.
.Sp
If you receive a linker error message that saying you have overflowed
If you still run out of space in the \s-1TOC\s0 even when you specify both of
these options, specify \fB\-mminimal\-toc\fR instead. This option causes
\&\s-1GCC\s0 to make only one \s-1TOC\s0 entry for every file. When you specify this
-option, \s-1GCC\s0 will produce code that is slower and larger but which
+option, \s-1GCC\s0 produces code that is slower and larger but which
uses extremely little \s-1TOC\s0 space. You may wish to use this option
-only on files that contain less frequently executed code.
+only on files that contain less frequently-executed code.
.IP "\fB\-maix64\fR" 4
.IX Item "-maix64"
.PD 0
.PD
Enable 64\-bit \s-1AIX\s0 \s-1ABI\s0 and calling convention: 64\-bit pointers, 64\-bit
\&\f(CW\*(C`long\*(C'\fR type, and the infrastructure needed to support them.
-Specifying \fB\-maix64\fR implies \fB\-mpowerpc64\fR and
-\&\fB\-mpowerpc\fR, while \fB\-maix32\fR disables the 64\-bit \s-1ABI\s0 and
+Specifying \fB\-maix64\fR implies \fB\-mpowerpc64\fR,
+while \fB\-maix32\fR disables the 64\-bit \s-1ABI\s0 and
implies \fB\-mno\-powerpc64\fR. \s-1GCC\s0 defaults to \fB\-maix32\fR.
.IP "\fB\-mxl\-compat\fR" 4
.IX Item "-mxl-compat"
\&\fB\-mdouble\-float\fR implies \fB\-msingle\-float\fR.
.IP "\fB\-msimple\-fpu\fR" 4
.IX Item "-msimple-fpu"
-Do not generate sqrt and div instructions for hardware floating-point unit.
-.IP "\fB\-mfpu\fR" 4
-.IX Item "-mfpu"
-Specify type of floating-point unit. Valid values are \fIsp_lite\fR
-(equivalent to \-msingle\-float \-msimple\-fpu), \fIdp_lite\fR (equivalent
-to \-mdouble\-float \-msimple\-fpu), \fIsp_full\fR (equivalent to \-msingle\-float),
-and \fIdp_full\fR (equivalent to \-mdouble\-float).
+Do not generate \f(CW\*(C`sqrt\*(C'\fR and \f(CW\*(C`div\*(C'\fR instructions for hardware
+floating-point unit.
+.IP "\fB\-mfpu=\fR\fIname\fR" 4
+.IX Item "-mfpu=name"
+Specify type of floating-point unit. Valid values for \fIname\fR are
+\&\fBsp_lite\fR (equivalent to \fB\-msingle\-float \-msimple\-fpu\fR),
+\&\fBdp_lite\fR (equivalent to \fB\-mdouble\-float \-msimple\-fpu\fR),
+\&\fBsp_full\fR (equivalent to \fB\-msingle\-float\fR),
+and \fBdp_full\fR (equivalent to \fB\-mdouble\-float\fR).
.IP "\fB\-mxilinx\-fpu\fR" 4
.IX Item "-mxilinx-fpu"
Perform optimizations for the floating-point unit on Xilinx \s-1PPC\s0 405/440.
or store instructions. These instructions can incur a performance
penalty on Power6 processors in certain situations, such as when
stepping through large arrays that cross a 16M boundary. This option
-is enabled by default when targetting Power6 and disabled otherwise.
+is enabled by default when targeting Power6 and disabled otherwise.
.IP "\fB\-mfused\-madd\fR" 4
.IX Item "-mfused-madd"
.PD 0
.PD
Generate code that uses (does not use) the half-word multiply and
multiply-accumulate instructions on the \s-1IBM\s0 405, 440, 464 and 476 processors.
-These instructions are generated by default when targetting those
+These instructions are generated by default when targeting those
processors.
.IP "\fB\-mdlmzb\fR" 4
.IX Item "-mdlmzb"
.PD
Generate code that uses (does not use) the string-search \fBdlmzb\fR
instruction on the \s-1IBM\s0 405, 440, 464 and 476 processors. This instruction is
-generated by default when targetting those processors.
+generated by default when targeting those processors.
.IP "\fB\-mno\-bit\-align\fR" 4
.IX Item "-mno-bit-align"
.PD 0
.IX Item "-mstrict-align"
.PD
On System V.4 and embedded PowerPC systems do not (do) assume that
-unaligned memory references will be handled by the system.
+unaligned memory references are handled by the system.
.IP "\fB\-mrelocatable\fR" 4
.IX Item "-mrelocatable"
.PD 0
.IX Item "-mprioritize-restricted-insns=priority"
This option controls the priority that is assigned to
dispatch-slot restricted instructions during the second scheduling
-pass. The argument \fIpriority\fR takes the value \fI0/1/2\fR to assign
-\&\fIno/highest/second\-highest\fR priority to dispatch slot restricted
+pass. The argument \fIpriority\fR takes the value \fB0\fR, \fB1\fR,
+or \fB2\fR to assign no, highest, or second-highest (respectively)
+priority to dispatch-slot restricted
instructions.
.IP "\fB\-msched\-costly\-dep=\fR\fIdependence_type\fR" 4
.IX Item "-msched-costly-dep=dependence_type"
This option controls which dependences are considered costly
by the target during instruction scheduling. The argument
\&\fIdependence_type\fR takes one of the following values:
-\&\fIno\fR: no dependence is costly,
-\&\fIall\fR: all dependences are costly,
-\&\fItrue_store_to_load\fR: a true dependence from store to load is costly,
-\&\fIstore_to_load\fR: any dependence from store to load is costly,
-\&\fInumber\fR: any dependence for which latency >= \fInumber\fR is costly.
+.RS 4
+.IP "\fBno\fR" 4
+.IX Item "no"
+No dependence is costly.
+.IP "\fBall\fR" 4
+.IX Item "all"
+All dependences are costly.
+.IP "\fBtrue_store_to_load\fR" 4
+.IX Item "true_store_to_load"
+A true dependence from store to load is costly.
+.IP "\fBstore_to_load\fR" 4
+.IX Item "store_to_load"
+Any dependence from store to load is costly.
+.IP "\fInumber\fR" 4
+.IX Item "number"
+Any dependence for which the latency is greater than or equal to
+\&\fInumber\fR is costly.
+.RE
+.RS 4
+.RE
.IP "\fB\-minsert\-sched\-nops=\fR\fIscheme\fR" 4
.IX Item "-minsert-sched-nops=scheme"
-This option controls which nop insertion scheme will be used during
+This option controls which \s-1NOP\s0 insertion scheme is used during
the second scheduling pass. The argument \fIscheme\fR takes one of the
following values:
-\&\fIno\fR: Don't insert nops.
-\&\fIpad\fR: Pad with nops any dispatch group that has vacant issue slots,
+.RS 4
+.IP "\fBno\fR" 4
+.IX Item "no"
+Don't insert NOPs.
+.IP "\fBpad\fR" 4
+.IX Item "pad"
+Pad with NOPs any dispatch group that has vacant issue slots,
according to the scheduler's grouping.
-\&\fIregroup_exact\fR: Insert nops to force costly dependent insns into
-separate groups. Insert exactly as many nops as needed to force an insn
+.IP "\fBregroup_exact\fR" 4
+.IX Item "regroup_exact"
+Insert NOPs to force costly dependent insns into
+separate groups. Insert exactly as many NOPs as needed to force an insn
to a new group, according to the estimated processor grouping.
-\&\fInumber\fR: Insert nops to force costly dependent insns into
-separate groups. Insert \fInumber\fR nops to force an insn to a new group.
+.IP "\fInumber\fR" 4
+.IX Item "number"
+Insert NOPs to force costly dependent insns into
+separate groups. Insert \fInumber\fR NOPs to force an insn to a new group.
+.RE
+.RS 4
+.RE
.IP "\fB\-mcall\-sysv\fR" 4
.IX Item "-mcall-sysv"
On System V.4 and embedded PowerPC systems compile code using calling
-conventions that adheres to the March 1995 draft of the System V
+conventions that adhere to the March 1995 draft of the System V
Application Binary Interface, PowerPC processor supplement. This is the
default unless you configured \s-1GCC\s0 using \fBpowerpc\-*\-eabiaix\fR.
.IP "\fB\-mcall\-sysv\-eabi\fR" 4
\&\s-1ABI\s0.
.IP "\fB\-mabi=no\-spe\fR" 4
.IX Item "-mabi=no-spe"
-Disable Booke \s-1SPE\s0 \s-1ABI\s0 extensions for the current \s-1ABI\s0.
+Disable Book-E \s-1SPE\s0 \s-1ABI\s0 extensions for the current \s-1ABI\s0.
.IP "\fB\-mabi=ibmlongdouble\fR" 4
.IX Item "-mabi=ibmlongdouble"
Change the current \s-1ABI\s0 to use \s-1IBM\s0 extended-precision long double.
.PD
On System V.4 and embedded PowerPC systems assume that all calls to
variable argument functions are properly prototyped. Otherwise, the
-compiler must insert an instruction before every non prototyped call to
+compiler must insert an instruction before every non-prototyped call to
set or clear bit 6 of the condition code register (\fI\s-1CR\s0\fR) to
-indicate whether floating-point values were passed in the floating-point
+indicate whether floating-point values are passed in the floating-point
registers in case the function takes variable arguments. With
\&\fB\-mprototype\fR, only calls to prototyped variable argument functions
-will set or clear the bit.
+set or clear the bit.
.IP "\fB\-msim\fR" 4
.IX Item "-msim"
On embedded PowerPC systems, assume that the startup module is called
.IX Item "-mno-eabi"
.PD
On System V.4 and embedded PowerPC systems do (do not) adhere to the
-Embedded Applications Binary Interface (eabi) which is a set of
+Embedded Applications Binary Interface (\s-1EABI\s0), which is a set of
modifications to the System V.4 specifications. Selecting \fB\-meabi\fR
means that the stack is aligned to an 8\-byte boundary, a function
-\&\f(CW\*(C`_\|_eabi\*(C'\fR is called to from \f(CW\*(C`main\*(C'\fR to set up the eabi
+\&\f(CW\*(C`_\|_eabi\*(C'\fR is called from \f(CW\*(C`main\*(C'\fR to set up the \s-1EABI\s0
environment, and the \fB\-msdata\fR option can use both \f(CW\*(C`r2\*(C'\fR and
\&\f(CW\*(C`r13\*(C'\fR to point to two separate small data areas. Selecting
\&\fB\-mno\-eabi\fR means that the stack is aligned to a 16\-byte boundary,
-do not call an initialization function from \f(CW\*(C`main\*(C'\fR, and the
-\&\fB\-msdata\fR option will only use \f(CW\*(C`r13\*(C'\fR to point to a single
+no \s-1EABI\s0 initialization function is called from \f(CW\*(C`main\*(C'\fR, and the
+\&\fB\-msdata\fR option only uses \f(CW\*(C`r13\*(C'\fR to point to a single
small data area. The \fB\-meabi\fR option is on by default if you
configured \s-1GCC\s0 using one of the \fBpowerpc*\-*\-eabi*\fR options.
.IP "\fB\-msdata=eabi\fR" 4
.IP "\fB\-G\fR \fInum\fR" 4
.IX Item "-G num"
On embedded PowerPC systems, put global and static items less than or
-equal to \fInum\fR bytes into the small data or bss sections instead of
-the normal data or bss section. By default, \fInum\fR is 8. The
+equal to \fInum\fR bytes into the small data or \s-1BSS\s0 sections instead of
+the normal data or \s-1BSS\s0 section. By default, \fInum\fR is 8. The
\&\fB\-G\fR \fInum\fR switch is also passed to the linker.
All modules should be compiled with the same \fB\-G\fR \fInum\fR value.
.IP "\fB\-mregnames\fR" 4
.IP "\fB\-mno\-longcall\fR" 4
.IX Item "-mno-longcall"
.PD
-By default assume that all calls are far away so that a longer more
+By default assume that all calls are far away so that a longer and more
expensive calling sequence is required. This is required for calls
-further than 32 megabytes (33,554,432 bytes) from the current location.
-A short call will be generated if the compiler knows
+farther than 32 megabytes (33,554,432 bytes) from the current location.
+A short call is generated if the compiler knows
the call cannot be that far away. This setting can be overridden by
the \f(CW\*(C`shortcall\*(C'\fR function attribute, or by \f(CW\*(C`#pragma
longcall(0)\*(C'\fR.
as can the \s-1GNU\s0 linker for PowerPC/64. It is planned to add this feature
to the \s-1GNU\s0 linker for 32\-bit PowerPC systems as well.
.Sp
-On Darwin/PPC systems, \f(CW\*(C`#pragma longcall\*(C'\fR will generate \*(L"jbsr
-callee, L42\*(R", plus a \*(L"branch island\*(R" (glue code). The two target
-addresses represent the callee and the \*(L"branch island\*(R". The
-Darwin/PPC linker will prefer the first address and generate a \*(L"bl
-callee\*(R" if the \s-1PPC\s0 \*(L"bl\*(R" instruction will reach the callee directly;
-otherwise, the linker will generate \*(L"bl L42\*(R" to call the \*(L"branch
-island\*(R". The \*(L"branch island\*(R" is appended to the body of the
+On Darwin/PPC systems, \f(CW\*(C`#pragma longcall\*(C'\fR generates \f(CW\*(C`jbsr
+callee, L42\*(C'\fR, plus a \fIbranch island\fR (glue code). The two target
+addresses represent the callee and the branch island. The
+Darwin/PPC linker prefers the first address and generates a \f(CW\*(C`bl
+callee\*(C'\fR if the \s-1PPC\s0 \f(CW\*(C`bl\*(C'\fR instruction reaches the callee directly;
+otherwise, the linker generates \f(CW\*(C`bl L42\*(C'\fR to call the branch
+island. The branch island is appended to the body of the
calling function; it computes the full 32\-bit address of the callee
and jumps to it.
.Sp
the glue for every direct call, and the Darwin linker decides whether
to use or discard it.
.Sp
-In the future, we may cause \s-1GCC\s0 to ignore all longcall specifications
+In the future, \s-1GCC\s0 may ignore all longcall specifications
when the linker is known to generate glue.
.IP "\fB\-mtls\-markers\fR" 4
.IX Item "-mtls-markers"
.IX Item "-mno-tls-markers"
.PD
Mark (do not mark) calls to \f(CW\*(C`_\|_tls_get_addr\*(C'\fR with a relocation
-specifying the function argument. The relocation allows ld to
+specifying the function argument. The relocation allows the linker to
reliably associate function call with argument setup instructions for
-\&\s-1TLS\s0 optimization, which in turn allows gcc to better schedule the
+\&\s-1TLS\s0 optimization, which in turn allows \s-1GCC\s0 to better schedule the
sequence.
.IP "\fB\-pthread\fR" 4
.IX Item "-pthread"
.IP "\fB\-mno\-recip\fR" 4
.IX Item "-mno-recip"
.PD
-This option will enable \s-1GCC\s0 to use the reciprocal estimate and
+This option enables use of the reciprocal estimate and
reciprocal square root estimate instructions with additional
Newton-Raphson steps to increase precision instead of doing a divide or
square root and divide for floating-point arguments. You should use
roots.
.IP "\fB\-mrecip=\fR\fIopt\fR" 4
.IX Item "-mrecip=opt"
-This option allows to control which reciprocal estimate instructions
-may be used. \fIopt\fR is a comma separated list of options, which may
+This option controls which reciprocal estimate instructions
+may be used. \fIopt\fR is a comma-separated list of options, which may
be preceded by a \f(CW\*(C`!\*(C'\fR to invert the option:
\&\f(CW\*(C`all\*(C'\fR: enable all estimate instructions,
\&\f(CW\*(C`default\*(C'\fR: enable the default instructions, equivalent to \fB\-mrecip\fR,
\&\f(CW\*(C`rsqrtf\*(C'\fR: enable the single-precision reciprocal square root approximation instructions;
\&\f(CW\*(C`rsqrtd\*(C'\fR: enable the double-precision reciprocal square root approximation instructions;
.Sp
-So for example, \fB\-mrecip=all,!rsqrtd\fR would enable the
+So, for example, \fB\-mrecip=all,!rsqrtd\fR enables
all of the reciprocal estimate instructions, except for the
\&\f(CW\*(C`FRSQRTE\*(C'\fR, \f(CW\*(C`XSRSQRTEDP\*(C'\fR, and \f(CW\*(C`XVRSQRTEDP\*(C'\fR instructions
which handle the double-precision reciprocal square root calculations.
.PD
Assume (do not assume) that the reciprocal estimate instructions
provide higher-precision estimates than is mandated by the PowerPC
-\&\s-1ABI\s0. Selecting \fB\-mcpu=power6\fR or \fB\-mcpu=power7\fR
-automatically selects \fB\-mrecip\-precision\fR. The double-precision
-square root estimate instructions are not generated by
+\&\s-1ABI\s0. Selecting \fB\-mcpu=power6\fR, \fB\-mcpu=power7\fR or
+\&\fB\-mcpu=power8\fR automatically selects \fB\-mrecip\-precision\fR.
+The double-precision square root estimate instructions are not generated by
default on low-precision machines, since they do not provide an
estimate that converges after three steps.
.IP "\fB\-mveclibabi=\fR\fItype\fR" 4
external library. The only type supported at present is \f(CW\*(C`mass\*(C'\fR,
which specifies to use \s-1IBM\s0's Mathematical Acceleration Subsystem
(\s-1MASS\s0) libraries for vectorizing intrinsics using external libraries.
-\&\s-1GCC\s0 will currently emit calls to \f(CW\*(C`acosd2\*(C'\fR, \f(CW\*(C`acosf4\*(C'\fR,
+\&\s-1GCC\s0 currently emits calls to \f(CW\*(C`acosd2\*(C'\fR, \f(CW\*(C`acosf4\*(C'\fR,
\&\f(CW\*(C`acoshd2\*(C'\fR, \f(CW\*(C`acoshf4\*(C'\fR, \f(CW\*(C`asind2\*(C'\fR, \f(CW\*(C`asinf4\*(C'\fR,
\&\f(CW\*(C`asinhd2\*(C'\fR, \f(CW\*(C`asinhf4\*(C'\fR, \f(CW\*(C`atan2d2\*(C'\fR, \f(CW\*(C`atan2f4\*(C'\fR,
\&\f(CW\*(C`atand2\*(C'\fR, \f(CW\*(C`atanf4\*(C'\fR, \f(CW\*(C`atanhd2\*(C'\fR, \f(CW\*(C`atanhf4\*(C'\fR,
\&\f(CW\*(C`sinhf4\*(C'\fR, \f(CW\*(C`sqrtd2\*(C'\fR, \f(CW\*(C`sqrtf4\*(C'\fR, \f(CW\*(C`tand2\*(C'\fR,
\&\f(CW\*(C`tanf4\*(C'\fR, \f(CW\*(C`tanhd2\*(C'\fR, and \f(CW\*(C`tanhf4\*(C'\fR when generating code
for power7. Both \fB\-ftree\-vectorize\fR and
-\&\fB\-funsafe\-math\-optimizations\fR have to be enabled. The \s-1MASS\s0
-libraries will have to be specified at link time.
+\&\fB\-funsafe\-math\-optimizations\fR must also be enabled. The \s-1MASS\s0
+libraries must be specified at link time.
.IP "\fB\-mfriz\fR" 4
.IX Item "-mfriz"
.PD 0
systems where a function pointer points to a 3\-word descriptor giving
the function address, \s-1TOC\s0 value to be loaded in register \fIr2\fR, and
static chain value to be loaded in register \fIr11\fR. The
-\&\fB\-mpointers\-to\-nested\-functions\fR is on by default. You will
-not be able to call through pointers to nested functions or pointers
+\&\fB\-mpointers\-to\-nested\-functions\fR is on by default. You cannot
+call through pointers to nested functions or pointers
to functions compiled in other languages that use the static chain if
you use the \fB\-mno\-pointers\-to\-nested\-functions\fR.
.IP "\fB\-msave\-toc\-indirect\fR" 4
floating-point hardware. The default is enabled for the \fI\s-1RX600\s0\fR
series and disabled for the \fI\s-1RX200\s0\fR series.
.Sp
-Floating-point instructions will only be generated for 32\-bit floating-point
-values however, so if the \fB\-m64bit\-doubles\fR option is in
-use then the \s-1FPU\s0 hardware will not be used for doubles.
+Floating-point instructions are only generated for 32\-bit floating-point
+values, however, so the \s-1FPU\s0 hardware is not used for doubles if the
+\&\fB\-m64bit\-doubles\fR option is used.
.Sp
\&\fINote\fR If the \fB\-fpu\fR option is enabled then
\&\fB\-funsafe\-math\-optimizations\fR is also enabled automatically.
not overflow. Also when the small data area is used one of the \s-1RX\s0's
registers (usually \f(CW\*(C`r13\*(C'\fR) is reserved for use pointing to this
area, so it is no longer available for use by the compiler. This
-could result in slower and/or larger code if variables which once
-could have been held in the reserved register are now pushed onto the
-stack.
+could result in slower and/or larger code if variables are pushed onto
+the stack instead of being held in this register.
.Sp
Note, common variables (variables that have not been initialized) and
constants are not placed into the small data area as they are assigned
.IP "\fB\-mno\-sim\fR" 4
.IX Item "-mno-sim"
.PD
-Use the simulator runtime. The default is to use the libgloss board
-specific runtime.
+Use the simulator runtime. The default is to use the libgloss
+board-specific runtime.
.IP "\fB\-mas100\-syntax\fR" 4
.IX Item "-mas100-syntax"
.PD 0
.PD
When generating assembler output use a syntax that is compatible with
Renesas's \s-1AS100\s0 assembler. This syntax can also be handled by the \s-1GAS\s0
-assembler but it has some restrictions so generating it is not the
-default option.
+assembler, but it has some restrictions so it is not generated by default.
.IP "\fB\-mmax\-constant\-size=\fR\fIN\fR" 4
.IX Item "-mmax-constant-size=N"
Specifies the maximum size, in bytes, of a constant that can be used as
.IP "\fB\-mrelax\fR" 4
.IX Item "-mrelax"
Enable linker relaxation. Linker relaxation is a process whereby the
-linker will attempt to reduce the size of a program by finding shorter
+linker attempts to reduce the size of a program by finding shorter
versions of various instructions. Disabled by default.
.IP "\fB\-mint\-register=\fR\fIN\fR" 4
.IX Item "-mint-register=N"
Specify the number of registers to reserve for fast interrupt handler
functions. The value \fIN\fR can be between 0 and 4. A value of 1
-means that register \f(CW\*(C`r13\*(C'\fR will be reserved for the exclusive use
+means that register \f(CW\*(C`r13\*(C'\fR is reserved for the exclusive use
of fast interrupt handlers. A value of 2 reserves \f(CW\*(C`r13\*(C'\fR and
\&\f(CW\*(C`r12\*(C'\fR. A value of 3 reserves \f(CW\*(C`r13\*(C'\fR, \f(CW\*(C`r12\*(C'\fR and
\&\f(CW\*(C`r11\*(C'\fR, and a value of 4 reserves \f(CW\*(C`r13\*(C'\fR through \f(CW\*(C`r10\*(C'\fR.
.IX Item "-mno-pid"
.PD
Enables the generation of position independent data. When enabled any
-access to constant data will done via an offset from a base address
+access to constant data is done via an offset from a base address
held in a register. This allows the location of constant data to be
determined at run time without requiring the executable to be
relocated, which is a benefit to embedded applications with tight
.Sp
By default this feature is not enabled. The default can be restored
via the \fB\-mno\-pid\fR command-line option.
+.IP "\fB\-mno\-warn\-multiple\-fast\-interrupts\fR" 4
+.IX Item "-mno-warn-multiple-fast-interrupts"
+.PD 0
+.IP "\fB\-mwarn\-multiple\-fast\-interrupts\fR" 4
+.IX Item "-mwarn-multiple-fast-interrupts"
+.PD
+Prevents \s-1GCC\s0 from issuing a warning message if it finds more than one
+fast interrupt handler when it is compiling a file. The default is to
+issue a warning for each extra fast interrupt handler found, as the \s-1RX\s0
+only supports one such interrupt.
.PP
\&\fINote:\fR The generic \s-1GCC\s0 command-line option \fB\-ffixed\-\fR\fIreg\fR
has special significance to the \s-1RX\s0 port when used with the
\&\f(CW\*(C`interrupt\*(C'\fR function attribute. This attribute indicates a
-function intended to process fast interrupts. \s-1GCC\s0 will will ensure
+function intended to process fast interrupts. \s-1GCC\s0 ensures
that it only uses the registers \f(CW\*(C`r10\*(C'\fR, \f(CW\*(C`r11\*(C'\fR, \f(CW\*(C`r12\*(C'\fR
and/or \f(CW\*(C`r13\*(C'\fR and only provided that the normal use of the
corresponding registers have been restricted via the
.PD
Use (do not use) the hardware floating-point instructions and registers
for floating-point operations. When \fB\-msoft\-float\fR is specified,
-functions in \fIlibgcc.a\fR will be used to perform floating-point
+functions in \fIlibgcc.a\fR are used to perform floating-point
operations. When \fB\-mhard\-float\fR is specified, the compiler
generates \s-1IEEE\s0 floating-point instructions. This is the default.
.IP "\fB\-mhard\-dfp\fR" 4
.PD
Use (do not use) the hardware decimal-floating-point instructions for
decimal-floating-point operations. When \fB\-mno\-hard\-dfp\fR is
-specified, functions in \fIlibgcc.a\fR will be used to perform
+specified, functions in \fIlibgcc.a\fR are used to perform
decimal-floating-point operations. When \fB\-mhard\-dfp\fR is
specified, the compiler generates decimal-floating-point hardware
instructions. This is the default for \fB\-march=z9\-ec\fR or higher.
Store (do not store) the address of the caller's frame as backchain pointer
into the callee's stack frame.
A backchain may be needed to allow debugging using tools that do not understand
-\&\s-1DWARF\-2\s0 call frame information.
+\&\s-1DWARF\s0 2 call frame information.
When \fB\-mno\-packed\-stack\fR is in effect, the backchain pointer is stored
at the bottom of the stack frame; when \fB\-mpacked\-stack\fR is in effect,
the backchain is placed into the topmost word of the 96/160 byte register
The default is to not print debug information.
.IP "\fB\-march=\fR\fIcpu-type\fR" 4
.IX Item "-march=cpu-type"
-Generate code that will run on \fIcpu-type\fR, which is the name of a system
+Generate code that runs on \fIcpu-type\fR, which is the name of a system
representing a certain processor type. Possible values for
\&\fIcpu-type\fR are \fBg5\fR, \fBg6\fR, \fBz900\fR, \fBz990\fR,
\&\fBz9\-109\fR, \fBz9\-ec\fR and \fBz10\fR.
size e.g. the linux kernel.
.IP "\fB\-mwarn\-dynamicstack\fR" 4
.IX Item "-mwarn-dynamicstack"
-Emit a warning if the function calls alloca or uses dynamically
-sized arrays. This is generally a bad idea with a limited stack size.
+Emit a warning if the function calls \f(CW\*(C`alloca\*(C'\fR or uses dynamically-sized
+arrays. This is generally a bad idea with a limited stack size.
.IP "\fB\-mstack\-guard=\fR\fIstack-guard\fR" 4
.IX Item "-mstack-guard=stack-guard"
.PD 0
.IP "\fB\-mstack\-size=\fR\fIstack-size\fR" 4
.IX Item "-mstack-size=stack-size"
.PD
-If these options are provided the s390 back end emits additional instructions in
-the function prologue which trigger a trap if the stack size is \fIstack-guard\fR
-bytes above the \fIstack-size\fR (remember that the stack on s390 grows downward).
+If these options are provided the S/390 back end emits additional instructions in
+the function prologue that trigger a trap if the stack size is \fIstack-guard\fR
+bytes above the \fIstack-size\fR (remember that the stack on S/390 grows downward).
If the \fIstack-guard\fR option is omitted the smallest power of 2 larger than
the frame size of the compiled function is chosen.
These options are intended to be used to help debugging stack overflow problems.
The additionally emitted code causes only little overhead and hence can also be
-used in production like systems without greater performance degradation. The given
+used in production-like systems without greater performance degradation. The given
values have to be exact powers of 2 and \fIstack-size\fR has to be greater than
\&\fIstack-guard\fR without exceeding 64k.
In order to be efficient the extra code makes the assumption that the stack starts
Compile code for little-endian mode.
.IP "\fB\-mnhwloop\fR" 4
.IX Item "-mnhwloop"
-Disable generate bcnz instruction.
+Disable generation of \f(CW\*(C`bcnz\*(C'\fR instructions.
.IP "\fB\-muls\fR" 4
.IX Item "-muls"
-Enable generate unaligned load and store instruction.
+Enable generation of unaligned load and store instructions.
.IP "\fB\-mmac\fR" 4
.IX Item "-mmac"
Enable the use of multiply-accumulate instructions. Disabled by default.
.IP "\fB\-mdalign\fR" 4
.IX Item "-mdalign"
Align doubles at 64\-bit boundaries. Note that this changes the calling
-conventions, and thus some functions from the standard C library will
+conventions, and thus some functions from the standard C library do
not work unless you recompile it first with \fB\-mdalign\fR.
.IP "\fB\-mrelax\fR" 4
.IX Item "-mrelax"
.IX Item "-minline-ic_invalidate"
Inline code to invalidate instruction cache entries after setting up
nested function trampolines.
-This option has no effect if \-musermode is in effect and the selected
-code generation option (e.g. \-m4) does not allow the use of the icbi
+This option has no effect if \fB\-musermode\fR is in effect and the selected
+code generation option (e.g. \fB\-m4\fR) does not allow the use of the \f(CW\*(C`icbi\*(C'\fR
instruction.
-If the selected code generation option does not allow the use of the icbi
-instruction, and \-musermode is not in effect, the inlined code will
-manipulate the instruction cache address array directly with an associative
-write. This not only requires privileged mode, but it will also
-fail if the cache line had been mapped via the \s-1TLB\s0 and has become unmapped.
+If the selected code generation option does not allow the use of the \f(CW\*(C`icbi\*(C'\fR
+instruction, and \fB\-musermode\fR is not in effect, the inlined code
+manipulates the instruction cache address array directly with an associative
+write. This not only requires privileged mode at run time, but it also
+fails if the cache line had been mapped via the \s-1TLB\s0 and has become unmapped.
.IP "\fB\-misize\fR" 4
.IX Item "-misize"
Dump instruction size and location in the assembly code.
.IX Item "-mpadstruct"
This option is deprecated. It pads structures to multiple of 4 bytes,
which is incompatible with the \s-1SH\s0 \s-1ABI\s0.
-.IP "\fB\-msoft\-atomic\fR" 4
-.IX Item "-msoft-atomic"
+.IP "\fB\-matomic\-model=\fR\fImodel\fR" 4
+.IX Item "-matomic-model=model"
+Sets the model of atomic operations and additional parameters as a comma
+separated list. For details on the atomic built-in functions see
+\&\fB_\|_atomic Builtins\fR. The following models and parameters are supported:
+.RS 4
+.IP "\fBnone\fR" 4
+.IX Item "none"
+Disable compiler generated atomic sequences and emit library calls for atomic
+operations. This is the default if the target is not \f(CW\*(C`sh\-*\-linux*\*(C'\fR.
+.IP "\fBsoft-gusa\fR" 4
+.IX Item "soft-gusa"
Generate GNU/Linux compatible gUSA software atomic sequences for the atomic
-built-in functions. The generated atomic sequences require support from the
-interrupt / exception handling code of the system and are only suitable for
-single-core systems. They will not perform correctly on multi-core systems.
-This option is enabled by default when the target is \f(CW\*(C`sh\-*\-linux*\*(C'\fR.
-For details on the atomic built-in functions see \fB_\|_atomic Builtins\fR.
+built-in functions. The generated atomic sequences require additional support
+from the interrupt/exception handling code of the system and are only suitable
+for SH3* and SH4* single-core systems. This option is enabled by default when
+the target is \f(CW\*(C`sh\-*\-linux*\*(C'\fR and SH3* or SH4*. When the target is \s-1SH4A\s0,
+this option will also partially utilize the hardware atomic instructions
+\&\f(CW\*(C`movli.l\*(C'\fR and \f(CW\*(C`movco.l\*(C'\fR to create more efficient code, unless
+\&\fBstrict\fR is specified.
+.IP "\fBsoft-tcb\fR" 4
+.IX Item "soft-tcb"
+Generate software atomic sequences that use a variable in the thread control
+block. This is a variation of the gUSA sequences which can also be used on
+SH1* and SH2* targets. The generated atomic sequences require additional
+support from the interrupt/exception handling code of the system and are only
+suitable for single-core systems. When using this model, the \fBgbr\-offset=\fR
+parameter has to be specified as well.
+.IP "\fBsoft-imask\fR" 4
+.IX Item "soft-imask"
+Generate software atomic sequences that temporarily disable interrupts by
+setting \f(CW\*(C`SR.IMASK = 1111\*(C'\fR. This model works only when the program runs
+in privileged mode and is only suitable for single-core systems. Additional
+support from the interrupt/exception handling code of the system is not
+required. This model is enabled by default when the target is
+\&\f(CW\*(C`sh\-*\-linux*\*(C'\fR and SH1* or SH2*.
+.IP "\fBhard-llcs\fR" 4
+.IX Item "hard-llcs"
+Generate hardware atomic sequences using the \f(CW\*(C`movli.l\*(C'\fR and \f(CW\*(C`movco.l\*(C'\fR
+instructions only. This is only available on \s-1SH4A\s0 and is suitable for
+multi-core systems. Since the hardware instructions support only 32 bit atomic
+variables access to 8 or 16 bit variables is emulated with 32 bit accesses.
+Code compiled with this option will also be compatible with other software
+atomic model interrupt/exception handling systems if executed on an \s-1SH4A\s0
+system. Additional support from the interrupt/exception handling code of the
+system is not required for this model.
+.IP "\fBgbr\-offset=\fR" 4
+.IX Item "gbr-offset="
+This parameter specifies the offset in bytes of the variable in the thread
+control block structure that should be used by the generated atomic sequences
+when the \fBsoft-tcb\fR model has been selected. For other models this
+parameter is ignored. The specified value must be an integer multiple of four
+and in the range 0\-1020.
+.IP "\fBstrict\fR" 4
+.IX Item "strict"
+This parameter prevents mixed usage of multiple atomic models, even though they
+would be compatible, and will make the compiler generate atomic sequences of the
+specified model only.
+.RE
+.RS 4
+.RE
+.IP "\fB\-mtas\fR" 4
+.IX Item "-mtas"
+Generate the \f(CW\*(C`tas.b\*(C'\fR opcode for \f(CW\*(C`_\|_atomic_test_and_set\*(C'\fR.
+Notice that depending on the particular hardware and software configuration
+this can degrade overall performance due to the operand cache line flushes
+that are implied by the \f(CW\*(C`tas.b\*(C'\fR instruction. On multi-core \s-1SH4A\s0
+processors the \f(CW\*(C`tas.b\*(C'\fR instruction must be used with caution since it
+can result in data corruption for certain cache configurations.
.IP "\fB\-mspace\fR" 4
.IX Item "-mspace"
Optimize for space instead of speed. Implied by \fB\-Os\fR.
the Global Offset Table instead of the Procedure Linkage Table.
.IP "\fB\-musermode\fR" 4
.IX Item "-musermode"
-Don't generate privileged mode only code; implies \-mno\-inline\-ic_invalidate
+Don't generate privileged mode only code. This option
+implies \fB\-mno\-inline\-ic_invalidate\fR
if the inlined code would not work in user mode.
This is the default when the target is \f(CW\*(C`sh\-*\-linux*\*(C'\fR.
.IP "\fB\-multcost=\fR\fInumber\fR" 4
.IP "\fB\-mdivsi3_libfunc=\fR\fIname\fR" 4
.IX Item "-mdivsi3_libfunc=name"
Set the name of the library function used for 32\-bit signed division to
-\&\fIname\fR. This only affect the name used in the call and inv:call
-division strategies, and the compiler will still expect the same
-sets of input/output/clobbered registers as if this option was not present.
+\&\fIname\fR.
+This only affects the name used in the \fBcall\fR and \fBinv:call\fR
+division strategies, and the compiler still expects the same
+sets of input/output/clobbered registers as if this option were not present.
.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4
.IX Item "-mfixed-range=register-range"
Generate code treating the given register range as fixed registers.
useful when compiling kernel code. A register range is specified as
two registers separated by a dash. Multiple register ranges can be
specified separated by a comma.
-.IP "\fB\-madjust\-unroll\fR" 4
-.IX Item "-madjust-unroll"
-Throttle unrolling to avoid thrashing target registers.
-This option only has an effect if the gcc code base supports the
-\&\s-1TARGET_ADJUST_UNROLL_MAX\s0 target hook.
.IP "\fB\-mindexed\-addressing\fR" 4
.IX Item "-mindexed-addressing"
Enable the use of the indexed addressing mode for SHmedia32/SHcompact.
the 32\-bit \s-1ABI\s0, the default is \fB\-mno\-indexed\-addressing\fR.
.IP "\fB\-mgettrcost=\fR\fInumber\fR" 4
.IX Item "-mgettrcost=number"
-Set the cost assumed for the gettr instruction to \fInumber\fR.
+Set the cost assumed for the \f(CW\*(C`gettr\*(C'\fR instruction to \fInumber\fR.
The default is 2 if \fB\-mpt\-fixed\fR is in effect, 100 otherwise.
.IP "\fB\-mpt\-fixed\fR" 4
.IX Item "-mpt-fixed"
-Assume pt* instructions won't trap. This will generally generate better
-scheduled code, but is unsafe on current hardware. The current architecture
-definition says that ptabs and ptrel trap when the target anded with 3 is 3.
-This has the unintentional effect of making it unsafe to schedule ptabs /
-ptrel before a branch, or hoist it out of a loop. For example,
-_\|_do_global_ctors, a part of libgcc that runs constructors at program
+Assume \f(CW\*(C`pt*\*(C'\fR instructions won't trap. This generally generates
+better-scheduled code, but is unsafe on current hardware.
+The current architecture
+definition says that \f(CW\*(C`ptabs\*(C'\fR and \f(CW\*(C`ptrel\*(C'\fR trap when the target
+anded with 3 is 3.
+This has the unintentional effect of making it unsafe to schedule these
+instructions before a branch, or hoist them out of a loop. For example,
+\&\f(CW\*(C`_\|_do_global_ctors\*(C'\fR, a part of \fIlibgcc\fR
+that runs constructors at program
startup, calls functions in a list which is delimited by \-1. With the
-\&\-mpt\-fixed option, the ptabs will be done before testing against \-1.
-That means that all the constructors will be run a bit quicker, but when
-the loop comes to the end of the list, the program crashes because ptabs
-loads \-1 into a target register. Since this option is unsafe for any
+\&\fB\-mpt\-fixed\fR option, the \f(CW\*(C`ptabs\*(C'\fR is done before testing against \-1.
+That means that all the constructors run a bit more quickly, but when
+the loop comes to the end of the list, the program crashes because \f(CW\*(C`ptabs\*(C'\fR
+loads \-1 into a target register.
+.Sp
+Since this option is unsafe for any
hardware implementing the current architecture specification, the default
-is \-mno\-pt\-fixed. Unless the user specifies a specific cost with
-\&\fB\-mgettrcost\fR, \-mno\-pt\-fixed also implies \fB\-mgettrcost=100\fR;
-this deters register allocation using target registers for storing
+is \fB\-mno\-pt\-fixed\fR. Unless specified explicitly with
+\&\fB\-mgettrcost\fR, \fB\-mno\-pt\-fixed\fR also implies \fB\-mgettrcost=100\fR;
+this deters register allocation from using target registers for storing
ordinary integers.
.IP "\fB\-minvalid\-symbols\fR" 4
.IX Item "-minvalid-symbols"
Assume symbols might be invalid. Ordinary function symbols generated by
-the compiler will always be valid to load with movi/shori/ptabs or
-movi/shori/ptrel, but with assembler and/or linker tricks it is possible
-to generate symbols that will cause ptabs / ptrel to trap.
+the compiler are always valid to load with
+\&\f(CW\*(C`movi\*(C'\fR/\f(CW\*(C`shori\*(C'\fR/\f(CW\*(C`ptabs\*(C'\fR or
+\&\f(CW\*(C`movi\*(C'\fR/\f(CW\*(C`shori\*(C'\fR/\f(CW\*(C`ptrel\*(C'\fR,
+but with assembler and/or linker tricks it is possible
+to generate symbols that cause \f(CW\*(C`ptabs\*(C'\fR or \f(CW\*(C`ptrel\*(C'\fR to trap.
This option is only meaningful when \fB\-mno\-pt\-fixed\fR is in effect.
-It will then prevent cross-basic-block cse, hoisting and most scheduling
+It prevents cross-basic-block \s-1CSE\s0, hoisting and most scheduling
of symbol loads. The default is \fB\-mno\-invalid\-symbols\fR.
.IP "\fB\-mbranch\-cost=\fR\fInum\fR" 4
.IX Item "-mbranch-cost=num"
Assume \fInum\fR to be the cost for a branch instruction. Higher numbers
-will make the compiler try to generate more branch-free code if possible.
+make the compiler try to generate more branch-free code if possible.
If not specified the value is selected depending on the processor type that
is being compiled for.
+.IP "\fB\-mzdcbranch\fR" 4
+.IX Item "-mzdcbranch"
+.PD 0
+.IP "\fB\-mno\-zdcbranch\fR" 4
+.IX Item "-mno-zdcbranch"
+.PD
+Assume (do not assume) that zero displacement conditional branch instructions
+\&\f(CW\*(C`bt\*(C'\fR and \f(CW\*(C`bf\*(C'\fR are fast. If \fB\-mzdcbranch\fR is specified, the
+compiler will try to prefer zero displacement branch code sequences. This is
+enabled by default when generating code for \s-1SH4\s0 and \s-1SH4A\s0. It can be explicitly
+disabled by specifying \fB\-mno\-zdcbranch\fR.
.IP "\fB\-mcbranchdi\fR" 4
.IX Item "-mcbranchdi"
Enable the \f(CW\*(C`cbranchdi4\*(C'\fR instruction pattern.
is in effect.
.IP "\fB\-mfused\-madd\fR" 4
.IX Item "-mfused-madd"
-Allow the usage of the \f(CW\*(C`fmac\*(C'\fR instruction (floating-point
-multiply-accumulate) if the processor type supports it. Enabling this
-option might generate code that produces different numeric floating-point
-results compared to strict \s-1IEEE\s0 754 arithmetic.
+.PD 0
+.IP "\fB\-mno\-fused\-madd\fR" 4
+.IX Item "-mno-fused-madd"
+.PD
+Generate code that uses (does not use) the floating-point multiply and
+accumulate instructions. These instructions are generated by default
+if hardware floating point is used. The machine-dependent
+\&\fB\-mfused\-madd\fR option is now mapped to the machine-independent
+\&\fB\-ffp\-contract=fast\fR option, and \fB\-mno\-fused\-madd\fR is
+mapped to \fB\-ffp\-contract=off\fR.
+.IP "\fB\-mfsca\fR" 4
+.IX Item "-mfsca"
+.PD 0
+.IP "\fB\-mno\-fsca\fR" 4
+.IX Item "-mno-fsca"
+.PD
+Allow or disallow the compiler to emit the \f(CW\*(C`fsca\*(C'\fR instruction for sine
+and cosine approximations. The option \f(CW\*(C`\-mfsca\*(C'\fR must be used in
+combination with \f(CW\*(C`\-funsafe\-math\-optimizations\*(C'\fR. It is enabled by default
+when generating code for \s-1SH4A\s0. Using \f(CW\*(C`\-mno\-fsca\*(C'\fR disables sine and cosine
+approximations even if \f(CW\*(C`\-funsafe\-math\-optimizations\*(C'\fR is in effect.
+.IP "\fB\-mfsrra\fR" 4
+.IX Item "-mfsrra"
+.PD 0
+.IP "\fB\-mno\-fsrra\fR" 4
+.IX Item "-mno-fsrra"
+.PD
+Allow or disallow the compiler to emit the \f(CW\*(C`fsrra\*(C'\fR instruction for
+reciprocal square root approximations. The option \f(CW\*(C`\-mfsrra\*(C'\fR must be used
+in combination with \f(CW\*(C`\-funsafe\-math\-optimizations\*(C'\fR and
+\&\f(CW\*(C`\-ffinite\-math\-only\*(C'\fR. It is enabled by default when generating code for
+\&\s-1SH4A\s0. Using \f(CW\*(C`\-mno\-fsrra\*(C'\fR disables reciprocal square root approximations
+even if \f(CW\*(C`\-funsafe\-math\-optimizations\*(C'\fR and \f(CW\*(C`\-ffinite\-math\-only\*(C'\fR are
+in effect.
.IP "\fB\-mpretend\-cmove\fR" 4
.IX Item "-mpretend-cmove"
Prefer zero-displacement conditional branches for conditional move instruction
.Sp
\&\fB\-mimpure\-text\fR suppresses the \*(L"relocations remain against
allocatable but non-writable sections\*(R" linker error message.
-However, the necessary relocations will trigger copy-on-write, and the
+However, the necessary relocations trigger copy-on-write, and the
shared object is not actually shared across processes. Instead of
using \fB\-mimpure\-text\fR, you should compile all source code with
\&\fB\-fpic\fR or \fB\-fPIC\fR.
2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications. This
is the default.
.Sp
-To be fully \s-1SVR4\s0 \s-1ABI\s0 compliant at the cost of some performance loss,
+To be fully \s-1SVR4\s0 ABI-compliant at the cost of some performance loss,
specify \fB\-mno\-app\-regs\fR. You should compile libraries and system
software with this option.
.IP "\fB\-mflat\fR" 4
With \fB\-mflat\fR, the compiler does not generate save/restore instructions
and uses a \*(L"flat\*(R" or single register window model. This model is compatible
with the regular register window model. The local registers and the input
-registers (0\-\-5) are still treated as \*(L"call-saved\*(R" registers and will be
+registers (0\-\-5) are still treated as \*(L"call-saved\*(R" registers and are
saved on the stack as needed.
.Sp
With \fB\-mno\-flat\fR (the default), the compiler generates save/restore
assignment, in place of twice as many \f(CW\*(C`ld\*(C'\fR and \f(CW\*(C`st\*(C'\fR pairs.
However, the use of this changed alignment directly violates the \s-1SPARC\s0
\&\s-1ABI\s0. Thus, it's intended only for use on targets where the developer
-acknowledges that their resulting code will not be directly in line with
+acknowledges that their resulting code is not directly in line with
the rules of the \s-1ABI\s0.
.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4
.IX Item "-mcpu=cpu_type"
.IX Item "-mtune=cpu_type"
Set the instruction scheduling parameters for machine type
\&\fIcpu_type\fR, but do not set the instruction set or register set that the
-option \fB\-mcpu=\fR\fIcpu_type\fR would.
+option \fB\-mcpu=\fR\fIcpu_type\fR does.
.Sp
The same values for \fB\-mcpu=\fR\fIcpu_type\fR can be used for
\&\fB\-mtune=\fR\fIcpu_type\fR, but the only useful values are those
.PD
With \fB\-mvis2\fR, \s-1GCC\s0 generates code that takes advantage of
version 2.0 of the UltraSPARC Visual Instruction Set extensions. The
-default is \fB\-mvis2\fR when targetting a cpu that supports such
+default is \fB\-mvis2\fR when targeting a cpu that supports such
instructions, such as UltraSPARC-III and later. Setting \fB\-mvis2\fR
also sets \fB\-mvis\fR.
.IP "\fB\-mvis3\fR" 4
.PD
With \fB\-mvis3\fR, \s-1GCC\s0 generates code that takes advantage of
version 3.0 of the UltraSPARC Visual Instruction Set extensions. The
-default is \fB\-mvis3\fR when targetting a cpu that supports such
+default is \fB\-mvis3\fR when targeting a cpu that supports such
instructions, such as niagara\-3 and later. Setting \fB\-mvis3\fR
also sets \fB\-mvis2\fR and \fB\-mvis\fR.
+.IP "\fB\-mcbcond\fR" 4
+.IX Item "-mcbcond"
+.PD 0
+.IP "\fB\-mno\-cbcond\fR" 4
+.IX Item "-mno-cbcond"
+.PD
+With \fB\-mcbcond\fR, \s-1GCC\s0 generates code that takes advantage of
+compare-and-branch instructions, as defined in the Sparc Architecture 2011.
+The default is \fB\-mcbcond\fR when targeting a cpu that supports such
+instructions, such as niagara\-4 and later.
.IP "\fB\-mpopc\fR" 4
.IX Item "-mpopc"
.PD 0
.PD
With \fB\-mpopc\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC
population count instruction. The default is \fB\-mpopc\fR
-when targetting a cpu that supports such instructions, such as Niagara\-2 and
+when targeting a cpu that supports such instructions, such as Niagara\-2 and
later.
.IP "\fB\-mfmaf\fR" 4
.IX Item "-mfmaf"
.PD
With \fB\-mfmaf\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC
Fused Multiply-Add Floating-point extensions. The default is \fB\-mfmaf\fR
-when targetting a cpu that supports such instructions, such as Niagara\-3 and
+when targeting a cpu that supports such instructions, such as Niagara\-3 and
later.
.IP "\fB\-mfix\-at697f\fR" 4
.IX Item "-mfix-at697f"
.IX Item "-merror-reloc"
.PD
The loader for \s-1SPU\s0 does not handle dynamic relocations. By default, \s-1GCC\s0
-will give an error when it generates code that requires a dynamic
+gives an error when it generates code that requires a dynamic
relocation. \fB\-mno\-error\-reloc\fR disables the error,
-\&\fB\-mwarn\-reloc\fR will generate a warning instead.
+\&\fB\-mwarn\-reloc\fR generates a warning instead.
.IP "\fB\-msafe\-dma\fR" 4
.IX Item "-msafe-dma"
.PD 0
.PD
Instructions that initiate or test completion of \s-1DMA\s0 must not be
reordered with respect to loads and stores of the memory that is being
-accessed. Users typically address this problem using the volatile
-keyword, but that can lead to inefficient code in places where the
-memory is known to not change. Rather than mark the memory as volatile
-we treat the \s-1DMA\s0 instructions as potentially effecting all memory. With
-\&\fB\-munsafe\-dma\fR users must use the volatile keyword to protect
-memory accesses.
+accessed.
+With \fB\-munsafe\-dma\fR you must use the \f(CW\*(C`volatile\*(C'\fR keyword to protect
+memory accesses, but that can lead to inefficient code in places where the
+memory is known to not change. Rather than mark the memory as volatile,
+you can use \fB\-msafe\-dma\fR to tell the compiler to treat
+the \s-1DMA\s0 instructions as potentially affecting all memory.
.IP "\fB\-mbranch\-hints\fR" 4
.IX Item "-mbranch-hints"
-By default, \s-1GCC\s0 will generate a branch hint instruction to avoid
-pipeline stalls for always taken or probably taken branches. A hint
-will not be generated closer than 8 instructions away from its branch.
+By default, \s-1GCC\s0 generates a branch hint instruction to avoid
+pipeline stalls for always-taken or probably-taken branches. A hint
+is not generated closer than 8 instructions away from its branch.
There is little reason to disable them, except for debugging purposes,
or to make an object a little bit smaller.
.IP "\fB\-msmall\-mem\fR" 4
.IX Item "-mstdmain"
By default, \s-1GCC\s0 links against startup code that assumes the SPU-style
main function interface (which has an unconventional parameter list).
-With \fB\-mstdmain\fR, \s-1GCC\s0 will link your program against startup
+With \fB\-mstdmain\fR, \s-1GCC\s0 links your program against startup
code that assumes a C99\-style interface to \f(CW\*(C`main\*(C'\fR, including a
local copy of \f(CW\*(C`argv\*(C'\fR strings.
.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4
.IX Item "-mfixed-range=register-range"
Generate code treating the given register range as fixed registers.
-A fixed register is one that the register allocator can not use. This is
+A fixed register is one that the register allocator cannot use. This is
useful when compiling kernel code. A register range is specified as
two registers separated by a dash. Multiple register ranges can be
specified separated by a comma.
.PD
Compile code assuming that pointers to the \s-1PPU\s0 address space accessed
via the \f(CW\*(C`_\|_ea\*(C'\fR named address space qualifier are either 32 or 64
-bits wide. The default is 32 bits. As this is an \s-1ABI\s0 changing option,
+bits wide. The default is 32 bits. As this is an ABI-changing option,
all object code in an executable must be compiled with the same setting.
.IP "\fB\-maddress\-space\-conversion\fR" 4
.IX Item "-maddress-space-conversion"
executable and selects whether atomic updates to the software-managed
cache of PPU-side variables are used. If you use atomic updates, changes
to a \s-1PPU\s0 variable from \s-1SPU\s0 code using the \f(CW\*(C`_\|_ea\*(C'\fR named address space
-qualifier will not interfere with changes to other \s-1PPU\s0 variables residing
+qualifier do not interfere with changes to other \s-1PPU\s0 variables residing
in the same cache line from \s-1PPU\s0 code. If you do not use atomic updates,
-such interference may occur; however, writing back cache lines will be
+such interference may occur; however, writing back cache lines is
more efficient. The default behavior is to use atomic updates.
.IP "\fB\-mdual\-nops\fR" 4
.IX Item "-mdual-nops"
.IP "\fB\-mdual\-nops=\fR\fIn\fR" 4
.IX Item "-mdual-nops=n"
.PD
-By default, \s-1GCC\s0 will insert nops to increase dual issue when it expects
+By default, \s-1GCC\s0 inserts nops to increase dual issue when it expects
it to increase performance. \fIn\fR can be a value from 0 to 10. A
-smaller \fIn\fR will insert fewer nops. 10 is the default, 0 is the
+smaller \fIn\fR inserts fewer nops. 10 is the default, 0 is the
same as \fB\-mno\-dual\-nops\fR. Disabled with \fB\-Os\fR.
.IP "\fB\-mhint\-max\-nops=\fR\fIn\fR" 4
.IX Item "-mhint-max-nops=n"
Maximum number of nops to insert for a branch hint. A branch hint must
-be at least 8 instructions away from the branch it is effecting. \s-1GCC\s0
-will insert up to \fIn\fR nops to enforce this, otherwise it will not
+be at least 8 instructions away from the branch it is affecting. \s-1GCC\s0
+inserts up to \fIn\fR nops to enforce this, otherwise it does not
generate the branch hint.
.IP "\fB\-mhint\-max\-distance=\fR\fIn\fR" 4
.IX Item "-mhint-max-distance=n"
The encoding of the branch hint instruction limits the hint to be within
-256 instructions of the branch it is effecting. By default, \s-1GCC\s0 makes
+256 instructions of the branch it is affecting. By default, \s-1GCC\s0 makes
sure it is within 125.
.IP "\fB\-msafe\-hints\fR" 4
.IX Item "-msafe-hints"
Work around a hardware bug that causes the \s-1SPU\s0 to stall indefinitely.
-By default, \s-1GCC\s0 will insert the \f(CW\*(C`hbrp\*(C'\fR instruction to make sure
+By default, \s-1GCC\s0 inserts the \f(CW\*(C`hbrp\*(C'\fR instruction to make sure
this stall won't happen.
.PP
\fIOptions for System V\fR
.IX Subsection "TILE-Gx Options"
.PP
These \fB\-m\fR options are supported on the TILE-Gx:
+.IP "\fB\-mcmodel=small\fR" 4
+.IX Item "-mcmodel=small"
+Generate code for the small model. The distance for direct calls is
+limited to 500M in either direction. PC-relative addresses are 32
+bits. Absolute addresses support the full address range.
+.IP "\fB\-mcmodel=large\fR" 4
+.IX Item "-mcmodel=large"
+Generate code for the large model. There is no limitation on call
+distance, pc-relative addresses, or absolute addresses.
.IP "\fB\-mcpu=\fR\fIname\fR" 4
.IX Item "-mcpu=name"
Selects the type of \s-1CPU\s0 to be targeted. Currently the only supported
.IX Item "-mno-long-calls"
.PD
Treat all calls as being far away (near). If calls are assumed to be
-far away, the compiler will always load the functions address up into a
-register, and call indirect through the pointer.
+far away, the compiler always loads the function's address into a
+register, and calls indirect through the pointer.
.IP "\fB\-mno\-ep\fR" 4
.IX Item "-mno-ep"
.PD 0
.IP "\fB\-mv850\fR" 4
.IX Item "-mv850"
Specify that the target processor is the V850.
-.IP "\fB\-mbig\-switch\fR" 4
-.IX Item "-mbig-switch"
-Generate code suitable for big switch tables. Use this option only if
-the assembler/linker complain about out of range branches within a switch
-table.
-.IP "\fB\-mapp\-regs\fR" 4
-.IX Item "-mapp-regs"
-This option will cause r2 and r5 to be used in the code generated by
-the compiler. This setting is the default.
-.IP "\fB\-mno\-app\-regs\fR" 4
-.IX Item "-mno-app-regs"
-This option will cause r2 and r5 to be treated as fixed registers.
+.IP "\fB\-mv850e3v5\fR" 4
+.IX Item "-mv850e3v5"
+Specify that the target processor is the V850E3V5. The preprocessor
+constant \fB_\|_v850e3v5_\|_\fR is defined if this option is used.
+.IP "\fB\-mv850e2v4\fR" 4
+.IX Item "-mv850e2v4"
+Specify that the target processor is the V850E3V5. This is an alias for
+the \fB\-mv850e3v5\fR option.
.IP "\fB\-mv850e2v3\fR" 4
.IX Item "-mv850e2v3"
Specify that the target processor is the V850E2V3. The preprocessor
-constants \fB_\|_v850e2v3_\|_\fR will be defined if
-this option is used.
+constant \fB_\|_v850e2v3_\|_\fR is defined if this option is used.
.IP "\fB\-mv850e2\fR" 4
.IX Item "-mv850e2"
Specify that the target processor is the V850E2. The preprocessor
-constants \fB_\|_v850e2_\|_\fR will be defined if this option is used.
+constant \fB_\|_v850e2_\|_\fR is defined if this option is used.
.IP "\fB\-mv850e1\fR" 4
.IX Item "-mv850e1"
Specify that the target processor is the V850E1. The preprocessor
-constants \fB_\|_v850e1_\|_\fR and \fB_\|_v850e_\|_\fR will be defined if
+constants \fB_\|_v850e1_\|_\fR and \fB_\|_v850e_\|_\fR are defined if
this option is used.
.IP "\fB\-mv850es\fR" 4
.IX Item "-mv850es"
.IP "\fB\-mv850e\fR" 4
.IX Item "-mv850e"
Specify that the target processor is the V850E. The preprocessor
-constant \fB_\|_v850e_\|_\fR will be defined if this option is used.
+constant \fB_\|_v850e_\|_\fR is defined if this option is used.
.Sp
If neither \fB\-mv850\fR nor \fB\-mv850e\fR nor \fB\-mv850e1\fR
-nor \fB\-mv850e2\fR nor \fB\-mv850e2v3\fR
-are defined then a default target processor will be chosen and the
-relevant \fB_\|_v850*_\|_\fR preprocessor constant will be defined.
+nor \fB\-mv850e2\fR nor \fB\-mv850e2v3\fR nor \fB\-mv850e3v5\fR
+are defined then a default target processor is chosen and the
+relevant \fB_\|_v850*_\|_\fR preprocessor constant is defined.
.Sp
The preprocessor constants \fB_\|_v850\fR and \fB_\|_v851_\|_\fR are always
defined, regardless of which processor variant is the target.
.IP "\fB\-mdisable\-callt\fR" 4
.IX Item "-mdisable-callt"
-This option will suppress generation of the \s-1CALLT\s0 instruction for the
-v850e, v850e1, v850e2 and v850e2v3 flavors of the v850 architecture. The default is
-\&\fB\-mno\-disable\-callt\fR which allows the \s-1CALLT\s0 instruction to be used.
+.PD 0
+.IP "\fB\-mno\-disable\-callt\fR" 4
+.IX Item "-mno-disable-callt"
+.PD
+This option suppresses generation of the \f(CW\*(C`CALLT\*(C'\fR instruction for the
+v850e, v850e1, v850e2, v850e2v3 and v850e3v5 flavors of the v850
+architecture.
+.Sp
+This option is enabled by default when the \s-1RH850\s0 \s-1ABI\s0 is
+in use (see \fB\-mrh850\-abi\fR), and disabled by default when the
+\&\s-1GCC\s0 \s-1ABI\s0 is in use. If \f(CW\*(C`CALLT\*(C'\fR instructions are being generated
+then the C preprocessor symbol \f(CW\*(C`_\|_V850_CALLT_\|_\*(C'\fR will be defined.
+.IP "\fB\-mrelax\fR" 4
+.IX Item "-mrelax"
+.PD 0
+.IP "\fB\-mno\-relax\fR" 4
+.IX Item "-mno-relax"
+.PD
+Pass on (or do not pass on) the \fB\-mrelax\fR command line option
+to the assembler.
+.IP "\fB\-mlong\-jumps\fR" 4
+.IX Item "-mlong-jumps"
+.PD 0
+.IP "\fB\-mno\-long\-jumps\fR" 4
+.IX Item "-mno-long-jumps"
+.PD
+Disable (or re-enable) the generation of PC-relative jump instructions.
+.IP "\fB\-msoft\-float\fR" 4
+.IX Item "-msoft-float"
+.PD 0
+.IP "\fB\-mhard\-float\fR" 4
+.IX Item "-mhard-float"
+.PD
+Disable (or re-enable) the generation of hardware floating point
+instructions. This option is only significant when the target
+architecture is \fBV850E2V3\fR or higher. If hardware floating point
+instructions are being generated then the C preprocessor symbol
+\&\f(CW\*(C`_\|_FPU_OK_\|_\*(C'\fR will be defined, otherwise the symbol
+\&\f(CW\*(C`_\|_NO_FPU_\|_\*(C'\fR will be defined.
+.IP "\fB\-mloop\fR" 4
+.IX Item "-mloop"
+Enables the use of the e3v5 \s-1LOOP\s0 instruction. The use of this
+instruction is not enabled by default when the e3v5 architecture is
+selected because its use is still experimental.
+.IP "\fB\-mrh850\-abi\fR" 4
+.IX Item "-mrh850-abi"
+.PD 0
+.IP "\fB\-mghs\fR" 4
+.IX Item "-mghs"
+.PD
+Enables support for the \s-1RH850\s0 version of the V850 \s-1ABI\s0. This is the
+default. With this version of the \s-1ABI\s0 the following rules apply:
+.RS 4
+.IP "\(bu" 4
+Integer sized structures and unions are returned via a memory pointer
+rather than a register.
+.IP "\(bu" 4
+Large structures and unions (more than 8 bytes in size) are passed by
+value.
+.IP "\(bu" 4
+Functions are aligned to 16\-bit boundaries.
+.IP "\(bu" 4
+The \fB\-m8byte\-align\fR command line option is supported.
+.IP "\(bu" 4
+The \fB\-mdisable\-callt\fR command line option is enabled by
+default. The \fB\-mno\-disable\-callt\fR command line option is not
+supported.
+.RE
+.RS 4
+.Sp
+When this version of the \s-1ABI\s0 is enabled the C preprocessor symbol
+\&\f(CW\*(C`_\|_V850_RH850_ABI_\|_\*(C'\fR is defined.
+.RE
+.IP "\fB\-mgcc\-abi\fR" 4
+.IX Item "-mgcc-abi"
+Enables support for the old \s-1GCC\s0 version of the V850 \s-1ABI\s0. With this
+version of the \s-1ABI\s0 the following rules apply:
+.RS 4
+.IP "\(bu" 4
+Integer sized structures and unions are returned in register \f(CW\*(C`r10\*(C'\fR.
+.IP "\(bu" 4
+Large structures and unions (more than 8 bytes in size) are passed by
+reference.
+.IP "\(bu" 4
+Functions are aligned to 32\-bit boundaries, unless optimizing for
+size.
+.IP "\(bu" 4
+The \fB\-m8byte\-align\fR command line option is not supported.
+.IP "\(bu" 4
+The \fB\-mdisable\-callt\fR command line option is supported but not
+enabled by default.
+.RE
+.RS 4
+.Sp
+When this version of the \s-1ABI\s0 is enabled the C preprocessor symbol
+\&\f(CW\*(C`_\|_V850_GCC_ABI_\|_\*(C'\fR is defined.
+.RE
+.IP "\fB\-m8byte\-align\fR" 4
+.IX Item "-m8byte-align"
+.PD 0
+.IP "\fB\-mno\-8byte\-align\fR" 4
+.IX Item "-mno-8byte-align"
+.PD
+Enables support for \f(CW\*(C`doubles\*(C'\fR and \f(CW\*(C`long long\*(C'\fR types to be
+aligned on 8\-byte boundaries. The default is to restrict the
+alignment of all objects to at most 4\-bytes. When
+\&\fB\-m8byte\-align\fR is in effect the C preprocessor symbol
+\&\f(CW\*(C`_\|_V850_8BYTE_ALIGN_\|_\*(C'\fR will be defined.
+.IP "\fB\-mbig\-switch\fR" 4
+.IX Item "-mbig-switch"
+Generate code suitable for big switch tables. Use this option only if
+the assembler/linker complain about out of range branches within a switch
+table.
+.IP "\fB\-mapp\-regs\fR" 4
+.IX Item "-mapp-regs"
+This option causes r2 and r5 to be used in the code generated by
+the compiler. This setting is the default.
+.IP "\fB\-mno\-app\-regs\fR" 4
+.IX Item "-mno-app-regs"
+This option causes r2 and r5 to be treated as fixed registers.
.PP
\fI\s-1VAX\s0 Options\fR
.IX Subsection "VAX Options"
ranges.
.IP "\fB\-mgnu\fR" 4
.IX Item "-mgnu"
-Do output those jump instructions, on the assumption that you
-will assemble with the \s-1GNU\s0 assembler.
+Do output those jump instructions, on the assumption that the
+\&\s-1GNU\s0 assembler is being used.
.IP "\fB\-mg\fR" 4
.IX Item "-mg"
Output code for G\-format floating-point numbers instead of D\-format.
.PP
+\fI\s-1VMS\s0 Options\fR
+.IX Subsection "VMS Options"
+.PP
+These \fB\-m\fR options are defined for the \s-1VMS\s0 implementations:
+.IP "\fB\-mvms\-return\-codes\fR" 4
+.IX Item "-mvms-return-codes"
+Return \s-1VMS\s0 condition codes from \f(CW\*(C`main\*(C'\fR. The default is to return POSIX-style
+condition (e.g. error) codes.
+.IP "\fB\-mdebug\-main=\fR\fIprefix\fR" 4
+.IX Item "-mdebug-main=prefix"
+Flag the first routine whose name starts with \fIprefix\fR as the main
+routine for the debugger.
+.IP "\fB\-mmalloc64\fR" 4
+.IX Item "-mmalloc64"
+Default to 64\-bit memory allocation routines.
+.IP "\fB\-mpointer\-size=\fR\fIsize\fR" 4
+.IX Item "-mpointer-size=size"
+Set the default size of pointers. Possible options for \fIsize\fR are
+\&\fB32\fR or \fBshort\fR for 32 bit pointers, \fB64\fR or \fBlong\fR
+for 64 bit pointers, and \fBno\fR for supporting only 32 bit pointers.
+The later option disables \f(CW\*(C`pragma pointer_size\*(C'\fR.
+.PP
\fIVxWorks Options\fR
.IX Subsection "VxWorks Options"
.PP
expense of some code density. The assembler attempts to widen density
instructions to align branch targets and the instructions following call
instructions. If there are not enough preceding safe density
-instructions to align a target, no widening will be performed. The
+instructions to align a target, no widening is performed. The
default is \fB\-mtarget\-align\fR. These options do not affect the
treatment of auto-aligned instructions like \f(CW\*(C`LOOP\*(C'\fR, which the
-assembler will always align, either by widening density instructions or
-by inserting no-op instructions.
+assembler always aligns, either by widening density instructions or
+by inserting \s-1NOP\s0 instructions.
.IP "\fB\-mlongcalls\fR" 4
.IX Item "-mlongcalls"
.PD 0
The default is \fB\-mno\-longcalls\fR. This option should be used in
programs where the call target can potentially be out of range. This
option is implemented in the assembler, not the compiler, so the
-assembly code generated by \s-1GCC\s0 will still show direct call
+assembly code generated by \s-1GCC\s0 still shows direct call
instructions\-\-\-look at the disassembled object code to see the actual
-instructions. Note that the assembler will use an indirect call for
-every cross-file call, not just those that really will be out of range.
+instructions. Note that the assembler uses an indirect call for
+every cross-file call, not just those that really are out of range.
.PP
\fIzSeries Options\fR
.IX Subsection "zSeries Options"
.PP
These are listed under
-.Sh "Options for Code Generation Conventions"
+.SS "Options for Code Generation Conventions"
.IX Subsection "Options for Code Generation Conventions"
These machine-independent options control the interface conventions
used in code generation.
.PP
Most of them have both positive and negative forms; the negative form
-of \fB\-ffoo\fR would be \fB\-fno\-foo\fR. In the table below, only
+of \fB\-ffoo\fR is \fB\-fno\-foo\fR. In the table below, only
one of the forms is listed\-\-\-the one that is not the default. You
can figure out the other form by either removing \fBno\-\fR or adding
it.
indices used to access arrays are within the declared range. This is
currently only supported by the Java and Fortran front ends, where
this option defaults to true and false respectively.
+.IP "\fB\-fstack\-reuse=\fR\fIreuse-level\fR" 4
+.IX Item "-fstack-reuse=reuse-level"
+This option controls stack space reuse for user declared local/auto variables
+and compiler generated temporaries. \fIreuse_level\fR can be \fBall\fR,
+\&\fBnamed_vars\fR, or \fBnone\fR. \fBall\fR enables stack reuse for all
+local variables and temporaries, \fBnamed_vars\fR enables the reuse only for
+user defined local variables with names, and \fBnone\fR disables stack reuse
+completely. The default value is \fBall\fR. The option is needed when the
+program extends the lifetime of a scoped local variable or a compiler generated
+temporary beyond the end point defined by the language. When a lifetime of
+a variable ends, and if the variable lives in memory, the optimizing compiler
+has the freedom to reuse its stack space with other temporaries or scoped
+local variables whose live range does not overlap with it. Legacy code extending
+local lifetime will likely to break with the stack reuse optimization.
+.Sp
+For example,
+.Sp
+.Vb 3
+\& int *p;
+\& {
+\& int local1;
+\&
+\& p = &local1;
+\& local1 = 10;
+\& ....
+\& }
+\& {
+\& int local2;
+\& local2 = 20;
+\& ...
+\& }
+\&
+\& if (*p == 10) // out of scope use of local1
+\& {
+\&
+\& }
+.Ve
+.Sp
+Another example:
+.Sp
+.Vb 6
+\& struct A
+\& {
+\& A(int k) : i(k), j(k) { }
+\& int i;
+\& int j;
+\& };
+\&
+\& A *ap;
+\&
+\& void foo(const A& ar)
+\& {
+\& ap = &ar;
+\& }
+\&
+\& void bar()
+\& {
+\& foo(A(10)); // temp object\*(Aqs lifetime ends when foo returns
+\&
+\& {
+\& A a(20);
+\& ....
+\& }
+\& ap\->i+= 10; // ap references out of scope temp whose space
+\& // is reused with a. What is the value of ap\->i?
+\& }
+.Ve
+.Sp
+The lifetime of a compiler generated temporary is well defined by the \*(C+
+standard. When a lifetime of a temporary ends, and if the temporary lives
+in memory, the optimizing compiler has the freedom to reuse its stack
+space with other temporaries or scoped local variables whose live range
+does not overlap with it. However some of the legacy code relies on
+the behavior of older compilers in which temporaries' stack space is
+not reused, the aggressive stack reuse can lead to runtime errors. This
+option is used to control the temporary stack reuse optimization.
.IP "\fB\-ftrapv\fR" 4
.IX Item "-ftrapv"
This option generates traps for signed overflow on addition, subtraction,
.IP "\fB\-fexceptions\fR" 4
.IX Item "-fexceptions"
Enable exception handling. Generates extra code needed to propagate
-exceptions. For some targets, this implies \s-1GCC\s0 will generate frame
+exceptions. For some targets, this implies \s-1GCC\s0 generates frame
unwind information for all functions, which can produce significant data
size overhead, although it does not affect execution. If you do not
-specify this option, \s-1GCC\s0 will enable it by default for languages like
-\&\*(C+ that normally require exception handling, and disable it for
+specify this option, \s-1GCC\s0 enables it by default for languages like
+\&\*(C+ that normally require exception handling, and disables it for
languages like C that do not normally require it. However, you may need
to enable this option when compiling C code that needs to interoperate
properly with exception handlers written in \*(C+. You may also wish to
instructions to throw exceptions, i.e. memory references or floating-point
instructions. It does not allow exceptions to be thrown from
arbitrary signal handlers such as \f(CW\*(C`SIGALRM\*(C'\fR.
+.IP "\fB\-fdelete\-dead\-exceptions\fR" 4
+.IX Item "-fdelete-dead-exceptions"
+Consider that instructions that may throw exceptions but don't otherwise
+contribute to the execution of the program can be optimized away.
+This option is enabled by default for the Ada front end, as permitted by
+the Ada language specification.
+Optimization passes that cause dead exceptions to be removed are enabled independently at different optimization levels.
.IP "\fB\-funwind\-tables\fR" 4
.IX Item "-funwind-tables"
-Similar to \fB\-fexceptions\fR, except that it will just generate any needed
-static data, but will not affect the generated code in any other way.
-You will normally not enable this option; instead, a language processor
-that needs this handling would enable it on your behalf.
+Similar to \fB\-fexceptions\fR, except that it just generates any needed
+static data, but does not affect the generated code in any other way.
+You normally do not need to enable this option; instead, a language processor
+that needs this handling enables it on your behalf.
.IP "\fB\-fasynchronous\-unwind\-tables\fR" 4
.IX Item "-fasynchronous-unwind-tables"
-Generate unwind table in dwarf2 format, if supported by target machine. The
+Generate unwind table in \s-1DWARF\s0 2 format, if supported by target machine. The
table is exact at each instruction boundary, so it can be used for stack
unwinding from asynchronous events (such as debugger or garbage collector).
.IP "\fB\-fpcc\-struct\-return\fR" 4
.IX Item "-fshort-enums"
Allocate to an \f(CW\*(C`enum\*(C'\fR type only as many bytes as it needs for the
declared range of possible values. Specifically, the \f(CW\*(C`enum\*(C'\fR type
-will be equivalent to the smallest integer type that has enough room.
+is equivalent to the smallest integer type that has enough room.
.Sp
\&\fBWarning:\fR the \fB\-fshort\-enums\fR switch causes \s-1GCC\s0 to generate
code that is not binary compatible with code generated without that switch.
rather than generating them as common blocks.
This has the effect that if the same variable is declared
(without \f(CW\*(C`extern\*(C'\fR) in two different compilations,
-you will get a multiple-definition error when you link them.
+you get a multiple-definition error when you link them.
In this case, you must compile with \fB\-fcommon\fR instead.
Compiling with \fB\-fno\-common\fR is useful on targets for which
it provides better performance, or if you wish to verify that the
files.
.IP "\fB\-frecord\-gcc\-switches\fR" 4
.IX Item "-frecord-gcc-switches"
-This switch causes the command line that was used to invoke the
+This switch causes the command line used to invoke the
compiler to be recorded into the object file that is being created.
This switch is only implemented on some targets and the exact format
of the recording is target and binary file format dependent, but it
.PD
These options are similar to \fB\-fpic\fR and \fB\-fPIC\fR, but
generated position independent code can be only linked into executables.
-Usually these options are used when \fB\-pie\fR \s-1GCC\s0 option will be
+Usually these options are used when \fB\-pie\fR \s-1GCC\s0 option is
used during linking.
.Sp
\&\fB\-fpie\fR and \fB\-fPIE\fR both define the macros
Treat the register named \fIreg\fR as an allocable register that is
clobbered by function calls. It may be allocated for temporaries or
variables that do not live across a call. Functions compiled this way
-will not save and restore the register \fIreg\fR.
+do not save and restore the register \fIreg\fR.
.Sp
-It is an error to used this flag with the frame pointer or stack pointer.
+It is an error to use this flag with the frame pointer or stack pointer.
Use of this flag for other registers that have fixed pervasive roles in
-the machine's execution model will produce disastrous results.
+the machine's execution model produces disastrous results.
.Sp
This flag does not have a negative form, because it specifies a
three-way choice.
.IX Item "-fcall-saved-reg"
Treat the register named \fIreg\fR as an allocable register saved by
functions. It may be allocated even for temporaries or variables that
-live across a call. Functions compiled this way will save and restore
+live across a call. Functions compiled this way save and restore
the register \fIreg\fR if they use it.
.Sp
-It is an error to used this flag with the frame pointer or stack pointer.
+It is an error to use this flag with the frame pointer or stack pointer.
Use of this flag for other registers that have fixed pervasive roles in
-the machine's execution model will produce disastrous results.
+the machine's execution model produces disastrous results.
.Sp
-A different sort of disaster will result from the use of this flag for
+A different sort of disaster results from the use of this flag for
a register in which function values may be returned.
.Sp
This flag does not have a negative form, because it specifies a
holes. When a value is specified (which must be a small power of two), pack
structure members according to this value, representing the maximum
alignment (that is, objects with default alignment requirements larger than
-this will be output potentially unaligned at the next fitting location.
+this are output potentially unaligned at the next fitting location.
.Sp
\&\fBWarning:\fR the \fB\-fpack\-struct\fR switch causes \s-1GCC\s0 to generate
code that is not binary compatible with code generated without that switch.
.IX Item "-finstrument-functions"
Generate instrumentation calls for entry and exit to functions. Just
after function entry and just before function exit, the following
-profiling functions will be called with the address of the current
+profiling functions are called with the address of the current
function and its call site. (On some platforms,
\&\f(CW\*(C`_\|_builtin_return_address\*(C'\fR does not work beyond the current
function, so the call site information may not be available to the
which may be looked up exactly in the symbol table.
.Sp
This instrumentation is also done for functions expanded inline in other
-functions. The profiling calls will indicate where, conceptually, the
+functions. The profiling calls indicate where, conceptually, the
inline function is entered and exited. This means that addressable
versions of such functions must be available. If all your uses of a
function are expanded inline, this may mean an additional expansion of
code size. If you use \fBextern inline\fR in your C code, an
addressable version of such functions must be provided. (This is
-normally the case anyways, but if you get lucky and the optimizer always
+normally the case anyway, but if you get lucky and the optimizer always
expands the functions inline, you might have gotten away without
providing static copies.)
.Sp
A function may be given the attribute \f(CW\*(C`no_instrument_function\*(C'\fR, in
-which case this instrumentation will not be done. This can be used, for
+which case this instrumentation is not done. This can be used, for
example, for the profiling functions listed above, high-priority
interrupt routines, and any functions from which the profiling functions
cannot safely be called (perhaps signal handlers, if the profiling
\& \-finstrument\-functions\-exclude\-file\-list=/bits/stl,include/sys
.Ve
.Sp
-will exclude any inline function defined in files whose pathnames
+excludes any inline function defined in files whose pathnames
contain \f(CW\*(C`/bits/stl\*(C'\fR or \f(CW\*(C`include/sys\*(C'\fR.
.Sp
If, for some reason, you want to include letter \f(CW\*(Aq,\*(Aq\fR in one of
.IX Item "-fstack-check"
Generate code to verify that you do not go beyond the boundary of the
stack. You should specify this flag if you are running in an
-environment with multiple threads, but only rarely need to specify it in
+environment with multiple threads, but you only rarely need to specify it in
a single-threaded environment since stack overflow is automatically
detected on nearly all systems if there is only one stack.
.Sp
target support in the compiler but comes with the following drawbacks:
.RS 4
.IP "1." 4
-Modified allocation strategy for large objects: they will always be
+Modified allocation strategy for large objects: they are always
allocated dynamically if their size exceeds a fixed threshold.
.IP "2." 4
Fixed limit on the size of the static frame of functions: when it is
a warning is issued by the compiler.
.IP "3." 4
Inefficiency: because of both the modified allocation strategy and the
-generic implementation, the performances of the code are hampered.
+generic implementation, code performance is hampered.
.RE
.RS 4
.Sp
.IX Item "-fno-stack-limit"
.PD
Generate code to ensure that the stack does not grow beyond a certain value,
-either the value of a register or the address of a symbol. If the stack
-would grow beyond the value, a signal is raised. For most targets,
+either the value of a register or the address of a symbol. If a larger
+stack is required, a signal is raised at run time. For most targets,
the signal is raised before the stack overruns the boundary, so
it is possible to catch the signal without taking special precautions.
.Sp
.IP "\fB\-fvisibility=\fR\fIdefault|internal|hidden|protected\fR" 4
.IX Item "-fvisibility=default|internal|hidden|protected"
Set the default \s-1ELF\s0 image symbol visibility to the specified option\-\-\-all
-symbols will be marked with this unless overridden within the code.
+symbols are marked with this unless overridden within the code.
Using this feature can very substantially improve linking and
load times of shared object libraries, produce more optimized
code, provide near-perfect \s-1API\s0 export and prevent symbol clashes.
Despite the nomenclature, \f(CW\*(C`default\*(C'\fR always means public; i.e.,
available to be linked against from outside the shared object.
\&\f(CW\*(C`protected\*(C'\fR and \f(CW\*(C`internal\*(C'\fR are pretty useless in real-world
-usage so the only other commonly used option will be \f(CW\*(C`hidden\*(C'\fR.
+usage so the only other commonly used option is \f(CW\*(C`hidden\*(C'\fR.
The default if \fB\-fvisibility\fR isn't specified is
\&\f(CW\*(C`default\*(C'\fR, i.e., make every
symbol public\-\-\-this causes the same behavior as previous versions of
<\fBhttp://people.redhat.com/~drepper/\fR>)\-\-\-however a superior
solution made possible by this option to marking things hidden when
the default is public is to make the default hidden and mark things
-public. This is the norm with \s-1DLL\s0's on Windows and with \fB\-fvisibility=hidden\fR
+public. This is the norm with DLLs on Windows and with \fB\-fvisibility=hidden\fR
and \f(CW\*(C`_\|_attribute_\|_ ((visibility("default")))\*(C'\fR instead of
\&\f(CW\*(C`_\|_declspec(dllexport)\*(C'\fR you get almost identical semantics with
identical syntax. This is a great boon to those working with
only for use within the local \s-1DSO\s0 should \fBalways\fR be marked explicitly
as hidden as so to avoid \s-1PLT\s0 indirection overheads\-\-\-making this
abundantly clear also aids readability and self-documentation of the code.
-Note that due to \s-1ISO\s0 \*(C+ specification requirements, operator new and
-operator delete must always be of default visibility.
+Note that due to \s-1ISO\s0 \*(C+ specification requirements, \f(CW\*(C`operator new\*(C'\fR and
+\&\f(CW\*(C`operator delete\*(C'\fR must always be of default visibility.
.Sp
Be aware that headers from outside your project, in particular system
headers and headers from any other library you use, may not be
.Sp
\&\fBextern\fR declarations are not affected by \fB\-fvisibility\fR, so
a lot of code can be recompiled with \fB\-fvisibility=hidden\fR with
-no modifications. However, this means that calls to \fBextern\fR
-functions with no explicit visibility will use the \s-1PLT\s0, so it is more
-effective to use \fB_\|_attribute ((visibility))\fR and/or
-\&\fB#pragma \s-1GCC\s0 visibility\fR to tell the compiler which \fBextern\fR
+no modifications. However, this means that calls to \f(CW\*(C`extern\*(C'\fR
+functions with no explicit visibility use the \s-1PLT\s0, so it is more
+effective to use \f(CW\*(C`_\|_attribute ((visibility))\*(C'\fR and/or
+\&\f(CW\*(C`#pragma GCC visibility\*(C'\fR to tell the compiler which \f(CW\*(C`extern\*(C'\fR
declarations should be treated as hidden.
.Sp
Note that \fB\-fvisibility\fR does affect \*(C+ vague linkage
-entities. This means that, for instance, an exception class that will
+entities. This means that, for instance, an exception class that is
be thrown between DSOs must be explicitly marked with default
-visibility so that the \fBtype_info\fR nodes will be unified between
+visibility so that the \fBtype_info\fR nodes are unified between
the DSOs.
.Sp
An overview of these techniques, their benefits and how to use them
anyway) should use a single access of the width of the
field's type, aligned to a natural alignment if possible. For
example, targets with memory-mapped peripheral registers might require
-all such accesses to be 16 bits wide; with this flag the user could
-declare all peripheral bit-fields as \*(L"unsigned short\*(R" (assuming short
+all such accesses to be 16 bits wide; with this flag you can
+declare all peripheral bit-fields as \f(CW\*(C`unsigned short\*(C'\fR (assuming short
is 16 bits on these targets) to force \s-1GCC\s0 to use 16\-bit accesses
instead of, perhaps, a more efficient 32\-bit access.
.Sp
-If this option is disabled, the compiler will use the most efficient
+If this option is disabled, the compiler uses the most efficient
instruction. In the previous example, that might be a 32\-bit load
-instruction, even though that will access bytes that do not contain
+instruction, even though that accesses bytes that do not contain
any portion of the bit-field, or memory-mapped registers unrelated to
the one being updated.
.Sp
.Sp
The default value of this option is determined by the application binary
interface for the target processor.
+.IP "\fB\-fsync\-libcalls\fR" 4
+.IX Item "-fsync-libcalls"
+This option controls whether any out-of-line instance of the \f(CW\*(C`_\|_sync\*(C'\fR
+family of functions may be used to implement the \*(C+11 \f(CW\*(C`_\|_atomic\*(C'\fR
+family of functions.
+.Sp
+The default value of this option is enabled, thus the only useful form
+of the option is \fB\-fno\-sync\-libcalls\fR. This option is used in
+the implementation of the \fIlibatomic\fR runtime library.
.SH "ENVIRONMENT"
.IX Header "ENVIRONMENT"
This section describes several environment variables that affect how \s-1GCC\s0
The \fB\s-1LC_CTYPE\s0\fR environment variable specifies character
classification. \s-1GCC\s0 uses it to determine the character boundaries in
a string; this is needed for some multibyte encodings that contain quote
-and escape characters that would otherwise be interpreted as a string
+and escape characters that are otherwise interpreted as a string
end or escape.
.Sp
The \fB\s-1LC_MESSAGES\s0\fR environment variable specifies the language to
when this prefix is combined with the name of a subprogram, but you can
specify a prefix that ends with a slash if you wish.
.Sp
-If \fB\s-1GCC_EXEC_PREFIX\s0\fR is not set, \s-1GCC\s0 will attempt to figure out
-an appropriate prefix to use based on the pathname it was invoked with.
+If \fB\s-1GCC_EXEC_PREFIX\s0\fR is not set, \s-1GCC\s0 attempts to figure out
+an appropriate prefix to use based on the pathname it is invoked with.
.Sp
If \s-1GCC\s0 cannot find the subprogram using the specified prefix, it
tries looking in the usual places for the subprogram.
directories whose name normally begins with \fB/usr/local/lib/gcc\fR
(more precisely, with the value of \fB\s-1GCC_INCLUDE_DIR\s0\fR), \s-1GCC\s0 tries
replacing that beginning with the specified prefix to produce an
-alternate directory name. Thus, with \fB\-Bfoo/\fR, \s-1GCC\s0 will search
-\&\fIfoo/bar\fR where it would normally search \fI/usr/local/lib/bar\fR.
-These alternate directories are searched first; the standard directories
-come next. If a standard directory begins with the configured
+alternate directory name. Thus, with \fB\-Bfoo/\fR, \s-1GCC\s0 searches
+\&\fIfoo/bar\fR just before it searches the standard directory
+\&\fI/usr/local/lib/bar\fR.
+If a standard directory begins with the configured
\&\fIprefix\fR then the value of \fIprefix\fR is replaced by
\&\fB\s-1GCC_EXEC_PREFIX\s0\fR when looking for header files.
.IP "\fB\s-1COMPILER_PATH\s0\fR" 4
.RS 4
.Sp
If \fB\s-1LANG\s0\fR is not defined, or if it has some other value, then the
-compiler will use mblen and mbtowc as defined by the default locale to
+compiler uses \f(CW\*(C`mblen\*(C'\fR and \f(CW\*(C`mbtowc\*(C'\fR as defined by the default locale to
recognize and translate multibyte characters.
.RE
.PP
-Some additional environments variables affect the behavior of the
+Some additional environment variables affect the behavior of the
preprocessor.
.IP "\fB\s-1CPATH\s0\fR" 4
.IX Item "CPATH"
for contributors to \s-1GCC\s0.
.SH "COPYRIGHT"
.IX Header "COPYRIGHT"
-Copyright (c) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
-2012
-Free Software Foundation, Inc.
+Copyright (c) 1988\-2013 Free Software Foundation, Inc.
.PP
Permission is granted to copy, distribute and/or modify this document
under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 or
projects / platform / upstream / gcc48.git / blobdiff