(define_attr "size" "8,16,32,64" (const_string "32"))
;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
-;; This is used for add, logical, shift, mul.
+;; This is used for add, logical, shift, exts, mul.
(define_attr "dot" "no,yes" (const_string "no"))
;; Does this instruction sign-extend its result?
; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
(define_attr "cell_micro" "not,conditional,always"
(if_then_else (ior (eq_attr "type" "compare")
- (and (eq_attr "type" "shift,mul")
+ (and (eq_attr "type" "shift,exts,mul")
(eq_attr "dot" "yes"))
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes"))
; Any supported integer mode that fits in one register.
(define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
-; extend modes for DImode
-(define_mode_iterator QHSI [QI HI SI])
+; Everything we can extend QImode to.
+(define_mode_iterator EXTQI [HI SI (DI "TARGET_POWERPC64")])
+
+; Everything we can extend HImode to.
+(define_mode_iterator EXTHI [SI (DI "TARGET_POWERPC64")])
+
+; Everything we can extend SImode to.
+(define_mode_iterator EXTSI [(DI "TARGET_POWERPC64")])
; QImode or HImode for small atomic ops
(define_mode_iterator QHI [QI HI])
(define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
; Definitions for 32-bit fpr direct move
-(define_mode_attr f32_dm [(SF "wn") (SD "wm")])
+(define_mode_attr f32_dm [(SF "wn") (SD "wh")])
; These modes do not fit in integer registers in 32-bit mode.
; but on e500v2, the gpr are 64 bit registers
(simple_return "1")])
(define_code_attr return_str [(return "") (simple_return "simple_")])
+; Signed/unsigned variants of ops.
+(define_code_iterator any_extend [sign_extend zero_extend])
+(define_code_attr u [(sign_extend "") (zero_extend "u")])
+(define_code_attr su [(sign_extend "s") (zero_extend "u")])
+
; Various instructions that come in SI and DI forms.
; A generic w/d attribute, for things like cmpw/cmpd.
(define_mode_attr wd [(QI "b")
;; Bitmask for shift instructions
(define_mode_attr hH [(SI "h") (DI "H")])
+;; A mode twice the size of the given mode
+(define_mode_attr dmode [(SI "di") (DI "ti")])
+(define_mode_attr DMODE [(SI "DI") (DI "TI")])
+
;; Suffix for reload patterns
(define_mode_attr ptrsize [(SI "32bit")
(DI "64bit")])
(V2DI "wa,v,r,0,0")
(V2DF "wa,v,r,0,0")
(V1TI "wa,v,r,0,0")])
-
-;; Mode attribute for the clobber of CC0 for AND expansion.
-;; For the 128-bit types, we never do AND immediate, but we need to
-;; get the correct number of X's for the number of operands.
-(define_mode_attr BOOL_REGS_AND_CR0 [(TI "X,X,X,X,X")
- (PTI "X,X,X")
- (V16QI "X,X,X,X,X")
- (V8HI "X,X,X,X,X")
- (V4SI "X,X,X,X,X")
- (V4SF "X,X,X,X,X")
- (V2DI "X,X,X,X,X")
- (V2DF "X,X,X,X,X")
- (V1TI "X,X,X,X,X")])
\f
;; Start with fixed-point load and store insns. Here we put only the more
;; complex forms. Basic data transfer is done later.
-(define_expand "zero_extend<mode>di2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
- "TARGET_POWERPC64"
- "")
-
-(define_insn "*zero_extend<mode>di2_internal1"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
- "TARGET_POWERPC64 && (<MODE>mode != SImode || !TARGET_LFIWZX)"
+(define_insn "zero_extendqi<mode>2"
+ [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
+ (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
+ ""
"@
- l<wd>z%U1%X1 %0,%1
- rldicl %0,%1,0,<dbits>"
+ lbz%U1%X1 %0,%1
+ rlwinm %0,%1,0,0xff"
[(set_attr "type" "load,shift")])
-(define_insn "*zero_extend<mode>di2_internal2"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
+(define_insn_and_split "*zero_extendqi<mode>2_dot"
+ [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
+ (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (clobber (match_scratch:DI 2 "=r,r"))]
- "TARGET_64BIT"
+ (clobber (match_scratch:EXTQI 0 "=r,r"))]
+ "rs6000_gen_cell_microcode"
"@
- rldicl. %2,%1,0,<dbits>
+ andi. %0,%1,0xff
#"
- [(set_attr "type" "shift")
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+ [(set (match_dup 0)
+ (zero_extend:EXTQI (match_dup 1)))
+ (set (match_dup 2)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
+ [(set_attr "type" "logical")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
+(define_insn_and_split "*zero_extendqi<mode>2_dot2"
+ [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
+ (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (clobber (match_scratch:DI 2 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 2)
- (zero_extend:DI (match_dup 1)))
- (set (match_dup 0)
- (compare:CC (match_dup 2)
+ (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
+ (zero_extend:EXTQI (match_dup 1)))]
+ "rs6000_gen_cell_microcode"
+ "@
+ andi. %0,%1,0xff
+ #"
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+ [(set (match_dup 0)
+ (zero_extend:EXTQI (match_dup 1)))
+ (set (match_dup 2)
+ (compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "logical")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
+
+
+(define_insn "zero_extendhi<mode>2"
+ [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
+ (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
+ ""
+ "@
+ lhz%U1%X1 %0,%1
+ rlwinm %0,%1,0,0xffff"
+ [(set_attr "type" "load,shift")])
-(define_insn "*zero_extend<mode>di2_internal3"
+(define_insn_and_split "*zero_extendhi<mode>2_dot"
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
+ (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (match_dup 1)))]
- "TARGET_64BIT"
+ (clobber (match_scratch:EXTHI 0 "=r,r"))]
+ "rs6000_gen_cell_microcode"
"@
- rldicl. %0,%1,0,<dbits>
+ andi. %0,%1,0xffff
#"
- [(set_attr "type" "shift")
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+ [(set (match_dup 0)
+ (zero_extend:EXTHI (match_dup 1)))
+ (set (match_dup 2)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
+ [(set_attr "type" "logical")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
-(define_split
- [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
+(define_insn_and_split "*zero_extendhi<mode>2_dot2"
+ [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
+ (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (match_dup 1)))]
- "TARGET_POWERPC64 && reload_completed"
+ (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
+ (zero_extend:EXTHI (match_dup 1)))]
+ "rs6000_gen_cell_microcode"
+ "@
+ andi. %0,%1,0xffff
+ #"
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
[(set (match_dup 0)
- (zero_extend:DI (match_dup 1)))
+ (zero_extend:EXTHI (match_dup 1)))
(set (match_dup 2)
(compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "logical")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
-(define_insn "*zero_extendsidi2_lfiwzx"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wz,!wu")
- (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
- "TARGET_POWERPC64 && TARGET_LFIWZX"
+
+(define_insn "zero_extendsi<mode>2"
+ [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu")
+ (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
+ ""
"@
lwz%U1%X1 %0,%1
rldicl %0,%1,0,32
lxsiwzx %x0,%y1"
[(set_attr "type" "load,shift,mffgpr,fpload,fpload")])
-(define_insn "extendqidi2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
- "TARGET_POWERPC64"
- "extsb %0,%1"
- [(set_attr "type" "exts")])
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
+(define_insn_and_split "*zero_extendsi<mode>2_dot"
+ [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
+ (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (clobber (match_scratch:DI 2 "=r,r"))]
- "TARGET_64BIT"
+ (clobber (match_scratch:EXTSI 0 "=r,r"))]
+ "rs6000_gen_cell_microcode"
"@
- extsb. %2,%1
+ rldicl. %0,%1,0,32
#"
- [(set_attr "type" "compare")
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+ [(set (match_dup 0)
+ (zero_extend:DI (match_dup 1)))
+ (set (match_dup 2)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
+(define_insn_and_split "*zero_extendsi<mode>2_dot2"
+ [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
+ (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (clobber (match_scratch:DI 2 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 2)
- (sign_extend:DI (match_dup 1)))
- (set (match_dup 0)
- (compare:CC (match_dup 2)
+ (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
+ (zero_extend:EXTSI (match_dup 1)))]
+ "rs6000_gen_cell_microcode"
+ "@
+ rldicl. %0,%1,0,32
+ #"
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+ [(set (match_dup 0)
+ (zero_extend:EXTSI (match_dup 1)))
+ (set (match_dup 2)
+ (compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
-(define_insn ""
+
+(define_insn "extendqi<mode>2"
+ [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r")
+ (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r")))]
+ ""
+ "extsb %0,%1"
+ [(set_attr "type" "exts")])
+
+(define_insn_and_split "*extendqi<mode>2_dot"
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
- (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
+ (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (sign_extend:DI (match_dup 1)))]
- "TARGET_64BIT"
+ (clobber (match_scratch:EXTQI 0 "=r,r"))]
+ "rs6000_gen_cell_microcode"
"@
extsb. %0,%1
#"
- [(set_attr "type" "compare")
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+ [(set (match_dup 0)
+ (sign_extend:EXTQI (match_dup 1)))
+ (set (match_dup 2)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
+ [(set_attr "type" "exts")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
-(define_split
- [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
+(define_insn_and_split "*extendqi<mode>2_dot2"
+ [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
+ (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (sign_extend:DI (match_dup 1)))]
- "TARGET_POWERPC64 && reload_completed"
+ (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
+ (sign_extend:EXTQI (match_dup 1)))]
+ "rs6000_gen_cell_microcode"
+ "@
+ extsb. %0,%1
+ #"
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
[(set (match_dup 0)
- (sign_extend:DI (match_dup 1)))
+ (sign_extend:EXTQI (match_dup 1)))
(set (match_dup 2)
(compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "exts")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
-(define_expand "extendhidi2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
- "TARGET_POWERPC64"
+
+(define_expand "extendhi<mode>2"
+ [(set (match_operand:EXTHI 0 "gpc_reg_operand" "")
+ (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "")))]
+ ""
"")
-(define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
- "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
+(define_insn "*extendhi<mode>2"
+ [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
+ (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
+ "rs6000_gen_cell_microcode"
"@
lha%U1%X1 %0,%1
extsh %0,%1"
[(set_attr "type" "load,exts")
(set_attr "sign_extend" "yes")])
-(define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
- "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
+(define_insn "*extendhi<mode>2_noload"
+ [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r")
+ (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r")))]
+ "!rs6000_gen_cell_microcode"
"extsh %0,%1"
[(set_attr "type" "exts")])
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
+(define_insn_and_split "*extendhi<mode>2_dot"
+ [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
+ (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (clobber (match_scratch:DI 2 "=r,r"))]
- "TARGET_64BIT"
+ (clobber (match_scratch:EXTHI 0 "=r,r"))]
+ "rs6000_gen_cell_microcode"
"@
- extsh. %2,%1
+ extsh. %0,%1
#"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:DI 2 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 2)
- (sign_extend:DI (match_dup 1)))
- (set (match_dup 0)
- (compare:CC (match_dup 2)
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+ [(set (match_dup 0)
+ (sign_extend:EXTHI (match_dup 1)))
+ (set (match_dup 2)
+ (compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "exts")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
-(define_insn ""
+(define_insn_and_split "*extendhi<mode>2_dot2"
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
- (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
+ (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (sign_extend:DI (match_dup 1)))]
- "TARGET_64BIT"
+ (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
+ (sign_extend:EXTHI (match_dup 1)))]
+ "rs6000_gen_cell_microcode"
"@
extsh. %0,%1
#"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (sign_extend:DI (match_dup 1)))]
- "TARGET_POWERPC64 && reload_completed"
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
[(set (match_dup 0)
- (sign_extend:DI (match_dup 1)))
+ (sign_extend:EXTHI (match_dup 1)))
(set (match_dup 2)
(compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "exts")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
-(define_expand "extendsidi2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
- "TARGET_POWERPC64"
- "")
-(define_insn "*extendsidi2_lfiwax"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wl,!wu")
- (sign_extend:DI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
- "TARGET_POWERPC64 && TARGET_LFIWAX"
+(define_insn "extendsi<mode>2"
+ [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu")
+ (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
+ ""
"@
lwa%U1%X1 %0,%1
extsw %0,%1
[(set_attr "type" "load,exts,mffgpr,fpload,fpload")
(set_attr "sign_extend" "yes")])
-(define_insn "*extendsidi2_nocell"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (sign_extend:DI (match_operand:SI 1 "lwa_operand" "Y,r")))]
- "TARGET_POWERPC64 && rs6000_gen_cell_microcode && !TARGET_LFIWAX"
- "@
- lwa%U1%X1 %0,%1
- extsw %0,%1"
- [(set_attr "type" "load,exts")
- (set_attr "sign_extend" "yes")])
-
-(define_insn "*extendsidi2_nocell"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
- "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
- "extsw %0,%1"
- [(set_attr "type" "exts")])
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
+(define_insn_and_split "*extendsi<mode>2_dot"
+ [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
+ (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (clobber (match_scratch:DI 2 "=r,r"))]
- "TARGET_64BIT"
+ (clobber (match_scratch:EXTSI 0 "=r,r"))]
+ "rs6000_gen_cell_microcode"
"@
- extsw. %2,%1
+ extsw. %0,%1
#"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:DI 2 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 2)
- (sign_extend:DI (match_dup 1)))
- (set (match_dup 0)
- (compare:CC (match_dup 2)
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+ [(set (match_dup 0)
+ (sign_extend:EXTSI (match_dup 1)))
+ (set (match_dup 2)
+ (compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "exts")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
-(define_insn ""
+(define_insn_and_split "*extendsi<mode>2_dot2"
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
- (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
+ (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (sign_extend:DI (match_dup 1)))]
- "TARGET_64BIT"
+ (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
+ (sign_extend:EXTSI (match_dup 1)))]
+ "rs6000_gen_cell_microcode"
"@
extsw. %0,%1
#"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (sign_extend:DI (match_dup 1)))]
- "TARGET_POWERPC64 && reload_completed"
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
[(set (match_dup 0)
- (sign_extend:DI (match_dup 1)))
+ (sign_extend:EXTSI (match_dup 1)))
(set (match_dup 2)
(compare:CC (match_dup 0)
(const_int 0)))]
- "")
-
-(define_expand "zero_extendqisi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
- ""
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
""
- "@
- lbz%U1%X1 %0,%1
- rlwinm %0,%1,0,0xff"
- [(set_attr "type" "load,shift")])
+ [(set_attr "type" "exts")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
+\f
+;; IBM 405, 440, 464 and 476 half-word multiplication operations.
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 2 "=r,r"))]
- ""
- "@
- andi. %2,%1,0xff
- #"
- [(set_attr "type" "logical,compare")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 2 ""))]
- "reload_completed"
- [(set (match_dup 2)
- (zero_extend:SI (match_dup 1)))
- (set (match_dup 0)
- (compare:CC (match_dup 2)
- (const_int 0)))]
- "")
+(define_insn "*macchwc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (plus:SI (mult:SI (ashiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16))
+ (sign_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "r")))
+ (match_operand:SI 4 "gpc_reg_operand" "0"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (ashiftrt:SI
+ (match_dup 2)
+ (const_int 16))
+ (sign_extend:SI
+ (match_dup 1)))
+ (match_dup 4)))]
+ "TARGET_MULHW"
+ "macchw. %0,%1,%2"
+ [(set_attr "type" "halfmul")])
-(define_insn ""
- [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:SI (match_dup 1)))]
- ""
- "@
- andi. %0,%1,0xff
- #"
- [(set_attr "type" "logical,compare")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
+(define_insn "*macchw"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (ashiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16))
+ (sign_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "r")))
+ (match_operand:SI 3 "gpc_reg_operand" "0")))]
+ "TARGET_MULHW"
+ "macchw %0,%1,%2"
+ [(set_attr "type" "halfmul")])
-(define_split
- [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extend:SI (match_dup 1)))]
- "reload_completed"
- [(set (match_dup 0)
- (zero_extend:SI (match_dup 1)))
- (set (match_dup 2)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
+(define_insn "*macchwuc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (plus:SI (mult:SI (lshiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16))
+ (zero_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "r")))
+ (match_operand:SI 4 "gpc_reg_operand" "0"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (lshiftrt:SI
+ (match_dup 2)
+ (const_int 16))
+ (zero_extend:SI
+ (match_dup 1)))
+ (match_dup 4)))]
+ "TARGET_MULHW"
+ "macchwu. %0,%1,%2"
+ [(set_attr "type" "halfmul")])
-(define_insn "extendqisi2"
+(define_insn "*macchwu"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
- ""
- "extsb %0,%1"
- [(set_attr "type" "exts")])
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 2 "=r,r"))]
- ""
- "@
- extsb. %2,%1
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
+ (plus:SI (mult:SI (lshiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16))
+ (zero_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "r")))
+ (match_operand:SI 3 "gpc_reg_operand" "0")))]
+ "TARGET_MULHW"
+ "macchwu %0,%1,%2"
+ [(set_attr "type" "halfmul")])
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 2 ""))]
- "reload_completed"
- [(set (match_dup 2)
- (sign_extend:SI (match_dup 1)))
- (set (match_dup 0)
- (compare:CC (match_dup 2)
- (const_int 0)))]
- "")
+(define_insn "*machhwc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (plus:SI (mult:SI (ashiftrt:SI
+ (match_operand:SI 1 "gpc_reg_operand" "%r")
+ (const_int 16))
+ (ashiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16)))
+ (match_operand:SI 4 "gpc_reg_operand" "0"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (ashiftrt:SI
+ (match_dup 1)
+ (const_int 16))
+ (ashiftrt:SI
+ (match_dup 2)
+ (const_int 16)))
+ (match_dup 4)))]
+ "TARGET_MULHW"
+ "machhw. %0,%1,%2"
+ [(set_attr "type" "halfmul")])
-(define_insn ""
- [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
- (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (sign_extend:SI (match_dup 1)))]
- ""
- "@
- extsb. %0,%1
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
+(define_insn "*machhw"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (ashiftrt:SI
+ (match_operand:SI 1 "gpc_reg_operand" "%r")
+ (const_int 16))
+ (ashiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16)))
+ (match_operand:SI 3 "gpc_reg_operand" "0")))]
+ "TARGET_MULHW"
+ "machhw %0,%1,%2"
+ [(set_attr "type" "halfmul")])
-(define_split
- [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (sign_extend:SI (match_dup 1)))]
- "reload_completed"
- [(set (match_dup 0)
- (sign_extend:SI (match_dup 1)))
- (set (match_dup 2)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
+(define_insn "*machhwuc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (plus:SI (mult:SI (lshiftrt:SI
+ (match_operand:SI 1 "gpc_reg_operand" "%r")
+ (const_int 16))
+ (lshiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16)))
+ (match_operand:SI 4 "gpc_reg_operand" "0"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (lshiftrt:SI
+ (match_dup 1)
+ (const_int 16))
+ (lshiftrt:SI
+ (match_dup 2)
+ (const_int 16)))
+ (match_dup 4)))]
+ "TARGET_MULHW"
+ "machhwu. %0,%1,%2"
+ [(set_attr "type" "halfmul")])
-(define_insn ""
- [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
- ""
- "@
- lbz%U1%X1 %0,%1
- rlwinm %0,%1,0,0xff"
- [(set_attr "type" "load,shift")])
+(define_insn "*machhwu"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (lshiftrt:SI
+ (match_operand:SI 1 "gpc_reg_operand" "%r")
+ (const_int 16))
+ (lshiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16)))
+ (match_operand:SI 3 "gpc_reg_operand" "0")))]
+ "TARGET_MULHW"
+ "machhwu %0,%1,%2"
+ [(set_attr "type" "halfmul")])
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:HI 2 "=r,r"))]
- ""
- "@
- andi. %2,%1,0xff
- #"
- [(set_attr "type" "logical,compare")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
+(define_insn "*maclhwc"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (plus:SI (mult:SI (sign_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "%r"))
+ (sign_extend:SI
+ (match_operand:HI 2 "gpc_reg_operand" "r")))
+ (match_operand:SI 4 "gpc_reg_operand" "0"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (sign_extend:SI
+ (match_dup 1))
+ (sign_extend:SI
+ (match_dup 2)))
+ (match_dup 4)))]
+ "TARGET_MULHW"
+ "maclhw. %0,%1,%2"
+ [(set_attr "type" "halfmul")])
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:HI 2 ""))]
- "reload_completed"
- [(set (match_dup 2)
- (zero_extend:HI (match_dup 1)))
- (set (match_dup 0)
- (compare:CC (match_dup 2)
- (const_int 0)))]
- "")
+(define_insn "*maclhw"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (mult:SI (sign_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "%r"))
+ (sign_extend:SI
+ (match_operand:HI 2 "gpc_reg_operand" "r")))
+ (match_operand:SI 3 "gpc_reg_operand" "0")))]
+ "TARGET_MULHW"
+ "maclhw %0,%1,%2"
+ [(set_attr "type" "halfmul")])
-(define_insn ""
- [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:HI (match_dup 1)))]
- ""
- "@
- andi. %0,%1,0xff
- #"
- [(set_attr "type" "logical,compare")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:HI 0 "gpc_reg_operand" "")
- (zero_extend:HI (match_dup 1)))]
- "reload_completed"
- [(set (match_dup 0)
- (zero_extend:HI (match_dup 1)))
- (set (match_dup 2)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "extendqihi2"
- [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
- (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
- ""
- "extsb %0,%1"
- [(set_attr "type" "exts")])
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:HI 2 "=r,r"))]
- ""
- "@
- extsb. %2,%1
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:HI 2 ""))]
- "reload_completed"
- [(set (match_dup 2)
- (sign_extend:HI (match_dup 1)))
- (set (match_dup 0)
- (compare:CC (match_dup 2)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
- (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
- (sign_extend:HI (match_dup 1)))]
- ""
- "@
- extsb. %0,%1
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:HI 0 "gpc_reg_operand" "")
- (sign_extend:HI (match_dup 1)))]
- "reload_completed"
- [(set (match_dup 0)
- (sign_extend:HI (match_dup 1)))
- (set (match_dup 2)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_expand "zero_extendhisi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
- ""
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
- ""
- "@
- lhz%U1%X1 %0,%1
- rlwinm %0,%1,0,0xffff"
- [(set_attr "type" "load,shift")])
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 2 "=r,r"))]
- ""
- "@
- andi. %2,%1,0xffff
- #"
- [(set_attr "type" "logical,compare")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 2 ""))]
- "reload_completed"
- [(set (match_dup 2)
- (zero_extend:SI (match_dup 1)))
- (set (match_dup 0)
- (compare:CC (match_dup 2)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:SI (match_dup 1)))]
- ""
- "@
- andi. %0,%1,0xffff
- #"
- [(set_attr "type" "logical,compare")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extend:SI (match_dup 1)))]
- "reload_completed"
- [(set (match_dup 0)
- (zero_extend:SI (match_dup 1)))
- (set (match_dup 2)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_expand "extendhisi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
- ""
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
- "rs6000_gen_cell_microcode"
- "@
- lha%U1%X1 %0,%1
- extsh %0,%1"
- [(set_attr "type" "load,exts")
- (set_attr "sign_extend" "yes")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
- "!rs6000_gen_cell_microcode"
- "extsh %0,%1"
- [(set_attr "type" "exts")])
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 2 "=r,r"))]
- ""
- "@
- extsh. %2,%1
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 2 ""))]
- "reload_completed"
- [(set (match_dup 2)
- (sign_extend:SI (match_dup 1)))
- (set (match_dup 0)
- (compare:CC (match_dup 2)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
- (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (sign_extend:SI (match_dup 1)))]
- ""
- "@
- extsh. %0,%1
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (sign_extend:SI (match_dup 1)))]
- "reload_completed"
- [(set (match_dup 0)
- (sign_extend:SI (match_dup 1)))
- (set (match_dup 2)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-\f
-;; IBM 405, 440, 464 and 476 half-word multiplication operations.
-
-(define_insn "*macchwc"
+(define_insn "*maclhwuc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (plus:SI (mult:SI (ashiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16))
- (sign_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "r")))
+ (compare:CC (plus:SI (mult:SI (zero_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "%r"))
+ (zero_extend:SI
+ (match_operand:HI 2 "gpc_reg_operand" "r")))
(match_operand:SI 4 "gpc_reg_operand" "0"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (ashiftrt:SI
- (match_dup 2)
- (const_int 16))
- (sign_extend:SI
- (match_dup 1)))
+ (plus:SI (mult:SI (zero_extend:SI
+ (match_dup 1))
+ (zero_extend:SI
+ (match_dup 2)))
(match_dup 4)))]
"TARGET_MULHW"
- "macchw. %0,%1,%2"
+ "maclhwu. %0,%1,%2"
[(set_attr "type" "halfmul")])
-(define_insn "*macchw"
+(define_insn "*maclhwu"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (ashiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16))
- (sign_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "r")))
+ (plus:SI (mult:SI (zero_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "%r"))
+ (zero_extend:SI
+ (match_operand:HI 2 "gpc_reg_operand" "r")))
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
- "macchw %0,%1,%2"
+ "maclhwu %0,%1,%2"
[(set_attr "type" "halfmul")])
-(define_insn "*macchwuc"
+(define_insn "*nmacchwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (plus:SI (mult:SI (lshiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16))
- (zero_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "r")))
- (match_operand:SI 4 "gpc_reg_operand" "0"))
+ (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
+ (mult:SI (ashiftrt:SI
+ (match_operand:SI 2 "gpc_reg_operand" "r")
+ (const_int 16))
+ (sign_extend:SI
+ (match_operand:HI 1 "gpc_reg_operand" "r"))))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (lshiftrt:SI
- (match_dup 2)
- (const_int 16))
- (zero_extend:SI
- (match_dup 1)))
- (match_dup 4)))]
+ (minus:SI (match_dup 4)
+ (mult:SI (ashiftrt:SI
+ (match_dup 2)
+ (const_int 16))
+ (sign_extend:SI
+ (match_dup 1)))))]
"TARGET_MULHW"
- "macchwu. %0,%1,%2"
+ "nmacchw. %0,%1,%2"
[(set_attr "type" "halfmul")])
-(define_insn "*macchwu"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (lshiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16))
- (zero_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "r")))
- (match_operand:SI 3 "gpc_reg_operand" "0")))]
- "TARGET_MULHW"
- "macchwu %0,%1,%2"
- [(set_attr "type" "halfmul")])
-
-(define_insn "*machhwc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (plus:SI (mult:SI (ashiftrt:SI
- (match_operand:SI 1 "gpc_reg_operand" "%r")
- (const_int 16))
- (ashiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16)))
- (match_operand:SI 4 "gpc_reg_operand" "0"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (ashiftrt:SI
- (match_dup 1)
- (const_int 16))
- (ashiftrt:SI
- (match_dup 2)
- (const_int 16)))
- (match_dup 4)))]
- "TARGET_MULHW"
- "machhw. %0,%1,%2"
- [(set_attr "type" "halfmul")])
-
-(define_insn "*machhw"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (ashiftrt:SI
- (match_operand:SI 1 "gpc_reg_operand" "%r")
- (const_int 16))
- (ashiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16)))
- (match_operand:SI 3 "gpc_reg_operand" "0")))]
- "TARGET_MULHW"
- "machhw %0,%1,%2"
- [(set_attr "type" "halfmul")])
-
-(define_insn "*machhwuc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (plus:SI (mult:SI (lshiftrt:SI
- (match_operand:SI 1 "gpc_reg_operand" "%r")
- (const_int 16))
- (lshiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16)))
- (match_operand:SI 4 "gpc_reg_operand" "0"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (lshiftrt:SI
- (match_dup 1)
- (const_int 16))
- (lshiftrt:SI
- (match_dup 2)
- (const_int 16)))
- (match_dup 4)))]
- "TARGET_MULHW"
- "machhwu. %0,%1,%2"
- [(set_attr "type" "halfmul")])
-
-(define_insn "*machhwu"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (lshiftrt:SI
- (match_operand:SI 1 "gpc_reg_operand" "%r")
- (const_int 16))
- (lshiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16)))
- (match_operand:SI 3 "gpc_reg_operand" "0")))]
- "TARGET_MULHW"
- "machhwu %0,%1,%2"
- [(set_attr "type" "halfmul")])
-
-(define_insn "*maclhwc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (plus:SI (mult:SI (sign_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "%r"))
- (sign_extend:SI
- (match_operand:HI 2 "gpc_reg_operand" "r")))
- (match_operand:SI 4 "gpc_reg_operand" "0"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (sign_extend:SI
- (match_dup 1))
- (sign_extend:SI
- (match_dup 2)))
- (match_dup 4)))]
- "TARGET_MULHW"
- "maclhw. %0,%1,%2"
- [(set_attr "type" "halfmul")])
-
-(define_insn "*maclhw"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (sign_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "%r"))
- (sign_extend:SI
- (match_operand:HI 2 "gpc_reg_operand" "r")))
- (match_operand:SI 3 "gpc_reg_operand" "0")))]
- "TARGET_MULHW"
- "maclhw %0,%1,%2"
- [(set_attr "type" "halfmul")])
-
-(define_insn "*maclhwuc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (plus:SI (mult:SI (zero_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "%r"))
- (zero_extend:SI
- (match_operand:HI 2 "gpc_reg_operand" "r")))
- (match_operand:SI 4 "gpc_reg_operand" "0"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (zero_extend:SI
- (match_dup 1))
- (zero_extend:SI
- (match_dup 2)))
- (match_dup 4)))]
- "TARGET_MULHW"
- "maclhwu. %0,%1,%2"
- [(set_attr "type" "halfmul")])
-
-(define_insn "*maclhwu"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (mult:SI (zero_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "%r"))
- (zero_extend:SI
- (match_operand:HI 2 "gpc_reg_operand" "r")))
- (match_operand:SI 3 "gpc_reg_operand" "0")))]
- "TARGET_MULHW"
- "maclhwu %0,%1,%2"
- [(set_attr "type" "halfmul")])
-
-(define_insn "*nmacchwc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
- (mult:SI (ashiftrt:SI
- (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16))
- (sign_extend:SI
- (match_operand:HI 1 "gpc_reg_operand" "r"))))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (minus:SI (match_dup 4)
- (mult:SI (ashiftrt:SI
- (match_dup 2)
- (const_int 16))
- (sign_extend:SI
- (match_dup 1)))))]
- "TARGET_MULHW"
- "nmacchw. %0,%1,%2"
- [(set_attr "type" "halfmul")])
-
-(define_insn "*nmacchw"
+(define_insn "*nmacchw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
(mult:SI (ashiftrt:SI
{
if (<MODE>mode == DImode && !TARGET_POWERPC64)
{
- rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);
+ rs6000_split_logical (operands, NOT, false, false, false);
DONE;
}
})
(define_expand "ctz<mode>2"
[(set (match_dup 2)
(neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
- (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
- (match_dup 2)))
- (clobber (scratch:CC))])
- (set (match_dup 4) (clz:GPR (match_dup 3)))
+ (set (match_dup 3)
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 4)
+ (clz:GPR (match_dup 3)))
(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (minus:GPR (match_dup 5) (match_dup 4)))]
+ (minus:GPR (match_dup 5)
+ (match_dup 4)))]
""
{
operands[2] = gen_reg_rtx (<MODE>mode);
(define_expand "ffs<mode>2"
[(set (match_dup 2)
(neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
- (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
- (match_dup 2)))
- (clobber (scratch:CC))])
- (set (match_dup 4) (clz:GPR (match_dup 3)))
+ (set (match_dup 3)
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 4)
+ (clz:GPR (match_dup 3)))
(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (minus:GPR (match_dup 5) (match_dup 4)))]
+ (minus:GPR (match_dup 5)
+ (match_dup 4)))]
""
{
operands[2] = gen_reg_rtx (<MODE>mode);
DONE;
}")
-(define_insn "mulsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
+
+(define_insn "mul<mode>3"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+ (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
+ (match_operand:GPR 2 "reg_or_short_operand" "r,I")))]
""
"@
- mullw %0,%1,%2
+ mull<wd> %0,%1,%2
mulli %0,%1,%2"
[(set_attr "type" "mul")
(set (attr "size")
- (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
+ (cond [(match_operand:GPR 2 "s8bit_cint_operand" "")
(const_string "8")
- (match_operand:SI 2 "short_cint_operand" "")
+ (match_operand:GPR 2 "short_cint_operand" "")
(const_string "16")]
- (const_string "32")))])
+ (const_string "<bits>")))])
-(define_insn "*mulsi3_internal1"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
+(define_insn_and_split "*mul<mode>3_dot"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "TARGET_32BIT"
+ (clobber (match_scratch:GPR 0 "=r,r"))]
+ "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
"@
- mullw. %3,%1,%2
+ mull<wd>. %0,%1,%2
#"
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+ [(set (match_dup 0)
+ (mult:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
[(set_attr "type" "mul")
+ (set_attr "size" "<bits>")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "TARGET_32BIT && reload_completed"
- [(set (match_dup 3)
- (mult:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*mulsi3_internal2"
+(define_insn_and_split "*mul<mode>3_dot2"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
+ (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (mult:SI (match_dup 1) (match_dup 2)))]
- "TARGET_32BIT"
+ (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+ (mult:GPR (match_dup 1)
+ (match_dup 2)))]
+ "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
"@
- mullw. %0,%1,%2
+ mull<wd>. %0,%1,%2
#"
- [(set_attr "type" "mul")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (mult:SI (match_dup 1) (match_dup 2)))]
- "TARGET_32BIT && reload_completed"
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
[(set (match_dup 0)
- (mult:SI (match_dup 1) (match_dup 2)))
+ (mult:GPR (match_dup 1)
+ (match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "mul")
+ (set_attr "size" "<bits>")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
+
+
+(define_expand "<su>mul<mode>3_highpart"
+ [(set (match_operand:GPR 0 "gpc_reg_operand")
+ (subreg:GPR
+ (mult:<DMODE> (any_extend:<DMODE>
+ (match_operand:GPR 1 "gpc_reg_operand"))
+ (any_extend:<DMODE>
+ (match_operand:GPR 2 "gpc_reg_operand")))
+ 0))]
+ ""
+{
+ if (<MODE>mode == SImode && TARGET_POWERPC64)
+ {
+ emit_insn (gen_<su>mulsi3_highpart_64 (operands[0], operands[1],
+ operands[2]));
+ DONE;
+ }
+
+ if (!WORDS_BIG_ENDIAN)
+ {
+ emit_insn (gen_<su>mul<mode>3_highpart_le (operands[0], operands[1],
+ operands[2]));
+ DONE;
+ }
+})
+
+(define_insn "*<su>mul<mode>3_highpart"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (subreg:GPR
+ (mult:<DMODE> (any_extend:<DMODE>
+ (match_operand:GPR 1 "gpc_reg_operand" "r"))
+ (any_extend:<DMODE>
+ (match_operand:GPR 2 "gpc_reg_operand" "r")))
+ 0))]
+ "WORDS_BIG_ENDIAN && !(<MODE>mode == SImode && TARGET_POWERPC64)"
+ "mulh<wd><u> %0,%1,%2"
+ [(set_attr "type" "mul")
+ (set_attr "size" "<bits>")])
+
+(define_insn "<su>mulsi3_highpart_le"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (subreg:SI
+ (mult:DI (any_extend:DI
+ (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (any_extend:DI
+ (match_operand:SI 2 "gpc_reg_operand" "r")))
+ 4))]
+ "!WORDS_BIG_ENDIAN && !TARGET_POWERPC64"
+ "mulhw<u> %0,%1,%2"
+ [(set_attr "type" "mul")])
+
+(define_insn "<su>muldi3_highpart_le"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (subreg:DI
+ (mult:TI (any_extend:TI
+ (match_operand:DI 1 "gpc_reg_operand" "r"))
+ (any_extend:TI
+ (match_operand:DI 2 "gpc_reg_operand" "r")))
+ 8))]
+ "!WORDS_BIG_ENDIAN && TARGET_POWERPC64"
+ "mulhd<u> %0,%1,%2"
+ [(set_attr "type" "mul")
+ (set_attr "size" "64")])
+
+(define_insn "<su>mulsi3_highpart_64"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (truncate:SI
+ (lshiftrt:DI
+ (mult:DI (any_extend:DI
+ (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (any_extend:DI
+ (match_operand:SI 2 "gpc_reg_operand" "r")))
+ (const_int 32))))]
+ "TARGET_POWERPC64"
+ "mulhw<u> %0,%1,%2"
+ [(set_attr "type" "mul")])
+
+(define_expand "<u>mul<mode><dmode>3"
+ [(set (match_operand:<DMODE> 0 "gpc_reg_operand")
+ (mult:<DMODE> (any_extend:<DMODE>
+ (match_operand:GPR 1 "gpc_reg_operand"))
+ (any_extend:<DMODE>
+ (match_operand:GPR 2 "gpc_reg_operand"))))]
+ "!(<MODE>mode == SImode && TARGET_POWERPC64)"
+{
+ rtx l = gen_reg_rtx (<MODE>mode);
+ rtx h = gen_reg_rtx (<MODE>mode);
+ emit_insn (gen_mul<mode>3 (l, operands[1], operands[2]));
+ emit_insn (gen_<su>mul<mode>3_highpart (h, operands[1], operands[2]));
+ emit_move_insn (gen_lowpart (<MODE>mode, operands[0]), l);
+ emit_move_insn (gen_highpart (<MODE>mode, operands[0]), h);
+ DONE;
+})
(define_insn "udiv<mode>3"
;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
;; those rotate-and-mask operations. Thus, the AND insns come first.
-(define_expand "andsi3"
- [(parallel
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "and_operand" "")))
- (clobber (match_scratch:CC 3 ""))])]
+(define_expand "and<mode>3"
+ [(set (match_operand:SDI 0 "gpc_reg_operand" "")
+ (and:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
+ (match_operand:SDI 2 "reg_or_cint_operand" "")))]
""
- "")
+{
+ if (<MODE>mode == DImode && !TARGET_POWERPC64)
+ {
+ rs6000_split_logical (operands, AND, false, false, false);
+ DONE;
+ }
-(define_insn "andsi3_mc"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
- (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
- (match_operand:SI 2 "and_operand" "?r,T,K,L")))
- (clobber (match_scratch:CC 3 "=X,X,x,x"))]
- "rs6000_gen_cell_microcode"
- "@
- and %0,%1,%2
- rlwinm %0,%1,0,%m2,%M2
- andi. %0,%1,%b2
- andis. %0,%1,%u2"
- [(set_attr "type" "*,shift,logical,logical")
- (set_attr "dot" "no,no,yes,yes")])
+ if (logical_const_operand (operands[2], <MODE>mode)
+ && !any_mask_operand (operands[2], <MODE>mode))
+ {
+ emit_insn (gen_and<mode>3_imm (operands[0], operands[1], operands[2]));
+ DONE;
+ }
-(define_insn "andsi3_nomc"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "and_operand" "?r,T")))
- (clobber (match_scratch:CC 3 "=X,X"))]
- "!rs6000_gen_cell_microcode"
- "@
- and %0,%1,%2
- rlwinm %0,%1,0,%m2,%M2"
- [(set_attr "type" "logical,shift")])
-
-(define_insn "andsi3_internal0_nomc"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "and_operand" "?r,T")))]
- "!rs6000_gen_cell_microcode"
- "@
- and %0,%1,%2
- rlwinm %0,%1,0,%m2,%M2"
- [(set_attr "type" "logical,shift")])
+ if ((<MODE>mode == DImode && !and64_2_operand (operands[2], <MODE>mode))
+ || (<MODE>mode != DImode && !and_operand (operands[2], <MODE>mode)))
+ operands[2] = force_reg (<MODE>mode, operands[2]);
+})
-;; Note to set cr's other than cr0 we do the and immediate and then
-;; the test again -- this avoids a mfcr which on the higher end
-;; machines causes an execution serialization
+(define_insn "*and<mode>3"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
+ (match_operand:GPR 2 "gpc_reg_operand" "r")))]
+ ""
+ "and %0,%1,%2"
+ [(set_attr "type" "logical")])
-(define_insn "*andsi3_internal2_mc"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
- (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
- (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
+(define_insn_and_split "*and<mode>3_dot"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
- (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
- "TARGET_32BIT && rs6000_gen_cell_microcode"
- "@
- and. %3,%1,%2
- andi. %3,%1,%b2
- andis. %3,%1,%u2
- rlwinm. %3,%1,0,%m2,%M2
- #
- #
- #
+ (clobber (match_scratch:GPR 0 "=r,r"))]
+ "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "@
+ and. %0,%1,%2
#"
- [(set_attr "type" "logical,logical,logical,shift,\
- compare,compare,compare,compare")
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+ [(set (match_dup 0)
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
+ [(set_attr "type" "logical")
(set_attr "dot" "yes")
- (set_attr "length" "4,4,4,4,8,8,8,8")])
+ (set_attr "length" "4,8")])
-(define_insn "*andsi3_internal3_mc"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
- (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
- (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
+(define_insn_and_split "*and<mode>3_dot2"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
- (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
- "TARGET_64BIT && rs6000_gen_cell_microcode"
+ (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+ (and:GPR (match_dup 1)
+ (match_dup 2)))]
+ "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
"@
- #
- andi. %3,%1,%b2
- andis. %3,%1,%u2
- rlwinm. %3,%1,0,%m2,%M2
- #
- #
- #
+ and. %0,%1,%2
#"
- [(set_attr "type" "compare,logical,logical,shift,compare,\
- compare,compare,compare")
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+ [(set (match_dup 0)
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
+ [(set_attr "type" "logical")
(set_attr "dot" "yes")
- (set_attr "length" "8,4,4,4,8,8,8,8")])
+ (set_attr "length" "4,8")])
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
- (match_operand:GPR 2 "and_operand" ""))
+
+(define_insn "and<mode>3_imm"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
+ (match_operand:GPR 2 "logical_const_operand" "n")))
+ (clobber (match_scratch:CC 3 "=x"))]
+ "rs6000_gen_cell_microcode
+ && !any_mask_operand (operands[2], <MODE>mode)"
+ "andi%e2. %0,%1,%u2"
+ [(set_attr "type" "logical")
+ (set_attr "dot" "yes")])
+
+(define_insn_and_split "*and<mode>3_imm_dot"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
+ (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
+ (match_operand:GPR 2 "logical_const_operand" "n,n"))
(const_int 0)))
- (clobber (match_scratch:GPR 3 ""))
- (clobber (match_scratch:CC 4 ""))]
- "reload_completed"
- [(parallel [(set (match_dup 3)
- (and:<MODE> (match_dup 1)
- (match_dup 2)))
+ (clobber (match_scratch:GPR 0 "=r,r"))
+ (clobber (match_scratch:CC 4 "=X,x"))]
+ "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
+ && rs6000_gen_cell_microcode
+ && !any_mask_operand (operands[2], <MODE>mode)"
+ "@
+ andi%e2. %0,%1,%u2
+ #"
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+ [(parallel [(set (match_dup 0)
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
(clobber (match_dup 4))])
- (set (match_dup 0)
- (compare:CC (match_dup 3)
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
(const_int 0)))]
- "")
-
-;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
-;; whole 64 bit reg, and we don't know what is in the high 32 bits.
+ ""
+ [(set_attr "type" "logical")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
-(define_split
- [(set (match_operand:CC 0 "cc_reg_operand" "")
- (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" ""))
+(define_insn_and_split "*and<mode>3_imm_dot2"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
+ (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
+ (match_operand:GPR 2 "logical_const_operand" "n,n"))
(const_int 0)))
- (clobber (match_scratch:SI 3 ""))
- (clobber (match_scratch:CC 4 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(parallel [(set (match_dup 3)
- (and:SI (match_dup 1)
- (match_dup 2)))
+ (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_scratch:CC 4 "=X,x"))]
+ "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
+ && rs6000_gen_cell_microcode
+ && !any_mask_operand (operands[2], <MODE>mode)"
+ "@
+ andi%e2. %0,%1,%u2
+ #"
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+ [(parallel [(set (match_dup 0)
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
(clobber (match_dup 4))])
- (set (match_dup 0)
- (compare:CC (match_dup 3)
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "logical")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
-(define_insn "*andsi3_internal4"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
- (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
- (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
+(define_insn_and_split "*and<mode>3_imm_mask_dot"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
+ (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
+ (match_operand:GPR 2 "logical_const_operand" "n,n"))
(const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
- (and:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
- "TARGET_32BIT && rs6000_gen_cell_microcode"
+ (clobber (match_scratch:GPR 0 "=r,r"))]
+ "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
+ && rs6000_gen_cell_microcode
+ && any_mask_operand (operands[2], <MODE>mode)"
"@
- and. %0,%1,%2
- andi. %0,%1,%b2
- andis. %0,%1,%u2
- rlwinm. %0,%1,0,%m2,%M2
- #
- #
- #
+ andi%e2. %0,%1,%u2
#"
- [(set_attr "type" "logical,logical,logical,shift,\
- compare,compare,compare,compare")
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+ [(set (match_dup 0)
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
+ [(set_attr "type" "logical")
(set_attr "dot" "yes")
- (set_attr "length" "4,4,4,4,8,8,8,8")])
+ (set_attr "length" "4,8")])
-(define_insn "*andsi3_internal5_mc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
- (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
- (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
+(define_insn_and_split "*and<mode>3_imm_mask_dot2"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
+ (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
+ (match_operand:GPR 2 "logical_const_operand" "n,n"))
(const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
- (and:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
- "TARGET_64BIT && rs6000_gen_cell_microcode"
+ (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+ (and:GPR (match_dup 1)
+ (match_dup 2)))]
+ "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
+ && rs6000_gen_cell_microcode
+ && any_mask_operand (operands[2], <MODE>mode)"
"@
- #
- andi. %0,%1,%b2
- andis. %0,%1,%u2
- rlwinm. %0,%1,0,%m2,%M2
- #
- #
- #
+ andi%e2. %0,%1,%u2
#"
- [(set_attr "type" "compare,logical,logical,shift,compare,\
- compare,compare,compare")
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+ [(set (match_dup 0)
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
+ [(set_attr "type" "logical")
(set_attr "dot" "yes")
- (set_attr "length" "8,4,4,4,8,8,8,8")])
+ (set_attr "length" "4,8")])
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "and_operand" ""))
+
+(define_insn "*and<mode>3_mask"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+ (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
+ (match_operand:GPR 2 "any_mask_operand" "S,T")))]
+ ""
+ "@
+ rldic%B2 %0,%1,0,%S2
+ rlwinm %0,%1,0,%m2,%M2"
+ [(set_attr "type" "shift")])
+
+(define_insn_and_split "*and<mode>3_mask_dot"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
+ (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
+ (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
(const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (and:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_scratch:CC 4 ""))]
- "reload_completed"
- [(parallel [(set (match_dup 0)
- (and:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 4))])
+ (clobber (match_scratch:GPR 0 "=r,r,r,r"))]
+ "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
+ && rs6000_gen_cell_microcode
+ && !logical_const_operand (operands[2], <MODE>mode)"
+ "@
+ rldic%B2. %0,%1,0,%S2
+ rlwinm. %0,%1,0,%m2,%M2
+ #
+ #"
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+ [(set (match_dup 0)
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,4,8,8")])
-(define_split
- [(set (match_operand:CC 3 "cc_reg_operand" "")
- (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" ""))
+(define_insn_and_split "*and<mode>3_mask_dot2"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
+ (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
+ (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
(const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (and:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_scratch:CC 4 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(parallel [(set (match_dup 0)
- (and:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_dup 4))])
+ (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
+ (and:GPR (match_dup 1)
+ (match_dup 2)))]
+ "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
+ && rs6000_gen_cell_microcode
+ && !logical_const_operand (operands[2], <MODE>mode)"
+ "@
+ rldic%B2. %0,%1,0,%S2
+ rlwinm. %0,%1,0,%m2,%M2
+ #
+ #"
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+ [(set (match_dup 0)
+ (and:GPR (match_dup 1)
+ (match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,4,8,8")])
+
+
+
+(define_insn "andsi3_internal0_nomc"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
+ (match_operand:SI 2 "and_operand" "?r,T")))]
+ "!rs6000_gen_cell_microcode"
+ "@
+ and %0,%1,%2
+ rlwinm %0,%1,0,%m2,%M2"
+ [(set_attr "type" "logical,shift")])
+
;; Handle the PowerPC64 rlwinm corner case
}"
[(set_attr "length" "8")])
-(define_expand "iorsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
+
+(define_expand "ior<mode>3"
+ [(set (match_operand:SDI 0 "gpc_reg_operand" "")
+ (ior:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
+ (match_operand:SDI 2 "reg_or_cint_operand" "")))]
""
- "
{
- if (GET_CODE (operands[2]) == CONST_INT
- && ! logical_operand (operands[2], SImode))
+ if (<MODE>mode == DImode && !TARGET_POWERPC64)
+ {
+ rs6000_split_logical (operands, IOR, false, false, false);
+ DONE;
+ }
+
+ if (non_logical_cint_operand (operands[2], <MODE>mode))
{
- HOST_WIDE_INT value = INTVAL (operands[2]);
rtx tmp = ((!can_create_pseudo_p ()
|| rtx_equal_p (operands[0], operands[1]))
- ? operands[0] : gen_reg_rtx (SImode));
+ ? operands[0] : gen_reg_rtx (<MODE>mode));
+ HOST_WIDE_INT value = INTVAL (operands[2]);
- emit_insn (gen_iorsi3 (tmp, operands[1],
+ emit_insn (gen_ior<mode>3 (tmp, operands[1],
GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
- emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
+
+ emit_insn (gen_ior<mode>3 (operands[0], tmp, GEN_INT (value & 0xffff)));
DONE;
}
-}")
-(define_expand "xorsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
+ if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
+ operands[2] = force_reg (<MODE>mode, operands[2]);
+})
+
+(define_expand "xor<mode>3"
+ [(set (match_operand:SDI 0 "gpc_reg_operand" "")
+ (xor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
+ (match_operand:SDI 2 "reg_or_cint_operand" "")))]
""
- "
{
- if (GET_CODE (operands[2]) == CONST_INT
- && ! logical_operand (operands[2], SImode))
+ if (<MODE>mode == DImode && !TARGET_POWERPC64)
+ {
+ rs6000_split_logical (operands, XOR, false, false, false);
+ DONE;
+ }
+
+ if (non_logical_cint_operand (operands[2], <MODE>mode))
{
- HOST_WIDE_INT value = INTVAL (operands[2]);
rtx tmp = ((!can_create_pseudo_p ()
|| rtx_equal_p (operands[0], operands[1]))
- ? operands[0] : gen_reg_rtx (SImode));
+ ? operands[0] : gen_reg_rtx (<MODE>mode));
+ HOST_WIDE_INT value = INTVAL (operands[2]);
- emit_insn (gen_xorsi3 (tmp, operands[1],
+ emit_insn (gen_xor<mode>3 (tmp, operands[1],
GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
- emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
+
+ emit_insn (gen_xor<mode>3 (operands[0], tmp, GEN_INT (value & 0xffff)));
DONE;
}
-}")
-(define_insn "*boolsi3_internal1"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
- (match_operator:SI 3 "boolean_or_operator"
- [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
- (match_operand:SI 2 "logical_operand" "r,K,L")]))]
+ if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
+ operands[2] = force_reg (<MODE>mode, operands[2]);
+})
+
+(define_insn "*bool<mode>3"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (match_operator:GPR 3 "boolean_or_operator"
+ [(match_operand:GPR 1 "gpc_reg_operand" "r")
+ (match_operand:GPR 2 "gpc_reg_operand" "r")]))]
""
- "@
- %q3 %0,%1,%2
- %q3i %0,%1,%b2
- %q3is %0,%1,%u2")
+ "%q3 %0,%1,%2"
+ [(set_attr "type" "logical")])
-(define_insn "*boolsi3_internal2"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (match_operator:SI 4 "boolean_or_operator"
- [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r")])
+(define_insn "*bool<mode>3_imm"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (match_operator:GPR 3 "boolean_or_operator"
+ [(match_operand:GPR 1 "gpc_reg_operand" "%r")
+ (match_operand:GPR 2 "logical_const_operand" "n")]))]
+ ""
+ "%q3i%e2 %0,%1,%u2"
+ [(set_attr "type" "logical")])
+
+(define_insn_and_split "*bool<mode>3_dot"
+ [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
+ (compare:CC (match_operator:GPR 3 "boolean_or_operator"
+ [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
(const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "TARGET_32BIT"
+ (clobber (match_scratch:GPR 0 "=r,r"))]
+ "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
"@
- %q4. %3,%1,%2
+ %q3. %0,%1,%2
#"
- [(set_attr "type" "logical,compare")
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
+ [(set (match_dup 0)
+ (match_dup 3))
+ (set (match_dup 4)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
+ [(set_attr "type" "logical")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (match_operator:SI 4 "boolean_operator"
- [(match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" "")])
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "TARGET_32BIT && reload_completed"
- [(set (match_dup 3) (match_dup 4))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*boolsi3_internal3"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (match_operator:SI 4 "boolean_operator"
- [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r")])
+(define_insn_and_split "*bool<mode>3_dot2"
+ [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
+ (compare:CC (match_operator:GPR 3 "boolean_or_operator"
+ [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
(const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (match_dup 4))]
- "TARGET_32BIT"
+ (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+ (match_dup 3))]
+ "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
"@
- %q4. %0,%1,%2
+ %q3. %0,%1,%2
#"
- [(set_attr "type" "logical,compare")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (match_operator:SI 4 "boolean_operator"
- [(match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" "")])
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (match_dup 4))]
- "TARGET_32BIT && reload_completed"
- [(set (match_dup 0) (match_dup 4))
- (set (match_dup 3)
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
+ [(set (match_dup 0)
+ (match_dup 3))
+ (set (match_dup 4)
(compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "logical")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
;; Split a logical operation that we can't do in one insn into two insns,
;; each of which does one 16-bit part. This is used by combine.
(define_split
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (match_operator:SI 3 "boolean_or_operator"
- [(match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "non_logical_cint_operand" "")]))]
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "")
+ (match_operator:GPR 3 "boolean_or_operator"
+ [(match_operand:GPR 1 "gpc_reg_operand" "")
+ (match_operand:GPR 2 "non_logical_cint_operand" "")]))]
""
[(set (match_dup 0) (match_dup 4))
(set (match_dup 0) (match_dup 5))]
-"
{
rtx i;
i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
- operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
+ operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
operands[1], i);
i = GEN_INT (INTVAL (operands[2]) & 0xffff);
- operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
+ operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
operands[0], i);
-}")
+})
-(define_insn "*boolcsi3_internal1"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (match_operator:SI 3 "boolean_operator"
- [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
- (match_operand:SI 2 "gpc_reg_operand" "r")]))]
+
+(define_insn "*boolc<mode>3"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (match_operator:GPR 3 "boolean_operator"
+ [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))
+ (match_operand:GPR 1 "gpc_reg_operand" "r")]))]
""
- "%q3 %0,%2,%1")
+ "%q3 %0,%1,%2"
+ [(set_attr "type" "logical")])
-(define_insn "*boolcsi3_internal2"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (match_operator:SI 4 "boolean_operator"
- [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
- (match_operand:SI 2 "gpc_reg_operand" "r,r")])
+(define_insn_and_split "*boolc<mode>3_dot"
+ [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
+ (compare:CC (match_operator:GPR 3 "boolean_operator"
+ [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
+ (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
(const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "TARGET_32BIT"
+ (clobber (match_scratch:GPR 0 "=r,r"))]
+ "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
"@
- %q4. %3,%2,%1
+ %q3. %0,%1,%2
#"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (match_operator:SI 4 "boolean_operator"
- [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
- (match_operand:SI 2 "gpc_reg_operand" "")])
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "TARGET_32BIT && reload_completed"
- [(set (match_dup 3) (match_dup 4))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
+ [(set (match_dup 0)
+ (match_dup 3))
+ (set (match_dup 4)
+ (compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "logical")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
-(define_insn "*boolcsi3_internal3"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (match_operator:SI 4 "boolean_operator"
- [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
- (match_operand:SI 2 "gpc_reg_operand" "r,r")])
+(define_insn_and_split "*boolc<mode>3_dot2"
+ [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
+ (compare:CC (match_operator:GPR 3 "boolean_operator"
+ [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
+ (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
(const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (match_dup 4))]
- "TARGET_32BIT"
+ (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+ (match_dup 3))]
+ "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
"@
- %q4. %0,%2,%1
+ %q3. %0,%1,%2
#"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (match_operator:SI 4 "boolean_operator"
- [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
- (match_operand:SI 2 "gpc_reg_operand" "")])
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (match_dup 4))]
- "TARGET_32BIT && reload_completed"
- [(set (match_dup 0) (match_dup 4))
- (set (match_dup 3)
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
+ [(set (match_dup 0)
+ (match_dup 3))
+ (set (match_dup 4)
(compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "logical")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
-(define_insn "*boolccsi3_internal1"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (match_operator:SI 3 "boolean_operator"
- [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
- (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
+
+(define_insn "*boolcc<mode>3"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (match_operator:GPR 3 "boolean_operator"
+ [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
+ (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))]))]
""
- "%q3 %0,%1,%2")
+ "%q3 %0,%1,%2"
+ [(set_attr "type" "logical")])
-(define_insn "*boolccsi3_internal2"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (match_operator:SI 4 "boolean_operator"
- [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
- (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
+(define_insn_and_split "*boolcc<mode>3_dot"
+ [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
+ (compare:CC (match_operator:GPR 3 "boolean_operator"
+ [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
+ (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
(const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "TARGET_32BIT"
+ (clobber (match_scratch:GPR 0 "=r,r"))]
+ "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
"@
- %q4. %3,%1,%2
+ %q3. %0,%1,%2
#"
- [(set_attr "type" "logical,compare")
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
+ [(set (match_dup 0)
+ (match_dup 3))
+ (set (match_dup 4)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
+ [(set_attr "type" "logical")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (match_operator:SI 4 "boolean_operator"
- [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
- (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "TARGET_32BIT && reload_completed"
- [(set (match_dup 3) (match_dup 4))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*boolccsi3_internal3"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (match_operator:SI 4 "boolean_operator"
- [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
- (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
+(define_insn_and_split "*boolcc<mode>3_dot2"
+ [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
+ (compare:CC (match_operator:GPR 3 "boolean_operator"
+ [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
+ (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
(const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (match_dup 4))]
- "TARGET_32BIT"
+ (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+ (match_dup 3))]
+ "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
"@
- %q4. %0,%1,%2
+ %q3. %0,%1,%2
#"
- [(set_attr "type" "logical,compare")
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
+ [(set (match_dup 0)
+ (match_dup 3))
+ (set (match_dup 4)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
+ [(set_attr "type" "logical")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (match_operator:SI 4 "boolean_operator"
- [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
- (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (match_dup 4))]
- "TARGET_32BIT && reload_completed"
- [(set (match_dup 0) (match_dup 4))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
+
+;; TODO: Should have dots of this as well.
+(define_insn "*eqv<mode>3"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (not:GPR (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
+ (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
+ ""
+ "eqv %0,%1,%2"
+ [(set_attr "type" "logical")])
\f
;; Rotate and shift insns, in all their variants. These support shifts,
;; field inserts and extracts, and various combinations thereof.
; We don't define lfiwax/lfiwzx with the normal definition, because we
; don't want to support putting SImode in FPR registers.
(define_insn "lfiwax"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
UNSPEC_LFIWAX))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
(float:SFDF
(sign_extend:DI
- (match_operand:SI 1 "memory_operand" "Z,Z"))))
+ (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
(clobber (match_scratch:DI 2 "=0,d"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
&& <SI_CONVERT_FP>"
(set_attr "type" "fpload")])
(define_insn "lfiwzx"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
UNSPEC_LFIWZX))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
(unsigned_float:SFDF
(zero_extend:DI
- (match_operand:SI 1 "memory_operand" "Z,Z"))))
+ (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
(clobber (match_scratch:DI 2 "=0,d"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
&& <SI_CONVERT_FP>"
(define_expand "floatdisf2_internal2"
[(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
(const_int 53)))
- (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
- (const_int 2047)))
- (clobber (scratch:CC))])
+ (set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
+ (const_int 2047)))
(set (match_dup 3) (plus:DI (match_dup 3)
(const_int 1)))
(set (match_dup 0) (plus:DI (match_dup 0)
(const_int 2)))
(set (match_dup 0) (ior:DI (match_dup 0)
(match_dup 1)))
- (parallel [(set (match_dup 0) (and:DI (match_dup 0)
- (const_int -2048)))
- (clobber (scratch:CC))])
+ (set (match_dup 0) (and:DI (match_dup 0)
+ (const_int -2048)))
(set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
(label_ref (match_operand:DI 2 "" ""))
(pc)))
return (WORDS_BIG_ENDIAN)
? \"subfic %L0,%L1,0\;subfze %0,%1\"
: \"subfic %0,%1,0\;subfze %L0,%L1\";
-}"
- [(set_attr "type" "two")
- (set_attr "length" "8")])
-
-(define_insn "mulsidi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
- (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
- "! TARGET_POWERPC64"
-{
- return (WORDS_BIG_ENDIAN)
- ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
- : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
-}
- [(set_attr "type" "mul")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
- (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
- "! TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (truncate:SI
- (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
- (sign_extend:DI (match_dup 2)))
- (const_int 32))))
- (set (match_dup 4)
- (mult:SI (match_dup 1)
- (match_dup 2)))]
- "
-{
- int endian = (WORDS_BIG_ENDIAN == 0);
- operands[3] = operand_subword (operands[0], endian, 0, DImode);
- operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
-}")
-
-(define_insn "umulsidi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
- "! TARGET_POWERPC64"
- "*
-{
- return (WORDS_BIG_ENDIAN)
- ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
- : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
-}"
- [(set_attr "type" "mul")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
- (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
- "! TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (truncate:SI
- (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
- (zero_extend:DI (match_dup 2)))
- (const_int 32))))
- (set (match_dup 4)
- (mult:SI (match_dup 1)
- (match_dup 2)))]
- "
-{
- int endian = (WORDS_BIG_ENDIAN == 0);
- operands[3] = operand_subword (operands[0], endian, 0, DImode);
- operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
-}")
-
-(define_insn "smulsi3_highpart"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (truncate:SI
- (lshiftrt:DI (mult:DI (sign_extend:DI
- (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (sign_extend:DI
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (const_int 32))))]
- ""
- "mulhw %0,%1,%2"
- [(set_attr "type" "mul")])
-
-(define_insn "umulsi3_highpart"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (truncate:SI
- (lshiftrt:DI (mult:DI (zero_extend:DI
- (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (zero_extend:DI
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (const_int 32))))]
- ""
- "mulhwu %0,%1,%2"
- [(set_attr "type" "mul")])
-
-;; Shift by a variable amount is too complex to be worth open-coding. We
-;; just handle shifts by constants.
-(define_insn "ashrdi3_no_power"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
- (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "const_int_operand" "M,i")))]
- "!TARGET_POWERPC64"
- "*
-{
- switch (which_alternative)
- {
- default:
- gcc_unreachable ();
- case 0:
- if (WORDS_BIG_ENDIAN)
- return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
- else
- return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
- case 1:
- if (WORDS_BIG_ENDIAN)
- return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
- else
- return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
- }
-}"
- [(set_attr "type" "two,three")
- (set_attr "length" "8,12")])
-
-(define_insn "*ashrdisi3_noppc64be"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (const_int 32)) 4))]
- "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
- "*
-{
- if (REGNO (operands[0]) == REGNO (operands[1]))
- return \"\";
- else
- return \"mr %0,%1\";
-}"
- [(set_attr "length" "4")])
-
-\f
-;; PowerPC64 DImode operations.
-
-(define_insn "muldi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
- (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
- "TARGET_POWERPC64"
- "@
- mulld %0,%1,%2
- mulli %0,%1,%2"
- [(set_attr "type" "mul")
- (set (attr "size")
- (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
- (const_string "8")
- (match_operand:SI 2 "short_cint_operand" "")
- (const_string "16")]
- (const_string "64")))])
-
-(define_insn "*muldi3_internal1"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
- (match_operand:DI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r"))]
- "TARGET_POWERPC64"
- "@
- mulld. %3,%1,%2
- #"
- [(set_attr "type" "mul")
- (set_attr "size" "64")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (mult:DI (match_dup 1) (match_dup 2)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*muldi3_internal2"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
- (match_operand:DI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (mult:DI (match_dup 1) (match_dup 2)))]
- "TARGET_POWERPC64"
- "@
- mulld. %0,%1,%2
- #"
- [(set_attr "type" "mul")
- (set_attr "size" "64")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (mult:DI (match_dup 1) (match_dup 2)))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (mult:DI (match_dup 1) (match_dup 2)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "smuldi3_highpart"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (truncate:DI
- (lshiftrt:TI (mult:TI (sign_extend:TI
- (match_operand:DI 1 "gpc_reg_operand" "%r"))
- (sign_extend:TI
- (match_operand:DI 2 "gpc_reg_operand" "r")))
- (const_int 64))))]
- "TARGET_POWERPC64"
- "mulhd %0,%1,%2"
- [(set_attr "type" "mul")
- (set_attr "size" "64")])
-
-(define_insn "umuldi3_highpart"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (truncate:DI
- (lshiftrt:TI (mult:TI (zero_extend:TI
- (match_operand:DI 1 "gpc_reg_operand" "%r"))
- (zero_extend:TI
- (match_operand:DI 2 "gpc_reg_operand" "r")))
- (const_int 64))))]
- "TARGET_POWERPC64"
- "mulhdu %0,%1,%2"
- [(set_attr "type" "mul")
- (set_attr "size" "64")])
-
-(define_expand "mulditi3"
- [(set (match_operand:TI 0 "gpc_reg_operand")
- (mult:TI (sign_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
- (sign_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
- "TARGET_POWERPC64"
-{
- rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
- emit_insn (gen_muldi3 (l, operands[1], operands[2]));
- emit_insn (gen_smuldi3_highpart (h, operands[1], operands[2]));
- emit_move_insn (gen_lowpart (DImode, operands[0]), l);
- emit_move_insn (gen_highpart (DImode, operands[0]), h);
- DONE;
-})
-
-(define_expand "umulditi3"
- [(set (match_operand:TI 0 "gpc_reg_operand")
- (mult:TI (zero_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
- (zero_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
- "TARGET_POWERPC64"
-{
- rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
- emit_insn (gen_muldi3 (l, operands[1], operands[2]));
- emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2]));
- emit_move_insn (gen_lowpart (DImode, operands[0]), l);
- emit_move_insn (gen_highpart (DImode, operands[0]), h);
- DONE;
-})
-
-(define_insn "*rotldi3_internal4"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn"))
- (match_operand:DI 3 "mask64_operand" "n")))]
- "TARGET_POWERPC64"
- "rld%I2c%B3 %0,%1,%H2,%S3"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")])
-
-(define_insn "*rotldi3_internal5"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (and:DI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
- (match_operand:DI 3 "mask64_operand" "n,n"))
- (const_int 0)))
- (clobber (match_scratch:DI 4 "=r,r"))]
- "TARGET_64BIT"
- "@
- rld%I2c%B3. %4,%1,%H2,%S3
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (and:DI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" ""))
- (match_operand:DI 3 "mask64_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:DI 4 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 4)
- (and:DI (rotate:DI (match_dup 1)
- (match_dup 2))
- (match_dup 3)))
- (set (match_dup 0)
- (compare:CC (match_dup 4)
- (const_int 0)))]
- "")
-
-(define_insn "*rotldi3_internal6"
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC (and:DI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
- (match_operand:DI 3 "mask64_operand" "n,n"))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_64BIT"
- "@
- rld%I2c%B3. %0,%1,%H2,%S3
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (and:DI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" ""))
- (match_operand:DI 3 "mask64_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*rotldi3_internal7le"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
- "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
- "rld%I2cl %0,%1,%H2,56"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")])
-
-(define_insn "*rotldi3_internal7be"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn")) 7)))]
- "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
- "rld%I2cl %0,%1,%H2,56"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")])
-
-(define_insn "*rotldi3_internal8le"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r"))]
- "TARGET_64BIT && !BYTES_BIG_ENDIAN"
- "@
- rld%I2cl. %3,%1,%H2,56
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn "*rotldi3_internal8be"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r"))]
- "TARGET_64BIT && BYTES_BIG_ENDIAN"
- "@
- rld%I2cl. %3,%1,%H2,56
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:DI (subreg:QI
- (rotate:DI (match_dup 1)
- (match_dup 2)) 0)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:DI (subreg:QI
- (rotate:DI (match_dup 1)
- (match_dup 2)) 7)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*rotldi3_internal9le"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
- "TARGET_64BIT && !BYTES_BIG_ENDIAN"
- "@
- rld%I2cl. %0,%1,%H2,56
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn "*rotldi3_internal9be"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
- "TARGET_64BIT && BYTES_BIG_ENDIAN"
- "@
- rld%I2cl. %0,%1,%H2,56
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
+}"
+ [(set_attr "type" "two")
+ (set_attr "length" "8")])
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
- "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
- "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
+;; Shift by a variable amount is too complex to be worth open-coding. We
+;; just handle shifts by constants.
+(define_insn "ashrdi3_no_power"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
+ (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "const_int_operand" "M,i")))]
+ "!TARGET_POWERPC64"
+ "*
+{
+ switch (which_alternative)
+ {
+ default:
+ gcc_unreachable ();
+ case 0:
+ if (WORDS_BIG_ENDIAN)
+ return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
+ else
+ return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
+ case 1:
+ if (WORDS_BIG_ENDIAN)
+ return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
+ else
+ return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
+ }
+}"
+ [(set_attr "type" "two,three")
+ (set_attr "length" "8,12")])
-(define_insn "*rotldi3_internal10le"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
- "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
- "rld%I2cl %0,%1,%H2,48"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")])
+(define_insn "*ashrdisi3_noppc64be"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (const_int 32)) 4))]
+ "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
+ "*
+{
+ if (REGNO (operands[0]) == REGNO (operands[1]))
+ return \"\";
+ else
+ return \"mr %0,%1\";
+}"
+ [(set_attr "length" "4")])
-(define_insn "*rotldi3_internal10be"
+\f
+;; PowerPC64 DImode operations.
+
+(define_insn "*rotldi3_internal4"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn")) 6)))]
- "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
- "rld%I2cl %0,%1,%H2,48"
+ (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "reg_or_cint_operand" "rn"))
+ (match_operand:DI 3 "mask64_operand" "n")))]
+ "TARGET_POWERPC64"
+ "rld%I2c%B3 %0,%1,%H2,%S3"
[(set_attr "type" "shift")
(set_attr "maybe_var_shift" "yes")])
-(define_insn "*rotldi3_internal11le"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r"))]
- "TARGET_64BIT && !BYTES_BIG_ENDIAN"
- "@
- rld%I2cl. %3,%1,%H2,48
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn "*rotldi3_internal11be"
+(define_insn "*rotldi3_internal5"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
+ (compare:CC (and:DI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
+ (match_operand:DI 3 "mask64_operand" "n,n"))
(const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r"))]
- "TARGET_64BIT && BYTES_BIG_ENDIAN"
+ (clobber (match_scratch:DI 4 "=r,r"))]
+ "TARGET_64BIT"
"@
- rld%I2cl. %3,%1,%H2,48
+ rld%I2c%B3. %4,%1,%H2,%S3
#"
[(set_attr "type" "shift")
(set_attr "maybe_var_shift" "yes")
(define_split
[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:DI (subreg:HI
- (rotate:DI (match_dup 1)
- (match_dup 2)) 0)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
+ (compare:CC (and:DI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "reg_or_cint_operand" ""))
+ (match_operand:DI 3 "mask64_operand" ""))
(const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:DI (subreg:HI
- (rotate:DI (match_dup 1)
- (match_dup 2)) 6)))
+ (clobber (match_scratch:DI 4 ""))]
+ "TARGET_POWERPC64 && reload_completed"
+ [(set (match_dup 4)
+ (and:DI (rotate:DI (match_dup 1)
+ (match_dup 2))
+ (match_dup 3)))
(set (match_dup 0)
- (compare:CC (match_dup 3)
+ (compare:CC (match_dup 4)
(const_int 0)))]
"")
-(define_insn "*rotldi3_internal12le"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
- "TARGET_64BIT && !BYTES_BIG_ENDIAN"
- "@
- rld%I2cl. %0,%1,%H2,48
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn "*rotldi3_internal12be"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
+(define_insn "*rotldi3_internal6"
+ [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
+ (compare:CC (and:DI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
+ (match_operand:DI 3 "mask64_operand" "n,n"))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
- "TARGET_64BIT && BYTES_BIG_ENDIAN"
+ (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
+ "TARGET_64BIT"
"@
- rld%I2cl. %0,%1,%H2,48
+ rld%I2c%B3. %0,%1,%H2,%S3
#"
[(set_attr "type" "shift")
(set_attr "maybe_var_shift" "yes")
(set_attr "length" "4,8")])
(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
- "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
+ [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
+ (compare:CC (and:DI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "reg_or_cint_operand" ""))
+ (match_operand:DI 3 "mask64_operand" ""))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
- "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
+ (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
+ "TARGET_POWERPC64 && reload_completed"
[(set (match_dup 0)
- (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
- (set (match_dup 3)
+ (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
+ (set (match_dup 4)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
-(define_insn "*rotldi3_internal13le"
+(define_insn "*rotldi3_internal7le"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(zero_extend:DI
- (subreg:SI
+ (subreg:QI
(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
"TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
- "rld%I2cl %0,%1,%H2,32"
+ "rld%I2cl %0,%1,%H2,56"
[(set_attr "type" "shift")
(set_attr "maybe_var_shift" "yes")])
-(define_insn "*rotldi3_internal13be"
+(define_insn "*rotldi3_internal7be"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(zero_extend:DI
- (subreg:SI
+ (subreg:QI
(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn")) 4)))]
+ (match_operand:DI 2 "reg_or_cint_operand" "rn")) 7)))]
"TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
- "rld%I2cl %0,%1,%H2,32"
+ "rld%I2cl %0,%1,%H2,56"
[(set_attr "type" "shift")
(set_attr "maybe_var_shift" "yes")])
-(define_insn "*rotldi3_internal14le"
+(define_insn "*rotldi3_internal8le"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC (zero_extend:DI
- (subreg:SI
+ (subreg:QI
(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
"TARGET_64BIT && !BYTES_BIG_ENDIAN"
"@
- rld%I2cl. %3,%1,%H2,32
+ rld%I2cl. %3,%1,%H2,56
#"
[(set_attr "type" "shift")
(set_attr "maybe_var_shift" "yes")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
-(define_insn "*rotldi3_internal14be"
+(define_insn "*rotldi3_internal8be"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC (zero_extend:DI
- (subreg:SI
+ (subreg:QI
(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
+ (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
"TARGET_64BIT && BYTES_BIG_ENDIAN"
"@
- rld%I2cl. %3,%1,%H2,32
+ rld%I2cl. %3,%1,%H2,56
#"
[(set_attr "type" "shift")
(set_attr "maybe_var_shift" "yes")
(define_split
[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
(compare:CC (zero_extend:DI
- (subreg:SI
+ (subreg:QI
(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
(match_operand:DI 2 "reg_or_cint_operand" "")) 0))
(const_int 0)))
(clobber (match_scratch:DI 3 ""))]
"TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
[(set (match_dup 3)
- (zero_extend:DI (subreg:SI
+ (zero_extend:DI (subreg:QI
(rotate:DI (match_dup 1)
(match_dup 2)) 0)))
(set (match_dup 0)
(define_split
[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
(compare:CC (zero_extend:DI
- (subreg:SI
+ (subreg:QI
(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
+ (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
(const_int 0)))
(clobber (match_scratch:DI 3 ""))]
"TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
[(set (match_dup 3)
- (zero_extend:DI (subreg:SI
+ (zero_extend:DI (subreg:QI
(rotate:DI (match_dup 1)
- (match_dup 2)) 4)))
+ (match_dup 2)) 7)))
(set (match_dup 0)
(compare:CC (match_dup 3)
(const_int 0)))]
"")
-(define_insn "*rotldi3_internal15le"
+(define_insn "*rotldi3_internal9le"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC (zero_extend:DI
- (subreg:SI
+ (subreg:QI
(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
+ (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
"TARGET_64BIT && !BYTES_BIG_ENDIAN"
"@
- rld%I2cl. %0,%1,%H2,32
+ rld%I2cl. %0,%1,%H2,56
#"
[(set_attr "type" "shift")
(set_attr "maybe_var_shift" "yes")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
-(define_insn "*rotldi3_internal15be"
+(define_insn "*rotldi3_internal9be"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC (zero_extend:DI
- (subreg:SI
+ (subreg:QI
(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
+ (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
+ (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
"TARGET_64BIT && BYTES_BIG_ENDIAN"
"@
- rld%I2cl. %0,%1,%H2,32
+ rld%I2cl. %0,%1,%H2,56
#"
[(set_attr "type" "shift")
(set_attr "maybe_var_shift" "yes")
(define_split
[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
(compare:CC (zero_extend:DI
- (subreg:SI
+ (subreg:QI
(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
(match_operand:DI 2 "reg_or_cint_operand" "")) 0))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
+ (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
"TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
[(set (match_dup 0)
- (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
+ (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
(define_split
[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
(compare:CC (zero_extend:DI
- (subreg:SI
+ (subreg:QI
(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
+ (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
+ (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
"TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
[(set (match_dup 0)
- (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
+ (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
-(define_insn "*ashldi3_internal4"
+(define_insn "*rotldi3_internal10le"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "const_int_operand" "i"))
- (match_operand:DI 3 "const_int_operand" "n")))]
- "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
- "rldic %0,%1,%H2,%W3"
- [(set_attr "type" "shift")])
-
-(define_insn "ashldi3_internal5"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "const_int_operand" "i,i"))
- (match_operand:DI 3 "const_int_operand" "n,n"))
- (const_int 0)))
- (clobber (match_scratch:DI 4 "=r,r"))]
- "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
- "@
- rldic. %4,%1,%H2,%W3
- #"
- [(set_attr "type" "shift")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC
- (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "const_int_operand" ""))
- (match_operand:DI 3 "const_int_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:DI 4 ""))]
- "TARGET_POWERPC64 && reload_completed
- && includes_rldic_lshift_p (operands[2], operands[3])"
- [(set (match_dup 4)
- (and:DI (ashift:DI (match_dup 1) (match_dup 2))
- (match_dup 3)))
- (set (match_dup 0)
- (compare:CC (match_dup 4)
- (const_int 0)))]
- "")
-
-(define_insn "*ashldi3_internal6"
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "const_int_operand" "i,i"))
- (match_operand:DI 3 "const_int_operand" "n,n"))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
- "@
- rldic. %0,%1,%H2,%W3
- #"
+ (zero_extend:DI
+ (subreg:HI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
+ "rld%I2cl %0,%1,%H2,48"
[(set_attr "type" "shift")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC
- (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "const_int_operand" ""))
- (match_operand:DI 3 "const_int_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWERPC64 && reload_completed
- && includes_rldic_lshift_p (operands[2], operands[3])"
- [(set (match_dup 0)
- (and:DI (ashift:DI (match_dup 1) (match_dup 2))
- (match_dup 3)))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
+ (set_attr "maybe_var_shift" "yes")])
-(define_insn "*ashldi3_internal7"
+(define_insn "*rotldi3_internal10be"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "const_int_operand" "i"))
- (match_operand:DI 3 "mask64_operand" "n")))]
- "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
- "rldicr %0,%1,%H2,%S3"
- [(set_attr "type" "shift")])
+ (zero_extend:DI
+ (subreg:HI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "reg_or_cint_operand" "rn")) 6)))]
+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
+ "rld%I2cl %0,%1,%H2,48"
+ [(set_attr "type" "shift")
+ (set_attr "maybe_var_shift" "yes")])
-(define_insn "ashldi3_internal8"
+(define_insn "*rotldi3_internal11le"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "const_int_operand" "i,i"))
- (match_operand:DI 3 "mask64_operand" "n,n"))
- (const_int 0)))
- (clobber (match_scratch:DI 4 "=r,r"))]
- "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
+ (compare:CC (zero_extend:DI
+ (subreg:HI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 "=r,r"))]
+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"
"@
- rldicr. %4,%1,%H2,%S3
+ rld%I2cl. %3,%1,%H2,48
#"
[(set_attr "type" "shift")
+ (set_attr "maybe_var_shift" "yes")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC
- (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "const_int_operand" ""))
- (match_operand:DI 3 "mask64_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:DI 4 ""))]
- "TARGET_POWERPC64 && reload_completed
- && includes_rldicr_lshift_p (operands[2], operands[3])"
- [(set (match_dup 4)
- (and:DI (ashift:DI (match_dup 1) (match_dup 2))
- (match_dup 3)))
- (set (match_dup 0)
- (compare:CC (match_dup 4)
- (const_int 0)))]
- "")
-
-(define_insn "*ashldi3_internal9"
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "const_int_operand" "i,i"))
- (match_operand:DI 3 "mask64_operand" "n,n"))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
+(define_insn "*rotldi3_internal11be"
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
+ (compare:CC (zero_extend:DI
+ (subreg:HI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 "=r,r"))]
+ "TARGET_64BIT && BYTES_BIG_ENDIAN"
"@
- rldicr. %0,%1,%H2,%S3
+ rld%I2cl. %3,%1,%H2,48
#"
[(set_attr "type" "shift")
+ (set_attr "maybe_var_shift" "yes")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC
- (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "const_int_operand" ""))
- (match_operand:DI 3 "mask64_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWERPC64 && reload_completed
- && includes_rldicr_lshift_p (operands[2], operands[3])"
- [(set (match_dup 0)
- (and:DI (ashift:DI (match_dup 1) (match_dup 2))
- (match_dup 3)))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_expand "anddi3"
- [(parallel
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" "")))
- (clobber (match_scratch:CC 3 ""))])]
- ""
-{
- if (!TARGET_POWERPC64)
- {
- rtx cc = gen_rtx_SCRATCH (CCmode);
- rs6000_split_logical (operands, AND, false, false, false, cc);
- DONE;
- }
- else if (!and64_2_operand (operands[2], DImode))
- operands[2] = force_reg (DImode, operands[2]);
-})
-
-(define_insn "anddi3_mc"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
- (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
- (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
- (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
- "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
- "@
- and %0,%1,%2
- rldic%B2 %0,%1,0,%S2
- rlwinm %0,%1,0,%m2,%M2
- andi. %0,%1,%b2
- andis. %0,%1,%u2
- #"
- [(set_attr "type" "*,shift,shift,logical,logical,*")
- (set_attr "dot" "no,no,no,yes,yes,no")
- (set_attr "length" "4,4,4,4,4,8")])
-
-(define_insn "anddi3_nomc"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
- (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
- (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
- (clobber (match_scratch:CC 3 "=X,X,X,X"))]
- "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
- "@
- and %0,%1,%2
- rldic%B2 %0,%1,0,%S2
- rlwinm %0,%1,0,%m2,%M2
- #"
- [(set_attr "type" "*,shift,shift,*")
- (set_attr "length" "4,4,4,8")])
+(define_split
+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
+ (compare:CC (zero_extend:DI
+ (subreg:HI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 ""))]
+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
+ [(set (match_dup 3)
+ (zero_extend:DI (subreg:HI
+ (rotate:DI (match_dup 1)
+ (match_dup 2)) 0)))
+ (set (match_dup 0)
+ (compare:CC (match_dup 3)
+ (const_int 0)))]
+ "")
(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "mask64_2_operand" "")))
- (clobber (match_scratch:CC 3 ""))]
- "TARGET_POWERPC64
- && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
- && !mask_operand (operands[2], DImode)
- && !mask64_operand (operands[2], DImode)"
- [(set (match_dup 0)
- (and:DI (rotate:DI (match_dup 1)
- (match_dup 4))
- (match_dup 5)))
+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
+ (compare:CC (zero_extend:DI
+ (subreg:HI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 ""))]
+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
+ [(set (match_dup 3)
+ (zero_extend:DI (subreg:HI
+ (rotate:DI (match_dup 1)
+ (match_dup 2)) 6)))
(set (match_dup 0)
- (and:DI (rotate:DI (match_dup 0)
- (match_dup 6))
- (match_dup 7)))]
-{
- build_mask64_2_operands (operands[2], &operands[4]);
-})
+ (compare:CC (match_dup 3)
+ (const_int 0)))]
+ "")
-(define_insn "*anddi3_internal2_mc"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
- (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
- (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
+(define_insn "*rotldi3_internal12le"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC (zero_extend:DI
+ (subreg:HI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
(const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
- (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
- "TARGET_64BIT && rs6000_gen_cell_microcode"
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+ (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"
"@
- and. %3,%1,%2
- rldic%B2. %3,%1,0,%S2
- rlwinm. %3,%1,0,%m2,%M2
- andi. %3,%1,%b2
- andis. %3,%1,%u2
- #
- #
- #
- #
- #
- #
+ rld%I2cl. %0,%1,%H2,48
#"
- [(set_attr "type" "logical,shift,shift,logical,\
- logical,compare,compare,compare,compare,compare,\
- compare,compare")
+ [(set_attr "type" "shift")
+ (set_attr "maybe_var_shift" "yes")
(set_attr "dot" "yes")
- (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_operand" "")
- (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "mask64_2_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))
- (clobber (match_scratch:CC 4 ""))]
- "TARGET_64BIT && reload_completed
- && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
- && !mask_operand (operands[2], DImode)
- && !mask64_operand (operands[2], DImode)"
- [(set (match_dup 3)
- (and:DI (rotate:DI (match_dup 1)
- (match_dup 5))
- (match_dup 6)))
- (parallel [(set (match_dup 0)
- (compare:CC (and:DI (rotate:DI (match_dup 3)
- (match_dup 7))
- (match_dup 8))
- (const_int 0)))
- (clobber (match_dup 3))])]
- "
-{
- build_mask64_2_operands (operands[2], &operands[5]);
-}")
+ (set_attr "length" "4,8")])
-(define_insn "*anddi3_internal3_mc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
- (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
- (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
+(define_insn "*rotldi3_internal12be"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC (zero_extend:DI
+ (subreg:HI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
(const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
- (and:DI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
- "TARGET_64BIT && rs6000_gen_cell_microcode"
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+ (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
+ "TARGET_64BIT && BYTES_BIG_ENDIAN"
"@
- and. %0,%1,%2
- rldic%B2. %0,%1,0,%S2
- rlwinm. %0,%1,0,%m2,%M2
- andi. %0,%1,%b2
- andis. %0,%1,%u2
- #
- #
- #
- #
- #
- #
+ rld%I2cl. %0,%1,%H2,48
#"
- [(set_attr "type" "logical,shift,shift,logical,\
- logical,compare,compare,compare,compare,compare,\
- compare,compare")
+ [(set_attr "type" "shift")
+ (set_attr "maybe_var_shift" "yes")
(set_attr "dot" "yes")
- (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
+ (set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "and64_2_operand" ""))
+ (compare:CC (zero_extend:DI
+ (subreg:HI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
- (and:DI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:CC 4 ""))]
- "TARGET_64BIT && reload_completed"
- [(parallel [(set (match_dup 0)
- (and:DI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))])
+ (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
+ [(set (match_dup 0)
+ (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
(define_split
- [(set (match_operand:CC 3 "cc_reg_operand" "")
- (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "mask64_2_operand" ""))
- (const_int 0)))
+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
+ (compare:CC (zero_extend:DI
+ (subreg:HI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
+ (const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
- (and:DI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:CC 4 ""))]
- "TARGET_64BIT && reload_completed
- && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
- && !mask_operand (operands[2], DImode)
- && !mask64_operand (operands[2], DImode)"
+ (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
[(set (match_dup 0)
- (and:DI (rotate:DI (match_dup 1)
- (match_dup 5))
- (match_dup 6)))
- (parallel [(set (match_dup 3)
- (compare:CC (and:DI (rotate:DI (match_dup 0)
- (match_dup 7))
- (match_dup 8))
- (const_int 0)))
- (set (match_dup 0)
- (and:DI (rotate:DI (match_dup 0)
- (match_dup 7))
- (match_dup 8)))])]
- "
-{
- build_mask64_2_operands (operands[2], &operands[5]);
-}")
-
-(define_expand "iordi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" "")))]
- ""
-{
- if (!TARGET_POWERPC64)
- {
- rs6000_split_logical (operands, IOR, false, false, false, NULL_RTX);
- DONE;
- }
- else if (!reg_or_logical_cint_operand (operands[2], DImode))
- operands[2] = force_reg (DImode, operands[2]);
- else if (non_logical_cint_operand (operands[2], DImode))
- {
- HOST_WIDE_INT value;
- rtx tmp = ((!can_create_pseudo_p ()
- || rtx_equal_p (operands[0], operands[1]))
- ? operands[0] : gen_reg_rtx (DImode));
-
- value = INTVAL (operands[2]);
- emit_insn (gen_iordi3 (tmp, operands[1],
- GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
-
- emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
- DONE;
- }
-})
-
-(define_expand "xordi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" "")))]
- ""
-{
- if (!TARGET_POWERPC64)
- {
- rs6000_split_logical (operands, XOR, false, false, false, NULL_RTX);
- DONE;
- }
- else if (!reg_or_logical_cint_operand (operands[2], DImode))
- operands[2] = force_reg (DImode, operands[2]);
- if (non_logical_cint_operand (operands[2], DImode))
- {
- HOST_WIDE_INT value;
- rtx tmp = ((!can_create_pseudo_p ()
- || rtx_equal_p (operands[0], operands[1]))
- ? operands[0] : gen_reg_rtx (DImode));
+ (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ "")
- value = INTVAL (operands[2]);
- emit_insn (gen_xordi3 (tmp, operands[1],
- GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
+(define_insn "*rotldi3_internal13le"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (zero_extend:DI
+ (subreg:SI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
+ "rld%I2cl %0,%1,%H2,32"
+ [(set_attr "type" "shift")
+ (set_attr "maybe_var_shift" "yes")])
- emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
- DONE;
- }
-})
+(define_insn "*rotldi3_internal13be"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (zero_extend:DI
+ (subreg:SI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "reg_or_cint_operand" "rn")) 4)))]
+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
+ "rld%I2cl %0,%1,%H2,32"
+ [(set_attr "type" "shift")
+ (set_attr "maybe_var_shift" "yes")])
-(define_insn "*booldi3_internal1"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
- (match_operator:DI 3 "boolean_or_operator"
- [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
- (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
- "TARGET_POWERPC64"
+(define_insn "*rotldi3_internal14le"
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
+ (compare:CC (zero_extend:DI
+ (subreg:SI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 "=r,r"))]
+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"
"@
- %q3 %0,%1,%2
- %q3i %0,%1,%b2
- %q3is %0,%1,%u2")
+ rld%I2cl. %3,%1,%H2,32
+ #"
+ [(set_attr "type" "shift")
+ (set_attr "maybe_var_shift" "yes")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
-(define_insn "*booldi3_internal2"
+(define_insn "*rotldi3_internal14be"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (match_operator:DI 4 "boolean_or_operator"
- [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")])
- (const_int 0)))
+ (compare:CC (zero_extend:DI
+ (subreg:SI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
+ (const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
- "TARGET_64BIT"
+ "TARGET_64BIT && BYTES_BIG_ENDIAN"
"@
- %q4. %3,%1,%2
+ rld%I2cl. %3,%1,%H2,32
#"
- [(set_attr "type" "logical,compare")
+ [(set_attr "type" "shift")
+ (set_attr "maybe_var_shift" "yes")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (match_operator:DI 4 "boolean_operator"
- [(match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "gpc_reg_operand" "")])
- (const_int 0)))
+ (compare:CC (zero_extend:DI
+ (subreg:SI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
+ (const_int 0)))
(clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3) (match_dup 4))
+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
+ [(set (match_dup 3)
+ (zero_extend:DI (subreg:SI
+ (rotate:DI (match_dup 1)
+ (match_dup 2)) 0)))
+ (set (match_dup 0)
+ (compare:CC (match_dup 3)
+ (const_int 0)))]
+ "")
+
+(define_split
+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
+ (compare:CC (zero_extend:DI
+ (subreg:SI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 ""))]
+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
+ [(set (match_dup 3)
+ (zero_extend:DI (subreg:SI
+ (rotate:DI (match_dup 1)
+ (match_dup 2)) 4)))
(set (match_dup 0)
(compare:CC (match_dup 3)
(const_int 0)))]
"")
-(define_insn "*booldi3_internal3"
+(define_insn "*rotldi3_internal15le"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC (zero_extend:DI
+ (subreg:SI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+ (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
+ "TARGET_64BIT && !BYTES_BIG_ENDIAN"
+ "@
+ rld%I2cl. %0,%1,%H2,32
+ #"
+ [(set_attr "type" "shift")
+ (set_attr "maybe_var_shift" "yes")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
+
+(define_insn "*rotldi3_internal15be"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (match_operator:DI 4 "boolean_or_operator"
- [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")])
- (const_int 0)))
+ (compare:CC (zero_extend:DI
+ (subreg:SI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
+ (const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (match_dup 4))]
- "TARGET_64BIT"
+ (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
+ "TARGET_64BIT && BYTES_BIG_ENDIAN"
"@
- %q4. %0,%1,%2
+ rld%I2cl. %0,%1,%H2,32
#"
- [(set_attr "type" "logical,compare")
+ [(set_attr "type" "shift")
+ (set_attr "maybe_var_shift" "yes")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (match_operator:DI 4 "boolean_operator"
- [(match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "gpc_reg_operand" "")])
- (const_int 0)))
+ (compare:CC (zero_extend:DI
+ (subreg:SI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
+ (const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
- (match_dup 4))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0) (match_dup 4))
+ (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
+ "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
+ [(set (match_dup 0)
+ (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
-;; Split a logical operation that we can't do in one insn into two insns,
-;; each of which does one 16-bit part. This is used by combine.
-
(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (match_operator:DI 3 "boolean_or_operator"
- [(match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "non_logical_cint_operand" "")]))]
- "TARGET_POWERPC64"
- [(set (match_dup 0) (match_dup 4))
- (set (match_dup 0) (match_dup 5))]
-"
-{
- rtx i3,i4;
-
- i3 = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
- i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
- operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
- operands[1], i3);
- operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
- operands[0], i4);
-}")
+ [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
+ (compare:CC (zero_extend:DI
+ (subreg:SI
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "")
+ (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
+ "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
+ [(set (match_dup 0)
+ (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ "")
-(define_insn "*boolcdi3_internal1"
+(define_insn "*ashldi3_internal4"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (match_operator:DI 3 "boolean_operator"
- [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
- (match_operand:DI 2 "gpc_reg_operand" "r")]))]
- "TARGET_POWERPC64"
- "%q3 %0,%2,%1")
+ (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "const_int_operand" "i"))
+ (match_operand:DI 3 "const_int_operand" "n")))]
+ "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
+ "rldic %0,%1,%H2,%W3"
+ [(set_attr "type" "shift")])
-(define_insn "*boolcdi3_internal2"
+(define_insn "ashldi3_internal5"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (match_operator:DI 4 "boolean_operator"
- [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
- (match_operand:DI 2 "gpc_reg_operand" "r,r")])
+ (compare:CC
+ (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "const_int_operand" "i,i"))
+ (match_operand:DI 3 "const_int_operand" "n,n"))
(const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r"))]
- "TARGET_64BIT"
+ (clobber (match_scratch:DI 4 "=r,r"))]
+ "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
"@
- %q4. %3,%2,%1
+ rldic. %4,%1,%H2,%W3
#"
- [(set_attr "type" "logical,compare")
+ [(set_attr "type" "shift")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (match_operator:DI 4 "boolean_operator"
- [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
- (match_operand:DI 2 "gpc_reg_operand" "")])
+ (compare:CC
+ (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "const_int_operand" ""))
+ (match_operand:DI 3 "const_int_operand" ""))
(const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3) (match_dup 4))
+ (clobber (match_scratch:DI 4 ""))]
+ "TARGET_POWERPC64 && reload_completed
+ && includes_rldic_lshift_p (operands[2], operands[3])"
+ [(set (match_dup 4)
+ (and:DI (ashift:DI (match_dup 1) (match_dup 2))
+ (match_dup 3)))
(set (match_dup 0)
- (compare:CC (match_dup 3)
+ (compare:CC (match_dup 4)
(const_int 0)))]
"")
-(define_insn "*boolcdi3_internal3"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (match_operator:DI 4 "boolean_operator"
- [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
- (match_operand:DI 2 "gpc_reg_operand" "r,r")])
+(define_insn "*ashldi3_internal6"
+ [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
+ (compare:CC
+ (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "const_int_operand" "i,i"))
+ (match_operand:DI 3 "const_int_operand" "n,n"))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (match_dup 4))]
- "TARGET_64BIT"
+ (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
+ "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
"@
- %q4. %0,%2,%1
+ rldic. %0,%1,%H2,%W3
#"
- [(set_attr "type" "logical,compare")
+ [(set_attr "type" "shift")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (match_operator:DI 4 "boolean_operator"
- [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
- (match_operand:DI 2 "gpc_reg_operand" "")])
+ [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
+ (compare:CC
+ (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "const_int_operand" ""))
+ (match_operand:DI 3 "const_int_operand" ""))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
- (match_dup 4))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0) (match_dup 4))
- (set (match_dup 3)
+ (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
+ "TARGET_POWERPC64 && reload_completed
+ && includes_rldic_lshift_p (operands[2], operands[3])"
+ [(set (match_dup 0)
+ (and:DI (ashift:DI (match_dup 1) (match_dup 2))
+ (match_dup 3)))
+ (set (match_dup 4)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
-(define_insn "*boolccdi3_internal1"
+(define_insn "*ashldi3_internal7"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (match_operator:DI 3 "boolean_operator"
- [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
- (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
- "TARGET_POWERPC64"
- "%q3 %0,%1,%2")
+ (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "const_int_operand" "i"))
+ (match_operand:DI 3 "mask64_operand" "n")))]
+ "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
+ "rldicr %0,%1,%H2,%S3"
+ [(set_attr "type" "shift")])
-(define_insn "*boolccdi3_internal2"
+(define_insn "ashldi3_internal8"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (match_operator:DI 4 "boolean_operator"
- [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
- (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
+ (compare:CC
+ (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "const_int_operand" "i,i"))
+ (match_operand:DI 3 "mask64_operand" "n,n"))
(const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r"))]
- "TARGET_64BIT"
+ (clobber (match_scratch:DI 4 "=r,r"))]
+ "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
"@
- %q4. %3,%1,%2
+ rldicr. %4,%1,%H2,%S3
#"
- [(set_attr "type" "logical,compare")
+ [(set_attr "type" "shift")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (match_operator:DI 4 "boolean_operator"
- [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
- (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
+ (compare:CC
+ (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "const_int_operand" ""))
+ (match_operand:DI 3 "mask64_operand" ""))
(const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3) (match_dup 4))
+ (clobber (match_scratch:DI 4 ""))]
+ "TARGET_POWERPC64 && reload_completed
+ && includes_rldicr_lshift_p (operands[2], operands[3])"
+ [(set (match_dup 4)
+ (and:DI (ashift:DI (match_dup 1) (match_dup 2))
+ (match_dup 3)))
(set (match_dup 0)
- (compare:CC (match_dup 3)
+ (compare:CC (match_dup 4)
(const_int 0)))]
"")
-(define_insn "*boolccdi3_internal3"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (match_operator:DI 4 "boolean_operator"
- [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
- (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
+(define_insn "*ashldi3_internal9"
+ [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
+ (compare:CC
+ (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "const_int_operand" "i,i"))
+ (match_operand:DI 3 "mask64_operand" "n,n"))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (match_dup 4))]
- "TARGET_64BIT"
+ (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
+ "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
"@
- %q4. %0,%1,%2
+ rldicr. %0,%1,%H2,%S3
#"
- [(set_attr "type" "logical,compare")
+ [(set_attr "type" "shift")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (match_operator:DI 4 "boolean_operator"
- [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
- (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
+ [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
+ (compare:CC
+ (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "const_int_operand" ""))
+ (match_operand:DI 3 "mask64_operand" ""))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
- (match_dup 4))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0) (match_dup 4))
- (set (match_dup 3)
+ (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
+ "TARGET_POWERPC64 && reload_completed
+ && includes_rldicr_lshift_p (operands[2], operands[3])"
+ [(set (match_dup 0)
+ (and:DI (ashift:DI (match_dup 1) (match_dup 2))
+ (match_dup 3)))
+ (set (match_dup 4)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
-;; Eqv operation.
-(define_insn "*eqv<mode>3"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (not:GPR
- (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
- (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
+
+(define_insn_and_split "*anddi3_2rld"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
+ (match_operand:DI 2 "and_2rld_operand" "n")))]
+ "TARGET_POWERPC64"
+ "#"
""
- "eqv %0,%1,%2"
- [(set_attr "type" "integer")
- (set_attr "length" "4")])
+ [(set (match_dup 0)
+ (and:DI (rotate:DI (match_dup 1)
+ (match_dup 4))
+ (match_dup 5)))
+ (set (match_dup 0)
+ (and:DI (rotate:DI (match_dup 0)
+ (match_dup 6))
+ (match_dup 7)))]
+{
+ build_mask64_2_operands (operands[2], &operands[4]);
+}
+ [(set_attr "length" "8")])
+
+(define_insn_and_split "*anddi3_2rld_dot"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
+ (match_operand:DI 2 "and_2rld_operand" "n,n"))
+ (const_int 0)))
+ (clobber (match_scratch:DI 0 "=r,r"))]
+ "TARGET_64BIT && rs6000_gen_cell_microcode"
+ "@
+ #
+ #"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (and:DI (rotate:DI (match_dup 1)
+ (match_dup 4))
+ (match_dup 5)))
+ (parallel [(set (match_dup 3)
+ (compare:CC (and:DI (rotate:DI (match_dup 0)
+ (match_dup 6))
+ (match_dup 7))
+ (const_int 0)))
+ (clobber (match_dup 0))])]
+{
+ build_mask64_2_operands (operands[2], &operands[4]);
+}
+ [(set_attr "type" "compare")
+ (set_attr "dot" "yes")
+ (set_attr "length" "8,12")])
+(define_insn_and_split "*anddi3_2rld_dot2"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
+ (match_operand:DI 2 "and_2rld_operand" "n,n"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+ (and:DI (match_dup 1)
+ (match_dup 2)))]
+ "TARGET_64BIT && rs6000_gen_cell_microcode"
+ "@
+ #
+ #"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (and:DI (rotate:DI (match_dup 1)
+ (match_dup 4))
+ (match_dup 5)))
+ (parallel [(set (match_dup 3)
+ (compare:CC (and:DI (rotate:DI (match_dup 0)
+ (match_dup 6))
+ (match_dup 7))
+ (const_int 0)))
+ (set (match_dup 0)
+ (and:DI (rotate:DI (match_dup 0)
+ (match_dup 6))
+ (match_dup 7)))])]
+{
+ build_mask64_2_operands (operands[2], &operands[4]);
+}
+ [(set_attr "type" "compare")
+ (set_attr "dot" "yes")
+ (set_attr "length" "8,12")])
\f
;; 128-bit logical operations expanders
(define_expand "and<mode>3"
- [(parallel [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
- (and:BOOL_128
- (match_operand:BOOL_128 1 "vlogical_operand" "")
- (match_operand:BOOL_128 2 "vlogical_operand" "")))
- (clobber (match_scratch:CC 3 ""))])]
+ [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
+ (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
+ (match_operand:BOOL_128 2 "vlogical_operand" "")))]
""
"")
[(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
(and:BOOL_128
(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
- (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))
- (clobber (match_scratch:CC 3 "<BOOL_REGS_AND_CR0>"))]
+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))]
""
{
if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
"reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
- rs6000_split_logical (operands, AND, false, false, false, operands[3]);
+ rs6000_split_logical (operands, AND, false, false, false);
DONE;
}
[(set (attr "type")
"reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
- rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false,
- NULL_RTX);
+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false);
DONE;
}
[(set (attr "type")
&& reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
- rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
- NULL_RTX);
+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
DONE;
}
[(set (attr "type")
"reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
[(const_int 0)]
{
- rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
- NULL_RTX);
+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
DONE;
}
[(set_attr "type" "integer")
&& reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
- rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,
- NULL_RTX);
+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
DONE;
}
[(set (attr "type")
"reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
[(const_int 0)]
{
- rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,
- NULL_RTX);
+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
DONE;
}
[(set_attr "type" "integer")
&& int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
- rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);
+ rs6000_split_logical (operands, XOR, true, false, false);
DONE;
}
[(set (attr "type")
"reload_completed && !TARGET_P8_VECTOR"
[(const_int 0)]
{
- rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);
+ rs6000_split_logical (operands, XOR, true, false, false);
DONE;
}
[(set_attr "type" "integer")
"reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
- rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);
+ rs6000_split_logical (operands, NOT, false, false, false);
DONE;
}
[(set (attr "type")
; ld/std require word-aligned displacements -> 'Y' constraint.
; List Y->r and r->Y before r->r for reload.
(define_insn "*mov<mode>_hardfloat64"
- [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wm")
- (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wm,r"))]
+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wk")
+ (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wk,r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
(define_insn "*movdi_internal64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wm")
- (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wm,r"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wj,?*wi")
+ (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wj,r,O"))]
"TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"
mftgpr %0,%1
mffgpr %0,%1
mfvsrd %0,%x1
- mtvsrd %x0,%1"
- [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr")
- (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")])
+ mtvsrd %x0,%1
+ xxlxor %x0,%x0,%x0"
+ [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr,vecsimple")
+ (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4")])
;; Generate all one-bits and clear left or right.
;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
projects / platform / upstream / gcc.git / blobdiff