;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
-;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
-;; Free Software Foundation, Inc.
+;; Copyright (C) 1990-2013 Free Software Foundation, Inc.
;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
;; This file is part of GCC.
(TOC_REGNUM 2)
(STATIC_CHAIN_REGNUM 11)
(HARD_FRAME_POINTER_REGNUM 31)
- (MQ_REGNO 64)
(LR_REGNO 65)
(CTR_REGNO 66)
(ARG_POINTER_REGNUM 67)
(define_c_enum "unspec"
[UNSPEC_FRSP ; frsp for POWER machines
UNSPEC_PROBE_STACK ; probe stack memory reference
- UNSPEC_TIE ; tie stack contents and stack pointer
UNSPEC_TOCPTR ; address of a word pointing to the TOC
UNSPEC_TOC ; address of the TOC (more-or-less)
UNSPEC_MOVSI_GOT
UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
UNSPECV_EH_RR ; eh_reg_restore
UNSPECV_ISYNC ; isync instruction
+ UNSPECV_MFTB ; move from time base
])
\f
;; Define an insn type attribute. This is used in function unit delay
;; computations.
-(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel"
+(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt"
(const_string "integer"))
;; Define floating point instruction sub-types for use with Xfpu.md
;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in rs6000.h.
-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
+(define_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan"
(const (symbol_ref "rs6000_cpu_attr")))
(automata_option "ndfa")
-(include "rios1.md")
-(include "rios2.md")
(include "rs64.md")
(include "mpc.md")
(include "40x.md")
(include "440.md")
(include "476.md")
+(include "601.md")
(include "603.md")
(include "6xx.md")
(include "7xx.md")
(include "e300c2c3.md")
(include "e500mc.md")
(include "e500mc64.md")
+(include "e5500.md")
+(include "e6500.md")
(include "power4.md")
(include "power5.md")
(include "power6.md")
; Conditional returns.
(define_code_iterator any_return [return simple_return])
(define_code_attr return_pred [(return "direct_return ()")
- (simple_return "")])
+ (simple_return "1")])
(define_code_attr return_str [(return "") (simple_return "simple_")])
; Various instructions that come in SI and DI forms.
(define_mode_attr mptrsize [(SI "si")
(DI "di")])
-(define_mode_attr ptrload [(SI "{l|lwz}")
+(define_mode_attr ptrload [(SI "lwz")
(DI "ld")])
+(define_mode_attr ptrm [(SI "m")
+ (DI "Y")])
+
(define_mode_attr rreg [(SF "f")
(DF "ws")
(V4SF "wf")
""
"@
lbz%U1%X1 %0,%1
- {rlinm|rlwinm} %0,%1,0,0xff"
+ rlwinm %0,%1,0,0xff"
[(set_attr "type" "load,*")])
(define_insn ""
(clobber (match_scratch:SI 2 "=r,r"))]
""
"@
- {andil.|andi.} %2,%1,0xff
+ andi. %2,%1,0xff
#"
[(set_attr "type" "fast_compare,compare")
(set_attr "length" "4,8")])
(zero_extend:SI (match_dup 1)))]
""
"@
- {andil.|andi.} %0,%1,0xff
+ andi. %0,%1,0xff
#"
[(set_attr "type" "fast_compare,compare")
(set_attr "length" "4,8")])
(const_int 0)))]
"")
-(define_expand "extendqisi2"
- [(use (match_operand:SI 0 "gpc_reg_operand" ""))
- (use (match_operand:QI 1 "gpc_reg_operand" ""))]
- ""
- "
-{
- if (TARGET_POWERPC)
- emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
- else if (TARGET_POWER)
- emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
- else
- emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
- DONE;
-}")
-
-(define_insn "extendqisi2_ppc"
+(define_insn "extendqisi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
- "TARGET_POWERPC"
+ ""
"extsb %0,%1"
[(set_attr "type" "exts")])
(compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:SI 2 "=r,r"))]
- "TARGET_POWERPC"
+ ""
"@
extsb. %2,%1
#"
(compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 2 ""))]
- "TARGET_POWERPC && reload_completed"
+ "reload_completed"
[(set (match_dup 2)
(sign_extend:SI (match_dup 1)))
(set (match_dup 0)
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(sign_extend:SI (match_dup 1)))]
- "TARGET_POWERPC"
+ ""
"@
extsb. %0,%1
#"
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(sign_extend:SI (match_dup 1)))]
- "TARGET_POWERPC && reload_completed"
+ "reload_completed"
[(set (match_dup 0)
(sign_extend:SI (match_dup 1)))
(set (match_dup 2)
(const_int 0)))]
"")
-(define_expand "extendqisi2_power"
- [(parallel [(set (match_dup 2)
- (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
- (const_int 24)))
- (clobber (scratch:SI))])
- (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (ashiftrt:SI (match_dup 2)
- (const_int 24)))
- (clobber (scratch:SI))])]
- "TARGET_POWER"
- "
-{ operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_reg_rtx (SImode); }")
-
-(define_expand "extendqisi2_no_power"
- [(set (match_dup 2)
- (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
- (const_int 24)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ashiftrt:SI (match_dup 2)
- (const_int 24)))]
- "! TARGET_POWER && ! TARGET_POWERPC"
- "
-{ operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_reg_rtx (SImode); }")
-
-(define_expand "zero_extendqihi2"
- [(set (match_operand:HI 0 "gpc_reg_operand" "")
- (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
- ""
- "")
-
(define_insn ""
[(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
(zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
""
"@
lbz%U1%X1 %0,%1
- {rlinm|rlwinm} %0,%1,0,0xff"
+ rlwinm %0,%1,0,0xff"
[(set_attr "type" "load,*")])
(define_insn ""
(clobber (match_scratch:HI 2 "=r,r"))]
""
"@
- {andil.|andi.} %2,%1,0xff
+ andi. %2,%1,0xff
#"
[(set_attr "type" "fast_compare,compare")
(set_attr "length" "4,8")])
(zero_extend:HI (match_dup 1)))]
""
"@
- {andil.|andi.} %0,%1,0xff
+ andi. %0,%1,0xff
#"
[(set_attr "type" "fast_compare,compare")
(set_attr "length" "4,8")])
(const_int 0)))]
"")
-(define_expand "extendqihi2"
- [(use (match_operand:HI 0 "gpc_reg_operand" ""))
- (use (match_operand:QI 1 "gpc_reg_operand" ""))]
- ""
- "
-{
- if (TARGET_POWERPC)
- emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
- else if (TARGET_POWER)
- emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
- else
- emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
- DONE;
-}")
-
-(define_insn "extendqihi2_ppc"
+(define_insn "extendqihi2"
[(set (match_operand:HI 0 "gpc_reg_operand" "=r")
(sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
- "TARGET_POWERPC"
+ ""
"extsb %0,%1"
[(set_attr "type" "exts")])
(compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:HI 2 "=r,r"))]
- "TARGET_POWERPC"
+ ""
"@
extsb. %2,%1
#"
(compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:HI 2 ""))]
- "TARGET_POWERPC && reload_completed"
+ "reload_completed"
[(set (match_dup 2)
(sign_extend:HI (match_dup 1)))
(set (match_dup 0)
(const_int 0)))
(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
(sign_extend:HI (match_dup 1)))]
- "TARGET_POWERPC"
+ ""
"@
extsb. %0,%1
#"
(const_int 0)))
(set (match_operand:HI 0 "gpc_reg_operand" "")
(sign_extend:HI (match_dup 1)))]
- "TARGET_POWERPC && reload_completed"
+ "reload_completed"
[(set (match_dup 0)
(sign_extend:HI (match_dup 1)))
(set (match_dup 2)
(const_int 0)))]
"")
-(define_expand "extendqihi2_power"
- [(parallel [(set (match_dup 2)
- (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
- (const_int 24)))
- (clobber (scratch:SI))])
- (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
- (ashiftrt:SI (match_dup 2)
- (const_int 24)))
- (clobber (scratch:SI))])]
- "TARGET_POWER"
- "
-{ operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_reg_rtx (SImode); }")
-
-(define_expand "extendqihi2_no_power"
- [(set (match_dup 2)
- (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
- (const_int 24)))
- (set (match_operand:HI 0 "gpc_reg_operand" "")
- (ashiftrt:SI (match_dup 2)
- (const_int 24)))]
- "! TARGET_POWER && ! TARGET_POWERPC"
- "
-{ operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_reg_rtx (SImode); }")
-
(define_expand "zero_extendhisi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
""
"@
lhz%U1%X1 %0,%1
- {rlinm|rlwinm} %0,%1,0,0xffff"
+ rlwinm %0,%1,0,0xffff"
[(set_attr "type" "load,*")])
(define_insn ""
(clobber (match_scratch:SI 2 "=r,r"))]
""
"@
- {andil.|andi.} %2,%1,0xffff
+ andi. %2,%1,0xffff
#"
[(set_attr "type" "fast_compare,compare")
(set_attr "length" "4,8")])
(zero_extend:SI (match_dup 1)))]
""
"@
- {andil.|andi.} %0,%1,0xffff
+ andi. %0,%1,0xffff
#"
[(set_attr "type" "fast_compare,compare")
(set_attr "length" "4,8")])
"rs6000_gen_cell_microcode"
"@
lha%U1%X1 %0,%1
- {exts|extsh} %0,%1"
+ extsh %0,%1"
[(set_attr "type" "load_ext,exts")])
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
"!rs6000_gen_cell_microcode"
- "{exts|extsh} %0,%1"
+ "extsh %0,%1"
[(set_attr "type" "exts")])
(define_insn ""
(clobber (match_scratch:SI 2 "=r,r"))]
""
"@
- {exts.|extsh.} %2,%1
+ extsh. %2,%1
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(sign_extend:SI (match_dup 1)))]
""
"@
- {exts.|extsh.} %0,%1
+ extsh. %0,%1
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
+
+(define_split
+ [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
+ (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
+ (sign_extend:SI (match_dup 1)))]
+ "reload_completed"
+ [(set (match_dup 0)
+ (sign_extend:SI (match_dup 1)))
+ (set (match_dup 2)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ "")
\f
;; IBM 405, 440, 464 and 476 half-word multiplication operations.
(match_dup 1)))
(match_dup 4)))]
"TARGET_MULHW"
- "macchw. %0, %1, %2"
+ "macchw. %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*macchw"
(match_operand:HI 1 "gpc_reg_operand" "r")))
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
- "macchw %0, %1, %2"
+ "macchw %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*macchwuc"
(match_dup 1)))
(match_dup 4)))]
"TARGET_MULHW"
- "macchwu. %0, %1, %2"
+ "macchwu. %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*macchwu"
(match_operand:HI 1 "gpc_reg_operand" "r")))
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
- "macchwu %0, %1, %2"
+ "macchwu %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*machhwc"
(const_int 16)))
(match_dup 4)))]
"TARGET_MULHW"
- "machhw. %0, %1, %2"
+ "machhw. %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*machhw"
(const_int 16)))
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
- "machhw %0, %1, %2"
+ "machhw %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*machhwuc"
(const_int 16)))
(match_dup 4)))]
"TARGET_MULHW"
- "machhwu. %0, %1, %2"
+ "machhwu. %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*machhwu"
(const_int 16)))
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
- "machhwu %0, %1, %2"
+ "machhwu %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*maclhwc"
(match_dup 2)))
(match_dup 4)))]
"TARGET_MULHW"
- "maclhw. %0, %1, %2"
+ "maclhw. %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*maclhw"
(match_operand:HI 2 "gpc_reg_operand" "r")))
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
- "maclhw %0, %1, %2"
+ "maclhw %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*maclhwuc"
(match_dup 2)))
(match_dup 4)))]
"TARGET_MULHW"
- "maclhwu. %0, %1, %2"
+ "maclhwu. %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*maclhwu"
(match_operand:HI 2 "gpc_reg_operand" "r")))
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
- "maclhwu %0, %1, %2"
+ "maclhwu %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*nmacchwc"
(sign_extend:SI
(match_dup 1)))))]
"TARGET_MULHW"
- "nmacchw. %0, %1, %2"
+ "nmacchw. %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*nmacchw"
(sign_extend:SI
(match_operand:HI 1 "gpc_reg_operand" "r")))))]
"TARGET_MULHW"
- "nmacchw %0, %1, %2"
+ "nmacchw %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*nmachhwc"
(match_dup 2)
(const_int 16)))))]
"TARGET_MULHW"
- "nmachhw. %0, %1, %2"
+ "nmachhw. %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*nmachhw"
(match_operand:SI 2 "gpc_reg_operand" "r")
(const_int 16)))))]
"TARGET_MULHW"
- "nmachhw %0, %1, %2"
+ "nmachhw %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*nmaclhwc"
(sign_extend:SI
(match_dup 2)))))]
"TARGET_MULHW"
- "nmaclhw. %0, %1, %2"
+ "nmaclhw. %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*nmaclhw"
(sign_extend:SI
(match_operand:HI 2 "gpc_reg_operand" "r")))))]
"TARGET_MULHW"
- "nmaclhw %0, %1, %2"
+ "nmaclhw %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*mulchwc"
(sign_extend:SI
(match_dup 1))))]
"TARGET_MULHW"
- "mulchw. %0, %1, %2"
+ "mulchw. %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*mulchw"
(sign_extend:SI
(match_operand:HI 1 "gpc_reg_operand" "r"))))]
"TARGET_MULHW"
- "mulchw %0, %1, %2"
+ "mulchw %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*mulchwuc"
(zero_extend:SI
(match_dup 1))))]
"TARGET_MULHW"
- "mulchwu. %0, %1, %2"
+ "mulchwu. %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*mulchwu"
(zero_extend:SI
(match_operand:HI 1 "gpc_reg_operand" "r"))))]
"TARGET_MULHW"
- "mulchwu %0, %1, %2"
+ "mulchwu %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*mulhhwc"
(match_dup 2)
(const_int 16))))]
"TARGET_MULHW"
- "mulhhw. %0, %1, %2"
+ "mulhhw. %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*mulhhw"
(match_operand:SI 2 "gpc_reg_operand" "r")
(const_int 16))))]
"TARGET_MULHW"
- "mulhhw %0, %1, %2"
+ "mulhhw %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*mulhhwuc"
(match_dup 2)
(const_int 16))))]
"TARGET_MULHW"
- "mulhhwu. %0, %1, %2"
+ "mulhhwu. %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*mulhhwu"
(match_operand:SI 2 "gpc_reg_operand" "r")
(const_int 16))))]
"TARGET_MULHW"
- "mulhhwu %0, %1, %2"
+ "mulhhwu %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*mullhwc"
(sign_extend:SI
(match_dup 2))))]
"TARGET_MULHW"
- "mullhw. %0, %1, %2"
+ "mullhw. %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*mullhw"
(sign_extend:SI
(match_operand:HI 2 "gpc_reg_operand" "r"))))]
"TARGET_MULHW"
- "mullhw %0, %1, %2"
+ "mullhw %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*mullhwuc"
(zero_extend:SI
(match_dup 2))))]
"TARGET_MULHW"
- "mullhwu. %0, %1, %2"
+ "mullhwu. %0,%1,%2"
[(set_attr "type" "imul3")])
(define_insn "*mullhwu"
(zero_extend:SI
(match_operand:HI 2 "gpc_reg_operand" "r"))))]
"TARGET_MULHW"
- "mullhwu %0, %1, %2"
+ "mullhwu %0,%1,%2"
[(set_attr "type" "imul3")])
\f
;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
(match_dup 2)]
UNSPEC_DLMZB))]
"TARGET_DLMZB"
- "dlmzb. %0, %1, %2")
+ "dlmzb. %0,%1,%2")
(define_expand "strlensi"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
DONE;
})
\f
-(define_split
- [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (sign_extend:SI (match_dup 1)))]
- "reload_completed"
- [(set (match_dup 0)
- (sign_extend:SI (match_dup 1)))
- (set (match_dup 2)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
;; Fixed-point arithmetic insns.
(define_expand "add<mode>3"
(match_operand:GPR 2 "add_operand" "r,I,I,L")))]
"!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
"@
- {cax|add} %0,%1,%2
- {cal %0,%2(%1)|addi %0,%1,%2}
- {ai|addic} %0,%1,%2
- {cau|addis} %0,%1,%v2"
+ add %0,%1,%2
+ addi %0,%1,%2
+ addic %0,%1,%2
+ addis %0,%1,%v2"
[(set_attr "length" "4,4,4,4")])
(define_insn "addsi3_high"
(plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(high:SI (match_operand 2 "" ""))))]
"TARGET_MACHO && !TARGET_64BIT"
- "{cau|addis} %0,%1,ha16(%2)"
+ "addis %0,%1,ha16(%2)"
[(set_attr "length" "4")])
(define_insn "*add<mode>3_internal2"
(clobber (match_scratch:P 3 "=r,r,r,r"))]
""
"@
- {cax.|add.} %3,%1,%2
- {ai.|addic.} %3,%1,%2
+ add. %3,%1,%2
+ addic. %3,%1,%2
#
#"
[(set_attr "type" "fast_compare,compare,compare,compare")
(match_dup 2)))]
""
"@
- {cax.|add.} %0,%1,%2
- {ai.|addic.} %0,%1,%2
+ add. %0,%1,%2
+ addic. %0,%1,%2
#
#"
[(set_attr "type" "fast_compare,compare,compare,compare")
"")
(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
- (match_operand:SI 2 "gpc_reg_operand" "r")))]
- "! TARGET_POWERPC"
- "{sf%I1|subf%I1c} %0,%2,%1")
-
-(define_insn ""
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
(minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
(match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
- "TARGET_POWERPC"
+ ""
"@
subf %0,%2,%1
subfic %0,%2,%1")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "! TARGET_POWERPC"
- "@
- {sf.|subfc.} %3,%2,%1
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
(match_operand:P 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:P 3 "=r,r"))]
- "TARGET_POWERPC"
+ ""
"@
subf. %3,%2,%1
#"
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (minus:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWERPC"
- "@
- {sf.|subfc.} %0,%2,%1
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
(match_operand:P 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
(minus:P (match_dup 1)
(match_dup 2)))]
- "TARGET_POWERPC"
+ ""
"@
subf. %0,%2,%1
#"
}
}")
-;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
-;; instruction and some auxiliary computations. Then we just have a single
-;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
-;; combine.
-
-(define_expand "sminsi3"
- [(set (match_dup 3)
- (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1))))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (minus:SI (match_dup 2) (match_dup 3)))]
- "TARGET_POWER || TARGET_ISEL"
- "
-{
- if (TARGET_ISEL)
- {
- operands[2] = force_reg (SImode, operands[2]);
- rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
- DONE;
- }
-
- operands[3] = gen_reg_rtx (SImode);
-}")
-
-(define_split
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" "")))
- (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
- "TARGET_POWER"
- [(set (match_dup 3)
- (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1))))
- (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
- "")
-
-(define_expand "smaxsi3"
- [(set (match_dup 3)
- (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1))))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (plus:SI (match_dup 3) (match_dup 1)))]
- "TARGET_POWER || TARGET_ISEL"
- "
-{
- if (TARGET_ISEL)
- {
- operands[2] = force_reg (SImode, operands[2]);
- rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
- DONE;
- }
- operands[3] = gen_reg_rtx (SImode);
-}")
-
-(define_split
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" "")))
- (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
- "TARGET_POWER"
- [(set (match_dup 3)
- (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1))))
- (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
- "")
-
-(define_expand "uminsi3"
- [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_dup 5)))
- (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
- (match_dup 5)))
- (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
- (const_int 0)
- (minus:SI (match_dup 4) (match_dup 3))))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (minus:SI (match_dup 2) (match_dup 3)))]
- "TARGET_POWER || TARGET_ISEL"
- "
-{
- if (TARGET_ISEL)
- {
- rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
- DONE;
- }
- operands[3] = gen_reg_rtx (SImode);
- operands[4] = gen_reg_rtx (SImode);
- operands[5] = GEN_INT (-2147483647 - 1);
-}")
-
-(define_expand "umaxsi3"
- [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_dup 5)))
- (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
- (match_dup 5)))
- (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
- (const_int 0)
- (minus:SI (match_dup 4) (match_dup 3))))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (plus:SI (match_dup 3) (match_dup 1)))]
- "TARGET_POWER || TARGET_ISEL"
- "
-{
- if (TARGET_ISEL)
- {
- rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
- DONE;
- }
- operands[3] = gen_reg_rtx (SImode);
- operands[4] = gen_reg_rtx (SImode);
- operands[5] = GEN_INT (-2147483647 - 1);
-}")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "rI"))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1))))]
- "TARGET_POWER"
- "doz%I2 %0,%1,%2")
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1)))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "TARGET_POWER"
- "@
- doz%I2. %3,%1,%2
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1)))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 3)
- (if_then_else:SI (gt (match_dup 1) (match_dup 2))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1))))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC
- (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1)))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (if_then_else:SI (gt (match_dup 1) (match_dup 2))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1))))]
- "TARGET_POWER"
- "@
- doz%I2. %0,%1,%2
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1)))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (if_then_else:SI (gt (match_dup 1) (match_dup 2))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1))))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (if_then_else:SI (gt (match_dup 1) (match_dup 2))
- (const_int 0)
- (minus:SI (match_dup 2) (match_dup 1))))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-;; We don't need abs with condition code because such comparisons should
-;; never be done.
-(define_expand "abssi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
- ""
- "
-{
- if (TARGET_ISEL)
- {
- emit_insn (gen_abssi2_isel (operands[0], operands[1]));
- DONE;
- }
- else if (! TARGET_POWER)
- {
- emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
- DONE;
- }
-}")
-
-(define_insn "*abssi2_power"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
- "TARGET_POWER"
- "abs %0,%1")
-
-(define_insn_and_split "abs<mode>2_isel"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b")))
- (clobber (match_scratch:GPR 2 "=&b"))
- (clobber (match_scratch:CC 3 "=y"))]
- "TARGET_ISEL"
- "#"
- "&& reload_completed"
- [(set (match_dup 2) (neg:GPR (match_dup 1)))
- (set (match_dup 3)
- (compare:CC (match_dup 1)
- (const_int 0)))
- (set (match_dup 0)
- (if_then_else:GPR (lt (match_dup 3)
- (const_int 0))
- (match_dup 2)
- (match_dup 1)))]
- "")
-
-(define_insn_and_split "nabs<mode>2_isel"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (neg:GPR (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b"))))
- (clobber (match_scratch:GPR 2 "=&b"))
- (clobber (match_scratch:CC 3 "=y"))]
- "TARGET_ISEL"
- "#"
- "&& reload_completed"
- [(set (match_dup 2) (neg:GPR (match_dup 1)))
- (set (match_dup 3)
- (compare:CC (match_dup 1)
- (const_int 0)))
- (set (match_dup 0)
- (if_then_else:GPR (lt (match_dup 3)
- (const_int 0))
- (match_dup 1)
- (match_dup 2)))]
- "")
-
-(define_insn_and_split "abssi2_nopower"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
- (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
- (clobber (match_scratch:SI 2 "=&r,&r"))]
- "! TARGET_POWER && ! TARGET_ISEL"
- "#"
- "&& reload_completed"
- [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
- (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
- (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
- "")
-
-(define_insn "*nabs_power"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
- "TARGET_POWER"
- "nabs %0,%1")
-
-(define_insn_and_split "*nabs_nopower"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
- (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
- (clobber (match_scratch:SI 2 "=&r,&r"))]
- "! TARGET_POWER"
- "#"
- "&& reload_completed"
- [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
- (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
- (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
- "")
-
(define_expand "neg<mode>2"
[(set (match_operand:SDI 0 "gpc_reg_operand" "")
(neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
""
- "{cntlz|cntlz<wd>} %0,%1"
+ "cntlz<wd> %0,%1"
[(set_attr "type" "cntlz")])
(define_expand "ctz<mode>2"
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
UNSPEC_POPCNTB))]
"TARGET_POPCNTB"
- "popcntb %0,%1")
+ "popcntb %0,%1"
+ [(set_attr "length" "4")
+ (set_attr "type" "popcnt")])
(define_insn "popcntd<mode>2"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
"TARGET_POPCNTD"
- "popcnt<wd> %0,%1")
+ "popcnt<wd> %0,%1"
+ [(set_attr "length" "4")
+ (set_attr "type" "popcnt")])
(define_expand "popcount<mode>2"
[(set (match_operand:GPR 0 "gpc_reg_operand" "")
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI
(bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
- "TARGET_POWERPC"
+ ""
"lhbrx %0,%y1"
[(set_attr "length" "4")
(set_attr "type" "load")])
(bswap:HI
(match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
(clobber (match_scratch:SI 2 "=X,X,&r"))]
- "TARGET_POWERPC"
+ ""
"@
lhbrx %0,%y1
sthbrx %1,%y0
[(set (match_operand:HI 0 "gpc_reg_operand" "")
(bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
(clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
- "TARGET_POWERPC && reload_completed"
+ "reload_completed"
[(set (match_dup 3)
(zero_extract:SI (match_dup 4)
(const_int 8)
(match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
""
"@
- {lbrx|lwbrx} %0,%y1
- {stbrx|stwbrx} %1,%y0
+ lwbrx %0,%y1
+ stwbrx %1,%y0
#"
[(set_attr "length" "4,4,12")
(set_attr "type" "load,store,*")])
emit_insn (gen_bswapsi2 (dest_low, src_high));
}")
-(define_expand "mulsi3"
- [(use (match_operand:SI 0 "gpc_reg_operand" ""))
- (use (match_operand:SI 1 "gpc_reg_operand" ""))
- (use (match_operand:SI 2 "reg_or_short_operand" ""))]
- ""
- "
-{
- if (TARGET_POWER)
- emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
- else
- emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
- DONE;
-}")
-
-(define_insn "mulsi3_mq"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,I")))
- (clobber (match_scratch:SI 3 "=q,q"))]
- "TARGET_POWER"
- "@
- {muls|mullw} %0,%1,%2
- {muli|mulli} %0,%1,%2"
- [(set (attr "type")
- (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
- (const_string "imul3")
- (match_operand:SI 2 "short_cint_operand" "")
- (const_string "imul2")]
- (const_string "imul")))])
-
-(define_insn "mulsi3_no_mq"
+(define_insn "mulsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,I")))]
- "! TARGET_POWER"
+ ""
"@
- {muls|mullw} %0,%1,%2
- {muli|mulli} %0,%1,%2"
+ mullw %0,%1,%2
+ mulli %0,%1,%2"
[(set (attr "type")
(cond [(match_operand:SI 2 "s8bit_cint_operand" "")
(const_string "imul3")
(const_string "imul2")]
(const_string "imul")))])
-(define_insn "*mulsi3_mq_internal1"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))
- (clobber (match_scratch:SI 4 "=q,q"))]
- "TARGET_POWER"
- "@
- {muls.|mullw.} %3,%1,%2
- #"
- [(set_attr "type" "imul_compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 3)
- (mult:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))])
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*mulsi3_no_mq_internal1"
+(define_insn "*mulsi3_internal1"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
(match_operand:SI 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r"))]
- "! TARGET_POWER"
+ ""
"@
- {muls.|mullw.} %3,%1,%2
+ mullw. %3,%1,%2
#"
[(set_attr "type" "imul_compare")
(set_attr "length" "4,8")])
(match_operand:SI 2 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 3 ""))]
- "! TARGET_POWER && reload_completed"
+ "reload_completed"
[(set (match_dup 3)
(mult:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0)
(const_int 0)))]
"")
-(define_insn "*mulsi3_mq_internal2"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (mult:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 4 "=q,q"))]
- "TARGET_POWER"
- "@
- {muls.|mullw.} %0,%1,%2
- #"
- [(set_attr "type" "imul_compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (mult:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))])
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*mulsi3_no_mq_internal2"
+(define_insn "*mulsi3_internal2"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
(match_operand:SI 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(mult:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWER"
+ ""
"@
- {muls.|mullw.} %0,%1,%2
+ mullw. %0,%1,%2
#"
[(set_attr "type" "imul_compare")
(set_attr "length" "4,8")])
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(mult:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWER && reload_completed"
+ "reload_completed"
[(set (match_dup 0)
(mult:SI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
(const_int 0)))]
"")
-;; Operand 1 is divided by operand 2; quotient goes to operand
-;; 0 and remainder to operand 3.
-;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
-
-(define_expand "divmodsi4"
- [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" "")))
- (set (match_operand:SI 3 "register_operand" "")
- (mod:SI (match_dup 1) (match_dup 2)))])]
- "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
- "
-{
- if (! TARGET_POWER && ! TARGET_POWERPC)
- {
- emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
- emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
- emit_insn (gen_divss_call ());
- emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
- emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
- DONE;
- }
-}")
-
-(define_insn "*divmodsi4_internal"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (set (match_operand:SI 3 "register_operand" "=q")
- (mod:SI (match_dup 1) (match_dup 2)))]
- "TARGET_POWER"
- "divs %0,%1,%2"
- [(set_attr "type" "idiv")])
-
-(define_expand "udiv<mode>3"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
- (match_operand:GPR 2 "gpc_reg_operand" "")))]
- "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
- "
-{
- if (! TARGET_POWER && ! TARGET_POWERPC)
- {
- emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
- emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
- emit_insn (gen_quous_call ());
- emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
- DONE;
- }
- else if (TARGET_POWER)
- {
- emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
- DONE;
- }
-}")
-(define_insn "udivsi3_mq"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (clobber (match_scratch:SI 3 "=q"))]
- "TARGET_POWERPC && TARGET_POWER"
- "divwu %0,%1,%2"
- [(set_attr "type" "idiv")])
-
-(define_insn "*udivsi3_no_mq"
+(define_insn "udiv<mode>3"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "gpc_reg_operand" "r")))]
- "TARGET_POWERPC && ! TARGET_POWER"
+ ""
"div<wd>u %0,%1,%2"
[(set (attr "type")
(cond [(match_operand:SI 0 "" "")
;; For powers of two we can do srai/aze for divide and then adjust for
-;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
-;; used; for PowerPC, force operands into register and do a normal divide;
-;; for AIX common-mode, use quoss call on register operands.
+;; modulus. If it isn't a power of two, force operands into register and do
+;; a normal divide.
(define_expand "div<mode>3"
[(set (match_operand:GPR 0 "gpc_reg_operand" "")
(div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
(match_operand:GPR 2 "reg_or_cint_operand" "")))]
""
- "
{
- if (GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 0
- && exact_log2 (INTVAL (operands[2])) >= 0)
- ;
- else if (TARGET_POWERPC)
- {
- operands[2] = force_reg (<MODE>mode, operands[2]);
- if (TARGET_POWER)
- {
- emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
- DONE;
- }
- }
- else if (TARGET_POWER)
- FAIL;
- else
- {
- emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
- emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
- emit_insn (gen_quoss_call ());
- emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
- DONE;
- }
-}")
+ if (GET_CODE (operands[2]) != CONST_INT
+ || INTVAL (operands[2]) <= 0
+ || exact_log2 (INTVAL (operands[2])) < 0)
+ operands[2] = force_reg (<MODE>mode, operands[2]);
+})
-(define_insn "divsi3_mq"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (clobber (match_scratch:SI 3 "=q"))]
- "TARGET_POWERPC && TARGET_POWER"
- "divw %0,%1,%2"
- [(set_attr "type" "idiv")])
-
-(define_insn "*div<mode>3_no_mq"
+(define_insn "*div<mode>3"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "gpc_reg_operand" "r")))]
- "TARGET_POWERPC && ! TARGET_POWER"
+ ""
"div<wd> %0,%1,%2"
[(set (attr "type")
(cond [(match_operand:SI 0 "" "")
(div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
""
- "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
+ "sra<wd>i %0,%1,%p2\;addze %0,%0"
[(set_attr "type" "two")
(set_attr "length" "8")])
(clobber (match_scratch:P 3 "=r,r"))]
""
"@
- {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
+ sra<wd>i %3,%1,%p2\;addze. %3,%3
#"
[(set_attr "type" "compare")
(set_attr "length" "8,12")
(div:P (match_dup 1) (match_dup 2)))]
""
"@
- {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
+ sra<wd>i %0,%1,%p2\;addze. %0,%0
#"
[(set_attr "type" "compare")
(set_attr "length" "8,12")
(compare:CC (match_dup 0)
(const_int 0)))]
"")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (udiv:SI
- (plus:DI (ashift:DI
- (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
- (const_int 32))
- (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
- (match_operand:SI 3 "gpc_reg_operand" "r")))
- (set (match_operand:SI 2 "register_operand" "=*q")
- (umod:SI
- (plus:DI (ashift:DI
- (zero_extend:DI (match_dup 1)) (const_int 32))
- (zero_extend:DI (match_dup 4)))
- (match_dup 3)))]
- "TARGET_POWER"
- "div %0,%1,%3"
- [(set_attr "type" "idiv")])
-
-;; To do unsigned divide we handle the cases of the divisor looking like a
-;; negative number. If it is a constant that is less than 2**31, we don't
-;; have to worry about the branches. So make a few subroutines here.
-;;
-;; First comes the normal case.
-(define_expand "udivmodsi4_normal"
- [(set (match_dup 4) (const_int 0))
- (parallel [(set (match_operand:SI 0 "" "")
- (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
- (const_int 32))
- (zero_extend:DI (match_operand:SI 1 "" "")))
- (match_operand:SI 2 "" "")))
- (set (match_operand:SI 3 "" "")
- (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
- (const_int 32))
- (zero_extend:DI (match_dup 1)))
- (match_dup 2)))])]
- "TARGET_POWER"
- "
-{ operands[4] = gen_reg_rtx (SImode); }")
-
-;; This handles the branches.
-(define_expand "udivmodsi4_tests"
- [(set (match_operand:SI 0 "" "") (const_int 0))
- (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
- (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
- (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
- (label_ref (match_operand:SI 4 "" "")) (pc)))
- (set (match_dup 0) (const_int 1))
- (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
- (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
- (label_ref (match_dup 4)) (pc)))]
- "TARGET_POWER"
- "
-{ operands[5] = gen_reg_rtx (CCUNSmode);
- operands[6] = gen_reg_rtx (CCmode);
-}")
-
-(define_expand "udivmodsi4"
- [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" "")))
- (set (match_operand:SI 3 "gpc_reg_operand" "")
- (umod:SI (match_dup 1) (match_dup 2)))])]
- ""
- "
-{
- rtx label = 0;
-
- if (! TARGET_POWER)
- {
- if (! TARGET_POWERPC)
- {
- emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
- emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
- emit_insn (gen_divus_call ());
- emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
- emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
- DONE;
- }
- else
- FAIL;
- }
-
- if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
- {
- operands[2] = force_reg (SImode, operands[2]);
- label = gen_label_rtx ();
- emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
- operands[3], label));
- }
- else
- operands[2] = force_reg (SImode, operands[2]);
-
- emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
- operands[3]));
- if (label)
- emit_label (label);
-
- DONE;
-}")
-
-;; AIX architecture-independent common-mode multiply (DImode),
-;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
-;; R4; results in R3 and sometimes R4; link register always clobbered by bla
-;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
-;; assumed unused if generating common-mode, so ignore.
-(define_insn "mulh_call"
- [(set (reg:SI 3)
- (truncate:SI
- (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
- (sign_extend:DI (reg:SI 4)))
- (const_int 32))))
- (clobber (reg:SI LR_REGNO))]
- "! TARGET_POWER && ! TARGET_POWERPC"
- "bla __mulh"
- [(set_attr "type" "imul")])
-
-(define_insn "mull_call"
- [(set (reg:DI 3)
- (mult:DI (sign_extend:DI (reg:SI 3))
- (sign_extend:DI (reg:SI 4))))
- (clobber (reg:SI LR_REGNO))
- (clobber (reg:SI 0))]
- "! TARGET_POWER && ! TARGET_POWERPC"
- "bla __mull"
- [(set_attr "type" "imul")])
-
-(define_insn "divss_call"
- [(set (reg:SI 3)
- (div:SI (reg:SI 3) (reg:SI 4)))
- (set (reg:SI 4)
- (mod:SI (reg:SI 3) (reg:SI 4)))
- (clobber (reg:SI LR_REGNO))
- (clobber (reg:SI 0))]
- "! TARGET_POWER && ! TARGET_POWERPC"
- "bla __divss"
- [(set_attr "type" "idiv")])
-
-(define_insn "divus_call"
- [(set (reg:SI 3)
- (udiv:SI (reg:SI 3) (reg:SI 4)))
- (set (reg:SI 4)
- (umod:SI (reg:SI 3) (reg:SI 4)))
- (clobber (reg:SI LR_REGNO))
- (clobber (reg:SI 0))
- (clobber (match_scratch:CC 0 "=x"))
- (clobber (reg:CC CR1_REGNO))]
- "! TARGET_POWER && ! TARGET_POWERPC"
- "bla __divus"
- [(set_attr "type" "idiv")])
-
-(define_insn "quoss_call"
- [(set (reg:SI 3)
- (div:SI (reg:SI 3) (reg:SI 4)))
- (clobber (reg:SI LR_REGNO))]
- "! TARGET_POWER && ! TARGET_POWERPC"
- "bla __quoss"
- [(set_attr "type" "idiv")])
-
-(define_insn "quous_call"
- [(set (reg:SI 3)
- (udiv:SI (reg:SI 3) (reg:SI 4)))
- (clobber (reg:SI LR_REGNO))
- (clobber (reg:SI 0))
- (clobber (match_scratch:CC 0 "=x"))
- (clobber (reg:CC CR1_REGNO))]
- "! TARGET_POWER && ! TARGET_POWERPC"
- "bla __quous"
- [(set_attr "type" "idiv")])
\f
;; Logical instructions
;; The logical instructions are mostly combined by using match_operator,
"rs6000_gen_cell_microcode"
"@
and %0,%1,%2
- {rlinm|rlwinm} %0,%1,0,%m2,%M2
- {andil.|andi.} %0,%1,%b2
- {andiu.|andis.} %0,%1,%u2"
+ rlwinm %0,%1,0,%m2,%M2
+ andi. %0,%1,%b2
+ andis. %0,%1,%u2"
[(set_attr "type" "*,*,fast_compare,fast_compare")])
(define_insn "andsi3_nomc"
"!rs6000_gen_cell_microcode"
"@
and %0,%1,%2
- {rlinm|rlwinm} %0,%1,0,%m2,%M2")
+ rlwinm %0,%1,0,%m2,%M2")
(define_insn "andsi3_internal0_nomc"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
"!rs6000_gen_cell_microcode"
"@
and %0,%1,%2
- {rlinm|rlwinm} %0,%1,0,%m2,%M2")
+ rlwinm %0,%1,0,%m2,%M2")
;; Note to set cr's other than cr0 we do the and immediate and then
"TARGET_32BIT && rs6000_gen_cell_microcode"
"@
and. %3,%1,%2
- {andil.|andi.} %3,%1,%b2
- {andiu.|andis.} %3,%1,%u2
- {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
+ andi. %3,%1,%b2
+ andis. %3,%1,%u2
+ rlwinm. %3,%1,0,%m2,%M2
#
#
#
"TARGET_64BIT && rs6000_gen_cell_microcode"
"@
#
- {andil.|andi.} %3,%1,%b2
- {andiu.|andis.} %3,%1,%u2
- {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
+ andi. %3,%1,%b2
+ andis. %3,%1,%u2
+ rlwinm. %3,%1,0,%m2,%M2
#
#
#
"TARGET_32BIT && rs6000_gen_cell_microcode"
"@
and. %0,%1,%2
- {andil.|andi.} %0,%1,%b2
- {andiu.|andis.} %0,%1,%u2
- {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
+ andi. %0,%1,%b2
+ andis. %0,%1,%u2
+ rlwinm. %0,%1,0,%m2,%M2
#
#
#
"TARGET_64BIT && rs6000_gen_cell_microcode"
"@
#
- {andil.|andi.} %0,%1,%b2
- {andiu.|andis.} %0,%1,%u2
- {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
+ andi. %0,%1,%b2
+ andis. %0,%1,%u2
+ rlwinm. %0,%1,0,%m2,%M2
#
#
#
""
"@
%q3 %0,%1,%2
- {%q3il|%q3i} %0,%1,%b2
- {%q3iu|%q3is} %0,%1,%u2")
+ %q3i %0,%1,%b2
+ %q3is %0,%1,%u2")
(define_insn "*boolsi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC (match_dup 0)
(const_int 0)))]
"")
-
-;; maskir insn. We need four forms because things might be in arbitrary
-;; orders. Don't define forms that only set CR fields because these
-;; would modify an input register.
-
-(define_insn "*maskir_internal1"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
- (match_operand:SI 1 "gpc_reg_operand" "0"))
- (and:SI (match_dup 2)
- (match_operand:SI 3 "gpc_reg_operand" "r"))))]
- "TARGET_POWER"
- "maskir %0,%3,%2")
-
-(define_insn "*maskir_internal2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
- (match_operand:SI 1 "gpc_reg_operand" "0"))
- (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
- (match_dup 2))))]
- "TARGET_POWER"
- "maskir %0,%3,%2")
-
-(define_insn "*maskir_internal3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
- (match_operand:SI 3 "gpc_reg_operand" "r"))
- (and:SI (not:SI (match_dup 2))
- (match_operand:SI 1 "gpc_reg_operand" "0"))))]
- "TARGET_POWER"
- "maskir %0,%3,%2")
-
-(define_insn "*maskir_internal4"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
- (match_operand:SI 2 "gpc_reg_operand" "r"))
- (and:SI (not:SI (match_dup 2))
- (match_operand:SI 1 "gpc_reg_operand" "0"))))]
- "TARGET_POWER"
- "maskir %0,%3,%2")
-
-(define_insn "*maskir_internal5"
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (match_operand:SI 1 "gpc_reg_operand" "0,0"))
- (and:SI (match_dup 2)
- (match_operand:SI 3 "gpc_reg_operand" "r,r")))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
- (and:SI (match_dup 2) (match_dup 3))))]
- "TARGET_POWER"
- "@
- maskir. %0,%3,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
- (match_operand:SI 1 "gpc_reg_operand" ""))
- (and:SI (match_dup 2)
- (match_operand:SI 3 "gpc_reg_operand" "")))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
- (and:SI (match_dup 2) (match_dup 3))))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
- (and:SI (match_dup 2) (match_dup 3))))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*maskir_internal6"
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (match_operand:SI 1 "gpc_reg_operand" "0,0"))
- (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
- (match_dup 2)))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
- (and:SI (match_dup 3) (match_dup 2))))]
- "TARGET_POWER"
- "@
- maskir. %0,%3,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
- (match_operand:SI 1 "gpc_reg_operand" ""))
- (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
- (match_dup 2)))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
- (and:SI (match_dup 3) (match_dup 2))))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
- (and:SI (match_dup 3) (match_dup 2))))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*maskir_internal7"
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
- (match_operand:SI 3 "gpc_reg_operand" "r,r"))
- (and:SI (not:SI (match_dup 2))
- (match_operand:SI 1 "gpc_reg_operand" "0,0")))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ior:SI (and:SI (match_dup 2) (match_dup 3))
- (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
- "TARGET_POWER"
- "@
- maskir. %0,%3,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (and:SI (not:SI (match_dup 2))
- (match_operand:SI 1 "gpc_reg_operand" "")))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ior:SI (and:SI (match_dup 2) (match_dup 3))
- (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (ior:SI (and:SI (match_dup 2) (match_dup 3))
- (and:SI (not:SI (match_dup 2)) (match_dup 1))))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*maskir_internal8"
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (and:SI (not:SI (match_dup 2))
- (match_operand:SI 1 "gpc_reg_operand" "0,0")))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ior:SI (and:SI (match_dup 3) (match_dup 2))
- (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
- "TARGET_POWER"
- "@
- maskir. %0,%3,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (and:SI (not:SI (match_dup 2))
- (match_operand:SI 1 "gpc_reg_operand" "")))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ior:SI (and:SI (match_dup 3) (match_dup 2))
- (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (ior:SI (and:SI (match_dup 3) (match_dup 2))
- (and:SI (not:SI (match_dup 2)) (match_dup 1))))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
\f
;; Rotate and shift insns, in all their variants. These support shifts,
;; field inserts and extracts, and various combinations thereof.
FAIL;
if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
- emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
+ emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
+ operands[3]));
else
- emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
+ emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
+ operands[3]));
DONE;
}")
-(define_insn "insvsi"
+(define_insn "insvsi_internal"
[(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "const_int_operand" "i"))
operands[4] = GEN_INT (32 - start - size);
operands[1] = GEN_INT (start + size - 1);
- return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
+ return \"rlwimi %0,%3,%h4,%h2,%h1\";
}"
[(set_attr "type" "insert_word")])
operands[4] = GEN_INT (shift - start - size);
operands[1] = GEN_INT (start + size - 1);
- return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
+ return \"rlwimi %0,%3,%h4,%h2,%h1\";
}"
[(set_attr "type" "insert_word")])
operands[4] = GEN_INT (32 - shift - start - size);
operands[1] = GEN_INT (start + size - 1);
- return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
+ return \"rlwimi %0,%3,%h4,%h2,%h1\";
}"
[(set_attr "type" "insert_word")])
operands[4] = GEN_INT (32 - shift - start - size);
operands[1] = GEN_INT (start + size - 1);
- return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
+ return \"rlwimi %0,%3,%h4,%h2,%h1\";
}"
[(set_attr "type" "insert_word")])
/* Align extract field with insert field */
operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
operands[1] = GEN_INT (insert_start + insert_size - 1);
- return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
+ return \"rlwimi %0,%3,%h5,%h2,%h1\";
}"
[(set_attr "type" "insert_word")])
(and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 5 "mask_operand" "i"))))]
- "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
+ "INTVAL(operands[1]) == ~INTVAL(operands[5])"
"*
{
int me = extract_ME(operands[5]);
operands[4] = GEN_INT(32 - INTVAL(operands[2]));
operands[2] = GEN_INT(mb);
operands[1] = GEN_INT(me);
- return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
+ return \"rlwimi %0,%3,%h4,%h2,%h1\";
}"
[(set_attr "type" "insert_word")])
(match_operand:SI 5 "mask_operand" "i"))
(and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
(match_operand:SI 1 "mask_operand" "i"))))]
- "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
+ "INTVAL(operands[1]) == ~INTVAL(operands[5])"
"*
{
int me = extract_ME(operands[5]);
operands[4] = GEN_INT(32 - INTVAL(operands[2]));
operands[2] = GEN_INT(mb);
operands[1] = GEN_INT(me);
- return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
+ return \"rlwimi %0,%3,%h4,%h2,%h1\";
}"
[(set_attr "type" "insert_word")])
-(define_insn "insvdi"
+(define_insn "insvdi_internal"
[(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "const_int_operand" "i"))
FAIL;
if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
- emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
+ emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
+ operands[3]));
else
- emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
+ emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
+ operands[3]));
DONE;
}")
-(define_insn "extzvsi"
+(define_insn "extzvsi_internal"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")
operands[3] = const0_rtx;
else
operands[3] = GEN_INT (start + size);
- return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
+ return \"rlwinm %0,%1,%3,%s2,31\";
}")
(define_insn "*extzvsi_internal1"
operands[3] = GEN_INT (((1 << (16 - (start & 15)))
- (1 << (16 - (start & 15) - size))));
if (start < 16)
- return \"{andiu.|andis.} %4,%1,%3\";
+ return \"andis. %4,%1,%3\";
else
- return \"{andil.|andi.} %4,%1,%3\";
+ return \"andi. %4,%1,%3\";
}
if (start + size >= 32)
operands[3] = const0_rtx;
else
operands[3] = GEN_INT (start + size);
- return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
+ return \"rlwinm. %4,%1,%3,%s2,31\";
}"
[(set_attr "type" "delayed_compare")
(set_attr "length" "4,8")])
if (start >= 16 && start + size == 32)
{
operands[3] = GEN_INT ((1 << size) - 1);
- return \"{andil.|andi.} %0,%1,%3\";
+ return \"andi. %0,%1,%3\";
}
if (start + size >= 32)
operands[3] = const0_rtx;
else
operands[3] = GEN_INT (start + size);
- return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
+ return \"rlwinm. %0,%1,%3,%s2,31\";
}"
[(set_attr "type" "delayed_compare")
(set_attr "length" "4,8")])
(const_int 0)))]
"")
-(define_insn "extzvdi"
+(define_insn "extzvdi_internal"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")
(match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
""
"@
- {rlnm|rlwnm} %0,%1,%2,0xffffffff
- {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
+ rlwnm %0,%1,%2,0xffffffff
+ rlwinm %0,%1,%h2,0xffffffff"
[(set_attr "type" "var_shift_rotate,integer")])
(define_insn "*rotlsi3_64"
(match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
"TARGET_64BIT"
"@
- {rlnm|rlwnm} %0,%1,%2,0xffffffff
- {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
+ rlwnm %0,%1,%2,0xffffffff
+ rlwinm %0,%1,%h2,0xffffffff"
[(set_attr "type" "var_shift_rotate,integer")])
(define_insn "*rotlsi3_internal2"
(clobber (match_scratch:SI 3 "=r,r,r,r"))]
""
"@
- {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
- {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
+ rlwnm. %3,%1,%2,0xffffffff
+ rlwinm. %3,%1,%h2,0xffffffff
#
#"
[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
(rotate:SI (match_dup 1) (match_dup 2)))]
""
"@
- {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
- {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
+ rlwnm. %0,%1,%2,0xffffffff
+ rlwinm. %0,%1,%h2,0xffffffff
#
#"
[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
(match_operand:SI 3 "mask_operand" "n,n")))]
""
"@
- {rlnm|rlwnm} %0,%1,%2,%m3,%M3
- {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
+ rlwnm %0,%1,%2,%m3,%M3
+ rlwinm %0,%1,%h2,%m3,%M3"
[(set_attr "type" "var_shift_rotate,integer")])
(define_insn "*rotlsi3_internal5"
(clobber (match_scratch:SI 4 "=r,r,r,r"))]
""
"@
- {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
- {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
+ rlwnm. %4,%1,%2,%m3,%M3
+ rlwinm. %4,%1,%h2,%m3,%M3
#
#"
[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
""
"@
- {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
- {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
+ rlwnm. %0,%1,%2,%m3,%M3
+ rlwinm. %0,%1,%h2,%m3,%M3
#
#"
[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
""
- "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
+ "rlw%I2nm %0,%1,%h2,0xff"
[(set (attr "cell_micro")
(if_then_else (match_operand:SI 2 "const_int_operand" "")
(const_string "not")
(clobber (match_scratch:SI 3 "=r,r,r,r"))]
""
"@
- {rlnm.|rlwnm.} %3,%1,%2,0xff
- {rlinm.|rlwinm.} %3,%1,%h2,0xff
+ rlwnm. %3,%1,%2,0xff
+ rlwinm. %3,%1,%h2,0xff
#
#"
[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
(zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
""
"@
- {rlnm.|rlwnm.} %0,%1,%2,0xff
- {rlinm.|rlwinm.} %0,%1,%h2,0xff
+ rlwnm. %0,%1,%2,0xff
+ rlwinm. %0,%1,%h2,0xff
#
#"
[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
(match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
""
"@
- {rlnm|rlwnm} %0,%1,%2,0xffff
- {rlinm|rlwinm} %0,%1,%h2,0xffff"
+ rlwnm %0,%1,%2,0xffff
+ rlwinm %0,%1,%h2,0xffff"
[(set_attr "type" "var_shift_rotate,integer")])
(clobber (match_scratch:SI 3 "=r,r,r,r"))]
""
"@
- {rlnm.|rlwnm.} %3,%1,%2,0xffff
- {rlinm.|rlwinm.} %3,%1,%h2,0xffff
+ rlwnm. %3,%1,%2,0xffff
+ rlwinm. %3,%1,%h2,0xffff
#
#"
[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
(zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
""
"@
- {rlnm.|rlwnm.} %0,%1,%2,0xffff
- {rlinm.|rlwinm.} %0,%1,%h2,0xffff
+ rlwnm. %0,%1,%2,0xffff
+ rlwinm. %0,%1,%h2,0xffff
#
#"
[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
(const_int 0)))]
"")
-;; Note that we use "sle." instead of "sl." so that we can set
-;; SHIFT_COUNT_TRUNCATED.
-
-(define_expand "ashlsi3"
- [(use (match_operand:SI 0 "gpc_reg_operand" ""))
- (use (match_operand:SI 1 "gpc_reg_operand" ""))
- (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
- ""
- "
-{
- if (TARGET_POWER)
- emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
- else
- emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
- DONE;
-}")
-
-(define_insn "ashlsi3_power"
+(define_insn "ashlsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
- (clobber (match_scratch:SI 3 "=q,X"))]
- "TARGET_POWER"
+ (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
+ ""
"@
- sle %0,%1,%2
- {sli|slwi} %0,%1,%h2")
-
-(define_insn "ashlsi3_no_power"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
- "! TARGET_POWER"
- "@
- {sl|slw} %0,%1,%2
- {sli|slwi} %0,%1,%h2"
- [(set_attr "type" "var_shift_rotate,shift")])
+ slw %0,%1,%2
+ slwi %0,%1,%h2"
+ [(set_attr "type" "var_shift_rotate,shift")])
(define_insn "*ashlsi3_64"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
"TARGET_POWERPC64"
"@
- {sl|slw} %0,%1,%2
- {sli|slwi} %0,%1,%h2"
+ slw %0,%1,%2
+ slwi %0,%1,%h2"
[(set_attr "type" "var_shift_rotate,shift")])
(define_insn ""
(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
(const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r,r,r"))
- (clobber (match_scratch:SI 4 "=q,X,q,X"))]
- "TARGET_POWER"
- "@
- sle. %3,%1,%2
- {sli.|slwi.} %3,%1,%h2
- #
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 3)
- (ashift:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))])
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
- (const_int 0)))
(clobber (match_scratch:SI 3 "=r,r,r,r"))]
- "! TARGET_POWER && TARGET_32BIT"
+ "TARGET_32BIT"
"@
- {sl.|slw.} %3,%1,%2
- {sli.|slwi.} %3,%1,%h2
+ slw. %3,%1,%2
+ slwi. %3,%1,%h2
#
#"
[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
(match_operand:SI 2 "reg_or_cint_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 3 ""))]
- "! TARGET_POWER && TARGET_32BIT && reload_completed"
+ "TARGET_32BIT && reload_completed"
[(set (match_dup 3)
(ashift:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0)
(match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
- (ashift:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 4 "=q,X,q,X"))]
- "TARGET_POWER"
- "@
- sle. %0,%1,%2
- {sli.|slwi.} %0,%1,%h2
- #
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ashift:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 0)
- (ashift:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))])
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
(ashift:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWER && TARGET_32BIT"
+ "TARGET_32BIT"
"@
- {sl.|slw.} %0,%1,%2
- {sli.|slwi.} %0,%1,%h2
+ slw. %0,%1,%2
+ slwi. %0,%1,%h2
#
#"
[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(ashift:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWER && TARGET_32BIT && reload_completed"
+ "TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(ashift:SI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 3 "mask_operand" "n")))]
"includes_lshift_p (operands[2], operands[3])"
- "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
+ "rlwinm %0,%1,%h2,%m3,%M3")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(clobber (match_scratch:SI 4 "=r,r"))]
"includes_lshift_p (operands[2], operands[3])"
"@
- {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
+ rlwinm. %4,%1,%h2,%m3,%M3
#"
[(set_attr "type" "delayed_compare")
(set_attr "length" "4,8")])
(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"includes_lshift_p (operands[2], operands[3])"
"@
- {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
+ rlwinm. %0,%1,%h2,%m3,%M3
#"
[(set_attr "type" "delayed_compare")
(set_attr "length" "4,8")])
(const_int 0)))]
"")
-;; The AIX assembler mis-handles "sri x,x,0", so write that case as
-;; "sli x,x,0".
-(define_expand "lshrsi3"
- [(use (match_operand:SI 0 "gpc_reg_operand" ""))
- (use (match_operand:SI 1 "gpc_reg_operand" ""))
- (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
- ""
- "
-{
- if (TARGET_POWER)
- emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
- else
- emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
- DONE;
-}")
-
-(define_insn "lshrsi3_power"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
- (clobber (match_scratch:SI 3 "=q,X,X"))]
- "TARGET_POWER"
- "@
- sre %0,%1,%2
- mr %0,%1
- {s%A2i|s%A2wi} %0,%1,%h2")
-
-(define_insn "lshrsi3_no_power"
+(define_insn "lshrsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
- "! TARGET_POWER"
+ ""
"@
mr %0,%1
- {sr|srw} %0,%1,%2
- {sri|srwi} %0,%1,%h2"
+ srw %0,%1,%2
+ srwi %0,%1,%h2"
[(set_attr "type" "integer,var_shift_rotate,shift")])
(define_insn "*lshrsi3_64"
(match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
"TARGET_POWERPC64"
"@
- {sr|srw} %0,%1,%2
- {sri|srwi} %0,%1,%h2"
+ srw %0,%1,%2
+ srwi %0,%1,%h2"
[(set_attr "type" "var_shift_rotate,shift")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
- (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
- "TARGET_POWER"
- "@
- sre. %3,%1,%2
- mr. %1,%1
- {s%A2i.|s%A2wi.} %3,%1,%h2
- #
- #
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,4,4,8,8,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 3)
- (lshiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))])
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
- (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
- "! TARGET_POWER && TARGET_32BIT"
+ "TARGET_32BIT"
"@
mr. %1,%1
- {sr.|srw.} %3,%1,%2
- {sri.|srwi.} %3,%1,%h2
+ srw. %3,%1,%2
+ srwi. %3,%1,%h2
#
#
#"
(match_operand:SI 2 "reg_or_cint_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 3 ""))]
- "! TARGET_POWER && TARGET_32BIT && reload_completed"
+ "TARGET_32BIT && reload_completed"
[(set (match_dup 3)
(lshiftrt:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0)
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
- (lshiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
- "TARGET_POWER"
- "@
- sre. %0,%1,%2
- mr. %0,%1
- {s%A2i.|s%A2wi.} %0,%1,%h2
- #
- #
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,4,4,8,8,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (lshiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 0)
- (lshiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))])
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
- (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWER && TARGET_32BIT"
+ "TARGET_32BIT"
"@
mr. %0,%1
- {sr.|srw.} %0,%1,%2
- {sri.|srwi.} %0,%1,%h2
+ srw. %0,%1,%2
+ srwi. %0,%1,%h2
#
#
#"
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWER && TARGET_32BIT && reload_completed"
+ "TARGET_32BIT && reload_completed"
[(set (match_dup 0)
(lshiftrt:SI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 3 "mask_operand" "n")))]
"includes_rshift_p (operands[2], operands[3])"
- "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
+ "rlwinm %0,%1,%s2,%m3,%M3")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(clobber (match_scratch:SI 4 "=r,r"))]
"includes_rshift_p (operands[2], operands[3])"
"@
- {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
+ rlwinm. %4,%1,%s2,%m3,%M3
#"
[(set_attr "type" "delayed_compare")
(set_attr "length" "4,8")])
(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"includes_rshift_p (operands[2], operands[3])"
"@
- {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
+ rlwinm. %0,%1,%s2,%m3,%M3
#"
[(set_attr "type" "delayed_compare")
(set_attr "length" "4,8")])
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 0)))]
"includes_rshift_p (operands[2], GEN_INT (255))"
- "{rlinm|rlwinm} %0,%1,%s2,0xff")
+ "rlwinm %0,%1,%s2,0xff")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(clobber (match_scratch:SI 3 "=r,r"))]
"includes_rshift_p (operands[2], GEN_INT (255))"
"@
- {rlinm.|rlwinm.} %3,%1,%s2,0xff
+ rlwinm. %3,%1,%s2,0xff
#"
[(set_attr "type" "delayed_compare")
(set_attr "length" "4,8")])
(zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
"includes_rshift_p (operands[2], GEN_INT (255))"
"@
- {rlinm.|rlwinm.} %0,%1,%s2,0xff
+ rlwinm. %0,%1,%s2,0xff
#"
[(set_attr "type" "delayed_compare")
(set_attr "length" "4,8")])
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 0)))]
"includes_rshift_p (operands[2], GEN_INT (65535))"
- "{rlinm|rlwinm} %0,%1,%s2,0xffff")
+ "rlwinm %0,%1,%s2,0xffff")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(clobber (match_scratch:SI 3 "=r,r"))]
"includes_rshift_p (operands[2], GEN_INT (65535))"
"@
- {rlinm.|rlwinm.} %3,%1,%s2,0xffff
+ rlwinm. %3,%1,%s2,0xffff
#"
[(set_attr "type" "delayed_compare")
(set_attr "length" "4,8")])
(zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
"includes_rshift_p (operands[2], GEN_INT (65535))"
"@
- {rlinm.|rlwinm.} %0,%1,%s2,0xffff
+ rlwinm. %0,%1,%s2,0xffff
#"
[(set_attr "type" "delayed_compare")
(set_attr "length" "4,8")])
(const_int 0)))]
"")
-(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
- (const_int 1)
- (match_operand:SI 1 "gpc_reg_operand" "r"))
- (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 31)))]
- "TARGET_POWER"
- "rrib %0,%1,%2")
-
-(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
- (const_int 1)
- (match_operand:SI 1 "gpc_reg_operand" "r"))
- (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 31)))]
- "TARGET_POWER"
- "rrib %0,%1,%2")
-
-(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
- (const_int 1)
- (match_operand:SI 1 "gpc_reg_operand" "r"))
- (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 1)
- (const_int 0)))]
- "TARGET_POWER"
- "rrib %0,%1,%2")
-
-(define_expand "ashrsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" "")))]
- ""
- "
-{
- if (TARGET_POWER)
- emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
- else
- emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
- DONE;
-}")
-
-(define_insn "ashrsi3_power"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
- (clobber (match_scratch:SI 3 "=q,X"))]
- "TARGET_POWER"
- "@
- srea %0,%1,%2
- {srai|srawi} %0,%1,%h2"
- [(set_attr "type" "shift")])
-
-(define_insn "ashrsi3_no_power"
+(define_insn "ashrsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
- "! TARGET_POWER"
+ ""
"@
- {sra|sraw} %0,%1,%2
- {srai|srawi} %0,%1,%h2"
+ sraw %0,%1,%2
+ srawi %0,%1,%h2"
[(set_attr "type" "var_shift_rotate,shift")])
(define_insn "*ashrsi3_64"
(match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
"TARGET_POWERPC64"
"@
- {sra|sraw} %0,%1,%2
- {srai|srawi} %0,%1,%h2"
+ sraw %0,%1,%2
+ srawi %0,%1,%h2"
[(set_attr "type" "var_shift_rotate,shift")])
(define_insn ""
(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
(const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r,r,r"))
- (clobber (match_scratch:SI 4 "=q,X,q,X"))]
- "TARGET_POWER"
- "@
- srea. %3,%1,%2
- {srai.|srawi.} %3,%1,%h2
- #
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 3)
- (ashiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))])
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
- (const_int 0)))
(clobber (match_scratch:SI 3 "=r,r,r,r"))]
- "! TARGET_POWER"
+ ""
"@
- {sra.|sraw.} %3,%1,%2
- {srai.|srawi.} %3,%1,%h2
+ sraw. %3,%1,%2
+ srawi. %3,%1,%h2
#
#"
[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
(match_operand:SI 2 "reg_or_cint_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 3 ""))]
- "! TARGET_POWER && reload_completed"
+ "reload_completed"
[(set (match_dup 3)
(ashiftrt:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0)
(match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
- (ashiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 4 "=q,X,q,X"))]
- "TARGET_POWER"
- "@
- srea. %0,%1,%2
- {srai.|srawi.} %0,%1,%h2
- #
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ashiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 0)
- (ashiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))])
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWER"
+ ""
"@
- {sra.|sraw.} %0,%1,%2
- {srai.|srawi.} %0,%1,%h2
+ sraw. %0,%1,%2
+ srawi. %0,%1,%h2
#
#"
[(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWER && reload_completed"
+ "reload_completed"
[(set (match_dup 0)
(ashiftrt:SI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
"frsp %0,%1"
[(set_attr "type" "fp")])
-(define_insn "aux_truncdfsf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
- (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
- "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
- "frsp %0,%1"
- [(set_attr "type" "fp")])
-
(define_expand "negsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
- "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
"fadds %0,%1,%2"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_addsub_s")])
-(define_insn ""
- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
- (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
- (match_operand:SF 2 "gpc_reg_operand" "f")))]
- "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
- "{fa|fadd} %0,%1,%2"
- [(set_attr "type" "fp")])
-
(define_expand "subsf3"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
- "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
"fsubs %0,%1,%2"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_addsub_s")])
-(define_insn ""
- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
- (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
- (match_operand:SF 2 "gpc_reg_operand" "f")))]
- "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
- "{fs|fsub} %0,%1,%2"
- [(set_attr "type" "fp")])
-
(define_expand "mulsf3"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
- "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
"fmuls %0,%1,%2"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_mul_s")])
-(define_insn ""
- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
- (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
- (match_operand:SF 2 "gpc_reg_operand" "f")))]
- "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
- "{fm|fmul} %0,%1,%2"
- [(set_attr "type" "dmul")])
-
(define_expand "divsf3"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(div:SF (match_operand:SF 1 "gpc_reg_operand" "")
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
- "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
+ "TARGET_HARD_FLOAT && TARGET_FPRS
&& TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
"fdivs %0,%1,%2"
[(set_attr "type" "sdiv")])
-(define_insn ""
- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
- (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
- (match_operand:SF 2 "gpc_reg_operand" "f")))]
- "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
- && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
- "{fd|fdiv} %0,%1,%2"
- [(set_attr "type" "ddiv")])
-
(define_insn "fres"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
(match_operand:SF 2 "gpc_reg_operand" "f")
(match_operand:SF 3 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
-{
- return (TARGET_POWERPC
- ? "fmadds %0,%1,%2,%3"
- : "{fma|fmadd} %0,%1,%2,%3");
-}
+ "fmadds %0,%1,%2,%3"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_maddsub_s")])
(match_operand:SF 2 "gpc_reg_operand" "f")
(neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
-{
- return (TARGET_POWERPC
- ? "fmsubs %0,%1,%2,%3"
- : "{fms|fmsub} %0,%1,%2,%3");
-}
+ "fmsubs %0,%1,%2,%3"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_maddsub_s")])
(match_operand:SF 2 "gpc_reg_operand" "f")
(match_operand:SF 3 "gpc_reg_operand" "f"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
-{
- return (TARGET_POWERPC
- ? "fnmadds %0,%1,%2,%3"
- : "{fnma|fnmadd} %0,%1,%2,%3");
-}
+ "fnmadds %0,%1,%2,%3"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_maddsub_s")])
(match_operand:SF 2 "gpc_reg_operand" "f")
(neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
-{
- return (TARGET_POWERPC
- ? "fnmsubs %0,%1,%2,%3"
- : "{fnms|fnmsub} %0,%1,%2,%3");
-}
+ "fnmsubs %0,%1,%2,%3"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_maddsub_s")])
(define_expand "sqrtsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
- "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
+ "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU)
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
&& !TARGET_SIMPLE_FPU"
"")
"fsqrts %0,%1"
[(set_attr "type" "ssqrt")])
-(define_insn ""
- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
- (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
- "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
- && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
- "fsqrt %0,%1"
- [(set_attr "type" "dsqrt")])
-
(define_insn "*rsqrtsf_internal1"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
(match_operand:DF 2 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& !VECTOR_UNIT_VSX_P (DFmode)"
- "{fa|fadd} %0,%1,%2"
+ "fadd %0,%1,%2"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_addsub_d")])
(match_operand:DF 2 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& !VECTOR_UNIT_VSX_P (DFmode)"
- "{fs|fsub} %0,%1,%2"
+ "fsub %0,%1,%2"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_addsub_d")])
(match_operand:DF 2 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& !VECTOR_UNIT_VSX_P (DFmode)"
- "{fm|fmul} %0,%1,%2"
+ "fmul %0,%1,%2"
[(set_attr "type" "dmul")
(set_attr "fp_type" "fp_mul_d")])
(match_operand:DF 2 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
&& !VECTOR_UNIT_VSX_P (DFmode)"
- "{fd|fdiv} %0,%1,%2"
+ "fdiv %0,%1,%2"
[(set_attr "type" "ddiv")])
(define_insn "*fred_fpr"
(match_operand:DF 3 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& VECTOR_UNIT_NONE_P (DFmode)"
- "{fma|fmadd} %0,%1,%2,%3"
+ "fmadd %0,%1,%2,%3"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_maddsub_d")])
(neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& VECTOR_UNIT_NONE_P (DFmode)"
- "{fms|fmsub} %0,%1,%2,%3"
+ "fmsub %0,%1,%2,%3"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_maddsub_d")])
(match_operand:DF 3 "gpc_reg_operand" "f"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& VECTOR_UNIT_NONE_P (DFmode)"
- "{fnma|fnmadd} %0,%1,%2,%3"
+ "fnmadd %0,%1,%2,%3"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_maddsub_d")])
(neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& VECTOR_UNIT_NONE_P (DFmode)"
- "{fnms|fnmsub} %0,%1,%2,%3"
+ "fnmsub %0,%1,%2,%3"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_maddsub_d")])
(define_expand "sqrtdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
- "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
- && TARGET_DOUBLE_FLOAT"
+ "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"")
(define_insn "*sqrtdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
- "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
- && TARGET_DOUBLE_FLOAT
+ "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& !VECTOR_UNIT_VSX_P (DFmode)"
"fsqrt %0,%1"
[(set_attr "type" "dsqrt")])
(define_expand "fix_trunc<mode>si2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
- "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT
- && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
+ "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
"
{
if (!<E500_CONVERT>)
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
(clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
(clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
- "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
- && TARGET_DOUBLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"#"
""
[(pc)]
[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
(unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
UNSPEC_FCTIWZ))]
- "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
- && TARGET_DOUBLE_FLOAT"
- "{fcirz|fctiwz} %0,%1"
+ "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
+ "fctiwz %0,%1"
[(set_attr "type" "fp")])
(define_insn "fctiwuz_<mode>"
{
if (WORDS_BIG_ENDIAN)
return (GET_CODE (operands[2])) != CONST_INT
- ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
- : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
+ ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
+ : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
else
return (GET_CODE (operands[2])) != CONST_INT
- ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
- : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
+ ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
+ : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
}"
[(set_attr "type" "two")
(set_attr "length" "8")])
{
if (WORDS_BIG_ENDIAN)
return (GET_CODE (operands[1]) != CONST_INT)
- ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
- : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
+ ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
+ : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
else
return (GET_CODE (operands[1]) != CONST_INT)
- ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
- : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
+ ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
+ : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
}"
[(set_attr "type" "two")
(set_attr "length" "8")])
"*
{
return (WORDS_BIG_ENDIAN)
- ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
- : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
+ ? \"subfic %L0,%L1,0\;subfze %0,%1\"
+ : \"subfic %0,%1,0\;subfze %L0,%L1\";
}"
[(set_attr "type" "two")
(set_attr "length" "8")])
-(define_expand "mulsidi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
- (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
- "! TARGET_POWERPC64"
- "
-{
- if (! TARGET_POWER && ! TARGET_POWERPC)
- {
- emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
- emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
- emit_insn (gen_mull_call ());
- if (WORDS_BIG_ENDIAN)
- emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
- else
- {
- emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
- gen_rtx_REG (SImode, 3));
- emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
- gen_rtx_REG (SImode, 4));
- }
- DONE;
- }
- else if (TARGET_POWER)
- {
- emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
- DONE;
- }
-}")
-
-(define_insn "mulsidi3_mq"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
- (clobber (match_scratch:SI 3 "=q"))]
- "TARGET_POWER"
- "mul %0,%1,%2\;mfmq %L0"
- [(set_attr "type" "imul")
- (set_attr "length" "8")])
-
-(define_insn "*mulsidi3_no_mq"
+(define_insn "mulsidi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
(sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
- "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
- "*
+ "! TARGET_POWERPC64"
{
return (WORDS_BIG_ENDIAN)
? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
: \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
-}"
+}
[(set_attr "type" "imul")
(set_attr "length" "8")])
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
(sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
- "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
+ "! TARGET_POWERPC64 && reload_completed"
[(set (match_dup 3)
(truncate:SI
(lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
}")
-(define_expand "umulsidi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
- (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
- "TARGET_POWERPC && ! TARGET_POWERPC64"
- "
-{
- if (TARGET_POWER)
- {
- emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
- DONE;
- }
-}")
-
-(define_insn "umulsidi3_mq"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
- (clobber (match_scratch:SI 3 "=q"))]
- "TARGET_POWERPC && TARGET_POWER"
- "*
-{
- return (WORDS_BIG_ENDIAN)
- ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
- : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
-}"
- [(set_attr "type" "imul")
- (set_attr "length" "8")])
-
-(define_insn "*umulsidi3_no_mq"
+(define_insn "umulsidi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
(zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
- "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
+ "! TARGET_POWERPC64"
"*
{
return (WORDS_BIG_ENDIAN)
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
(zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
- "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
+ "! TARGET_POWERPC64 && reload_completed"
[(set (match_dup 3)
(truncate:SI
(lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
}")
-(define_expand "smulsi3_highpart"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (truncate:SI
- (lshiftrt:DI (mult:DI (sign_extend:DI
- (match_operand:SI 1 "gpc_reg_operand" ""))
- (sign_extend:DI
- (match_operand:SI 2 "gpc_reg_operand" "")))
- (const_int 32))))]
- ""
- "
-{
- if (! TARGET_POWER && ! TARGET_POWERPC)
- {
- emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
- emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
- emit_insn (gen_mulh_call ());
- emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
- DONE;
- }
- else if (TARGET_POWER)
- {
- emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
- DONE;
- }
-}")
-
-(define_insn "smulsi3_highpart_mq"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (truncate:SI
- (lshiftrt:DI (mult:DI (sign_extend:DI
- (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (sign_extend:DI
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 "=q"))]
- "TARGET_POWER"
- "mul %0,%1,%2"
- [(set_attr "type" "imul")])
-
-(define_insn "*smulsi3_highpart_no_mq"
+(define_insn "smulsi3_highpart"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(truncate:SI
(lshiftrt:DI (mult:DI (sign_extend:DI
(sign_extend:DI
(match_operand:SI 2 "gpc_reg_operand" "r")))
(const_int 32))))]
- "TARGET_POWERPC && ! TARGET_POWER"
+ ""
"mulhw %0,%1,%2"
[(set_attr "type" "imul")])
-(define_expand "umulsi3_highpart"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (truncate:SI
- (lshiftrt:DI (mult:DI (zero_extend:DI
- (match_operand:SI 1 "gpc_reg_operand" ""))
- (zero_extend:DI
- (match_operand:SI 2 "gpc_reg_operand" "")))
- (const_int 32))))]
- "TARGET_POWERPC"
- "
-{
- if (TARGET_POWER)
- {
- emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
- DONE;
- }
-}")
-
-(define_insn "umulsi3_highpart_mq"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (truncate:SI
- (lshiftrt:DI (mult:DI (zero_extend:DI
- (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (zero_extend:DI
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 "=q"))]
- "TARGET_POWERPC && TARGET_POWER"
- "mulhwu %0,%1,%2"
- [(set_attr "type" "imul")])
-
-(define_insn "*umulsi3_highpart_no_mq"
+(define_insn "umulsi3_highpart"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(truncate:SI
(lshiftrt:DI (mult:DI (zero_extend:DI
(zero_extend:DI
(match_operand:SI 2 "gpc_reg_operand" "r")))
(const_int 32))))]
- "TARGET_POWERPC && ! TARGET_POWER"
+ ""
"mulhwu %0,%1,%2"
[(set_attr "type" "imul")])
-;; If operands 0 and 2 are in the same register, we have a problem. But
-;; operands 0 and 1 (the usual case) can be in the same register. That's
-;; why we have the strange constraints below.
-(define_insn "ashldi3_power"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
- (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
- (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
- (clobber (match_scratch:SI 3 "=X,q,q,q"))]
- "TARGET_POWER"
- "@
- {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
- sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
- sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
- sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
- [(set_attr "length" "8")])
-
-(define_insn "lshrdi3_power"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
- (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
- (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
- (clobber (match_scratch:SI 3 "=X,q,q,q"))]
- "TARGET_POWER"
- "@
- {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
- sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
- sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
- sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
- [(set_attr "length" "8")])
-
;; Shift by a variable amount is too complex to be worth open-coding. We
;; just handle shifts by constants.
-(define_insn "ashrdi3_power"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
- (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "const_int_operand" "M,i")))
- (clobber (match_scratch:SI 3 "=X,q"))]
- "TARGET_POWER"
- "@
- {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
- sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
- [(set_attr "type" "shift")
- (set_attr "length" "8")])
-
(define_insn "ashrdi3_no_power"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "const_int_operand" "M,i")))]
- "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
+ "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
"@
- {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
- {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
+ srawi %0,%1,31\;srawi %L0,%1,%h2
+ srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2"
[(set_attr "type" "two,three")
(set_attr "length" "8,12")])
\f
;; PowerPC64 DImode operations.
-(define_expand "absdi2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
- "TARGET_POWERPC64"
- "
-{
- if (TARGET_ISEL)
- emit_insn (gen_absdi2_isel (operands[0], operands[1]));
- else
- emit_insn (gen_absdi2_internal (operands[0], operands[1]));
- DONE;
-}")
-
-(define_insn_and_split "absdi2_internal"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
- (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
- (clobber (match_scratch:DI 2 "=&r,&r"))]
- "TARGET_POWERPC64 && !TARGET_ISEL"
- "#"
- "&& reload_completed"
- [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
- (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
- (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
- "")
-
-(define_insn_and_split "*nabsdi2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
- (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
- (clobber (match_scratch:DI 2 "=&r,&r"))]
- "TARGET_POWERPC64 && !TARGET_ISEL"
- "#"
- "&& reload_completed"
- [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
- (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
- (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
- "")
-
(define_insn "muldi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
"mulhdu %0,%1,%2"
[(set_attr "type" "lmul")])
+(define_expand "mulditi3"
+ [(set (match_operand:TI 0 "gpc_reg_operand")
+ (mult:TI (sign_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
+ (sign_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
+ "TARGET_POWERPC64"
+{
+ rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
+ emit_insn (gen_muldi3 (l, operands[1], operands[2]));
+ emit_insn (gen_smuldi3_highpart (h, operands[1], operands[2]));
+ emit_move_insn (gen_lowpart (DImode, operands[0]), l);
+ emit_move_insn (gen_highpart (DImode, operands[0]), h);
+ DONE;
+})
+
+(define_expand "umulditi3"
+ [(set (match_operand:TI 0 "gpc_reg_operand")
+ (mult:TI (zero_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
+ (zero_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
+ "TARGET_POWERPC64"
+{
+ rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
+ emit_insn (gen_muldi3 (l, operands[1], operands[2]));
+ emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2]));
+ emit_move_insn (gen_lowpart (DImode, operands[0]), l);
+ emit_move_insn (gen_highpart (DImode, operands[0]), h);
+ DONE;
+})
+
(define_insn "rotldi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_cint_operand" "")))]
- "TARGET_POWERPC64 || TARGET_POWER"
- "
-{
- if (TARGET_POWERPC64)
- ;
- else if (TARGET_POWER)
- {
- emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
- DONE;
- }
- else
- FAIL;
-}")
+ "TARGET_POWERPC64"
+ "")
(define_insn "*ashldi3_internal1"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_cint_operand" "")))]
- "TARGET_POWERPC64 || TARGET_POWER"
- "
-{
- if (TARGET_POWERPC64)
- ;
- else if (TARGET_POWER)
- {
- emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
- DONE;
- }
- else
- FAIL;
-}")
+ "TARGET_POWERPC64"
+ "")
(define_insn "*lshrdi3_internal1"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
{
if (TARGET_POWERPC64)
;
- else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
- {
- emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
- DONE;
- }
else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
&& WORDS_BIG_ENDIAN)
{
(compare:CC (match_dup 0)
(const_int 0)))]
"")
-
-(define_expand "smindi3"
- [(match_operand:DI 0 "gpc_reg_operand" "")
- (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "gpc_reg_operand" "")]
- "TARGET_ISEL64"
- "
-{
- rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
- DONE;
-}")
-
-(define_expand "smaxdi3"
- [(match_operand:DI 0 "gpc_reg_operand" "")
- (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "gpc_reg_operand" "")]
- "TARGET_ISEL64"
- "
-{
- rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
- DONE;
-}")
-
-(define_expand "umindi3"
- [(match_operand:DI 0 "gpc_reg_operand" "")
- (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "gpc_reg_operand" "")]
- "TARGET_ISEL64"
- "
-{
- rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
- DONE;
-}")
-
-(define_expand "umaxdi3"
- [(match_operand:DI 0 "gpc_reg_operand" "")
- (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "gpc_reg_operand" "")]
- "TARGET_ISEL64"
- "
-{
- rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
- DONE;
-}")
-
\f
;; Now define ways of moving data around.
(match_operand:SI 2 "gpc_reg_operand" "b")]
UNSPEC_MOVSI_GOT))]
"DEFAULT_ABI == ABI_V4 && flag_pic == 1"
- "{l|lwz} %0,%a1@got(%2)"
+ "lwz %0,%a1@got(%2)"
[(set_attr "type" "load")])
;; Used by sched, shorten_branches and final when the GOT pseudo reg
(mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && ! TARGET_64BIT"
- "{l|lwz} %0,lo16(%2)(%1)"
+ "lwz %0,lo16(%2)(%1)"
[(set_attr "type" "load")
(set_attr "length" "4")])
(define_insn "*movsi_internal1"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
- (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
+ [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
+ (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
"!TARGET_SINGLE_FPU &&
(gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
"@
mr %0,%1
- {cal|la} %0,%a1
- {l%U1%X1|lwz%U1%X1} %0,%1
- {st%U0%X0|stw%U0%X0} %1,%0
- {lil|li} %0,%1
- {liu|lis} %0,%v1
+ la %0,%a1
+ lwz%U1%X1 %0,%1
+ stw%U0%X0 %1,%0
+ li %0,%1
+ lis %0,%v1
#
- {cal|la} %0,%a1
mf%1 %0
mt%0 %1
mt%0 %1
- mt%0 %1
- {cror 0,0,0|nop}"
- [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
- (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
+ nop"
+ [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
+ (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
(define_insn "*movsi_internal1_single"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
- (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
+ [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
+ (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
"TARGET_SINGLE_FPU &&
(gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
"@
mr %0,%1
- {cal|la} %0,%a1
- {l%U1%X1|lwz%U1%X1} %0,%1
- {st%U0%X0|stw%U0%X0} %1,%0
- {lil|li} %0,%1
- {liu|lis} %0,%v1
+ la %0,%a1
+ lwz%U1%X1 %0,%1
+ stw%U0%X0 %1,%0
+ li %0,%1
+ lis %0,%v1
#
- {cal|la} %0,%a1
mf%1 %0
mt%0 %1
mt%0 %1
- mt%0 %1
- {cror 0,0,0|nop}
- stfs%U0%X0 %1, %0
- lfs%U1%X1 %0, %1"
- [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
- (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
+ nop
+ stfs%U0%X0 %1,%0
+ lfs%U1%X1 %0,%1"
+ [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,*,*")
+ (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
;; Split a load of a large constant into the appropriate two-insn
;; sequence.
(set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
""
"@
- {cmpi|cmp<wd>i} %2,%0,0
+ cmp<wd>i %2,%0,0
mr. %0,%1
#"
[(set_attr "type" "cmp,compare,cmp")
"")
\f
(define_insn "*movhi_internal"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
- (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
+ (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
"gpc_reg_operand (operands[0], HImode)
|| gpc_reg_operand (operands[1], HImode)"
"@
mr %0,%1
lhz%U1%X1 %0,%1
sth%U0%X0 %1,%0
- {lil|li} %0,%w1
+ li %0,%w1
mf%1 %0
mt%0 %1
- mt%0 %1
- {cror 0,0,0|nop}"
- [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
+ nop"
+ [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
(define_expand "mov<mode>"
[(set (match_operand:INT 0 "general_operand" "")
"{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
(define_insn "*movqi_internal"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
- (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
+ (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
"gpc_reg_operand (operands[0], QImode)
|| gpc_reg_operand (operands[1], QImode)"
"@
mr %0,%1
lbz%U1%X1 %0,%1
stb%U0%X0 %1,%0
- {lil|li} %0,%1
+ li %0,%1
mf%1 %0
mt%0 %1
- mt%0 %1
- {cror 0,0,0|nop}"
- [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
+ nop"
+ [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
\f
;; Here is how to move condition codes around. When we store CC data in
;; an integer register or memory, we store just the high-order 4 bits.
"")
(define_insn "*movcc_internal1"
- [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
- (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
+ [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
+ (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
"register_operand (operands[0], CCmode)
|| register_operand (operands[1], CCmode)"
"@
mcrf %0,%1
mtcrf 128,%1
- {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
+ rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
crxor %0,%0,%0
mfcr %0%Q1
- mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
+ mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
mr %0,%1
- {lil|li} %0,%1
+ li %0,%1
mf%1 %0
mt%0 %1
- mt%0 %1
- {l%U1%X1|lwz%U1%X1} %0,%1
- {st%U0%U1|stw%U0%U1} %1,%0"
+ lwz%U1%X1 %0,%1
+ stw%U0%U1 %1,%0"
[(set (attr "type")
(cond [(eq_attr "alternative" "0,3")
(const_string "cr_logical")
(eq_attr "alternative" "1,2")
(const_string "mtcr")
- (eq_attr "alternative" "6,7,9")
+ (eq_attr "alternative" "6,7")
(const_string "integer")
(eq_attr "alternative" "8")
(const_string "mfjmpr")
- (eq_attr "alternative" "10")
+ (eq_attr "alternative" "9")
(const_string "mtjmpr")
- (eq_attr "alternative" "11")
+ (eq_attr "alternative" "10")
(const_string "load")
- (eq_attr "alternative" "12")
+ (eq_attr "alternative" "11")
(const_string "store")
(match_test "TARGET_MFCRF")
(const_string "mfcrf")
]
(const_string "mfcr")))
- (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
+ (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
\f
;; For floating-point, we normally deal with the floating-point registers
;; unless -msoft-float is used. The sole exception is that parameter passing
}")
(define_insn "*movsf_hardfloat"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
- (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,!r,*h,!r,!r")
+ (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,h,0,G,Fn"))]
"(gpc_reg_operand (operands[0], SFmode)
|| gpc_reg_operand (operands[1], SFmode))
&& (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
"@
mr %0,%1
- {l%U1%X1|lwz%U1%X1} %0,%1
- {st%U0%X0|stw%U0%X0} %1,%0
+ lwz%U1%X1 %0,%1
+ stw%U0%X0 %1,%0
fmr %0,%1
lfs%U1%X1 %0,%1
stfs%U0%X0 %1,%0
mt%0 %1
- mt%0 %1
mf%1 %0
- {cror 0,0,0|nop}
+ nop
#
#"
- [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
+ [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*")
+ (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
(define_insn "*movsf_softfloat"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
- (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
+ (match_operand:SF 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
"(gpc_reg_operand (operands[0], SFmode)
|| gpc_reg_operand (operands[1], SFmode))
&& (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
"@
mr %0,%1
mt%0 %1
- mt%0 %1
mf%1 %0
- {l%U1%X1|lwz%U1%X1} %0,%1
- {st%U0%X0|stw%U0%X0} %1,%0
- {lil|li} %0,%1
- {liu|lis} %0,%v1
- {cal|la} %0,%a1
+ lwz%U1%X1 %0,%1
+ stw%U0%X0 %1,%0
+ li %0,%1
+ lis %0,%v1
#
#
- {cror 0,0,0|nop}"
- [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
+ nop"
+ [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
+ (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
\f
(define_expand "movdf"
#endif
}")
-;; Don't have reload use general registers to load a constant. First,
-;; it might not work if the output operand is the equivalent of
-;; a non-offsettable memref, but also it is less efficient than loading
-;; the constant into an FP register, since it will probably be used there.
-;; The "??" is a kludge until we can figure out a more reasonable way
-;; of handling these non-offsettable values.
+;; Don't have reload use general registers to load a constant. It is
+;; less efficient than loading the constant into an FP register, since
+;; it will probably be used there.
;; The move constraints are ordered to prefer floating point registers before
;; general purpose registers to avoid doing a store and a load to get the value
;; reloading.
(define_insn "*movdf_hardfloat32"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=m,d,d,ws,?wa,Z,?Z,ws,?wa,wa,Y,??r,!r,!r,!r,!r")
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=m,d,d,ws,?wa,Z,?Z,ws,?wa,wa,Y,r,!r,!r,!r,!r")
(match_operand:DF 1 "input_operand" "d,m,d,Z,Z,ws,wa,ws,wa,j,r,Y,r,G,H,F"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], DFmode)
(set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,8,8,8,12,16")])
(define_insn "*movdf_softfloat32"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
- (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
+ (match_operand:DF 1 "input_operand" "r,Y,r,G,H,F"))]
"! TARGET_POWERPC64
&& ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
|| TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
&& (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))"
"#"
- [(set_attr "type" "two,load,store,*,*,*")
+ [(set_attr "type" "store,load,two,*,*,*")
(set_attr "length" "8,8,8,8,12,16")])
;; Reload patterns to support gpr load/store with misaligned mem.
-(define_expand "reload_di_store"
+;; and multiple gpr load/store at offset >= 0xfffc
+(define_expand "reload_<mode>_store"
[(parallel [(match_operand 0 "memory_operand" "=m")
(match_operand 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "register_operand" "=&b")])]
- "TARGET_POWERPC64"
+ (match_operand:GPR 2 "register_operand" "=&b")])]
+ ""
{
- rs6000_secondary_reload_ppc64 (operands[1], operands[0], operands[2], true);
+ rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
DONE;
})
-(define_expand "reload_di_load"
+(define_expand "reload_<mode>_load"
[(parallel [(match_operand 0 "gpc_reg_operand" "=r")
(match_operand 1 "memory_operand" "m")
- (match_operand:DI 2 "register_operand" "=b")])]
- "TARGET_POWERPC64"
+ (match_operand:GPR 2 "register_operand" "=b")])]
+ ""
{
- rs6000_secondary_reload_ppc64 (operands[0], operands[1], operands[2], false);
+ rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
DONE;
})
; ld/std require word-aligned displacements -> 'Y' constraint.
; List Y->r and r->Y before r->r for reload.
(define_insn "*movdf_hardfloat64_mfpgpr"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r,r,d")
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,*c*l,!r,*h,!r,!r,!r,r,d")
(match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
"TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
lxsd%U1x %x0,%y1
stxsd%U0x %x1,%y0
stxsd%U0x %x1,%y0
- fmr %0,%1
- lfd%U1%X1 %0,%1
stfd%U0%X0 %1,%0
+ lfd%U1%X1 %0,%1
+ fmr %0,%1
xxlxor %x0,%x0,%x0
mt%0 %1
mf%1 %0
- {cror 0,0,0|nop}
+ nop
#
#
#
mftgpr %0,%1
mffgpr %0,%1"
- [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
+ [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
(set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
; ld/std require word-aligned displacements -> 'Y' constraint.
; List Y->r and r->Y before r->r for reload.
(define_insn "*movdf_hardfloat64"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=m,d,d,Y,??r,!r,ws,?wa,Z,?Z,ws,?wa,wa,*c*l,!r,*h,!r,!r,!r")
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=m,d,d,Y,r,!r,ws,?wa,Z,?Z,ws,?wa,wa,*c*l,!r,*h,!r,!r,!r")
(match_operand:DF 1 "input_operand" "d,m,d,r,Y,r,Z,Z,ws,wa,ws,wa,j,r,h,0,G,H,F"))]
"TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
(set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
(define_insn "*movdf_softfloat64"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
- (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
+ (match_operand:DF 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
"TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
&& (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))"
"@
- ld%U1%X1 %0,%1
std%U0%X0 %1,%0
+ ld%U1%X1 %0,%1
mr %0,%1
mt%0 %1
mf%1 %0
#
#
#
- {cror 0,0,0|nop}"
- [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
+ nop"
+ [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
(set_attr "length" "4,4,4,4,4,8,12,16,4")])
\f
(define_expand "movtf"
"!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
"{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
-; It's important to list the o->f and f->o moves before f->f because
-; otherwise reload, given m->f, will try to pick f->f and reload it,
-; which doesn't make progress. Likewise r->Y must be before r->r.
+;; It's important to list Y->r and r->Y before r->r because otherwise
+;; reload, given m->r, will try to pick r->r and reload it, which
+;; doesn't make progress.
(define_insn_and_split "*movtf_internal"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
- (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
+ (match_operand:TF 1 "input_operand" "d,m,d,r,YGHF,r"))]
"!TARGET_IEEEQUAD
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
&& (gpc_reg_operand (operands[0], TFmode)
[(set_attr "length" "8,8,8,20,20,16")])
(define_insn_and_split "*movtf_softfloat"
- [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
- (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
+ [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=Y,r,r")
+ (match_operand:TF 1 "input_operand" "r,YGHF,r"))]
"!TARGET_IEEEQUAD
&& (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
&& (gpc_reg_operand (operands[0], TFmode)
})
(define_insn_and_split "*extenddftf2_internal"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
- (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
- (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
+ (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
+ (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
"!TARGET_IEEEQUAD
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& TARGET_LONG_DOUBLE_128"
(define_expand "fix_trunctfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
- "!TARGET_IEEEQUAD
- && (TARGET_POWER2 || TARGET_POWERPC)
- && TARGET_HARD_FLOAT
- && (TARGET_FPRS || TARGET_E500_DOUBLE)
- && TARGET_LONG_DOUBLE_128"
+ "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
+ && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
{
if (TARGET_E500_DOUBLE)
emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
(clobber (match_dup 4))
(clobber (match_dup 5))])]
"!TARGET_IEEEQUAD
- && (TARGET_POWER2 || TARGET_POWERPC)
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
{
operands[2] = gen_reg_rtx (DFmode);
operands[3] = gen_reg_rtx (DFmode);
operands[4] = gen_reg_rtx (DImode);
- operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
+ operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
})
(define_insn_and_split "*fix_trunctfsi2_internal"
;; Next come the multi-word integer load and store and the load and store
;; multiple insns.
-; List r->r after r->"o<>", otherwise reload will try to reload a
-; non-offsettable address by using r->r which won't make progress.
+;; List r->r after r->Y, otherwise reload will try to reload a
+;; non-offsettable address by using r->r which won't make progress.
+;; Use of fprs is disparaged slightly otherwise reload prefers to reload
+;; a gpr into a fpr instead of reloading an invalid 'Y' address
(define_insn "*movdi_internal32"
- [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r,?wa")
- (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF,O"))]
+ [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r,?wa")
+ (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF,O"))]
"! TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"
#
#
#
- fmr %0,%1
- lfd%U1%X1 %0,%1
stfd%U0%X0 %1,%0
+ lfd%U1%X1 %0,%1
+ fmr %0,%1
#
xxlxor %x0,%x0,%x0"
- [(set_attr "type" "load,*,store,fp,fpload,fpstore,*,vecsimple")])
+ [(set_attr "type" "store,load,*,fpstore,fpload,fp,*,vecsimple")])
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
(define_insn "*movdi_mfpgpr"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
- (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*d")
+ (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*d,r"))]
"TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"
"@
- mr %0,%1
- ld%U1%X1 %0,%1
std%U0%X0 %1,%0
+ ld%U1%X1 %0,%1
+ mr %0,%1
li %0,%1
lis %0,%v1
#
- la %0,%a1
- fmr %0,%1
- lfd%U1%X1 %0,%1
stfd%U0%X0 %1,%0
+ lfd%U1%X1 %0,%1
+ fmr %0,%1
mf%1 %0
mt%0 %1
- {cror 0,0,0|nop}
+ nop
mftgpr %0,%1
mffgpr %0,%1"
- [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
- (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
+ [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
+ (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")])
(define_insn "*movdi_internal64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,?wa")
- (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,O"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,?wa")
+ (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,O"))]
"TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"
"@
- mr %0,%1
- ld%U1%X1 %0,%1
std%U0%X0 %1,%0
+ ld%U1%X1 %0,%1
+ mr %0,%1
li %0,%1
lis %0,%v1
#
- la %0,%a1
- fmr %0,%1
- lfd%U1%X1 %0,%1
stfd%U0%X0 %1,%0
+ lfd%U1%X1 %0,%1
+ fmr %0,%1
mf%1 %0
mt%0 %1
- {cror 0,0,0|nop}
+ nop
xxlxor %x0,%x0,%x0"
- [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,vecsimple")
- (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")])
+ [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,vecsimple")
+ (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
;; immediate value valid for a single instruction hiding in a const_double
(define_insn ""
}")
\f
;; TImode is similar, except that we usually want to compute the address into
-;; a register and use lsi/stsi (the exception is during reload). MQ is also
-;; clobbered in stsi for POWER, so we need a SCRATCH for it.
-
-;; We say that MQ is clobbered in the last alternative because the first
-;; alternative would never get used otherwise since it would need a reload
-;; while the 2nd alternative would not. We put memory cases first so they
-;; are preferred. Otherwise, we'd try to reload the output instead of
-;; giving the SCRATCH mq.
-
-(define_insn "*movti_power"
- [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
- (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
- (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
- "TARGET_POWER && ! TARGET_POWERPC64
+;; a register and use lsi/stsi (the exception is during reload).
+
+(define_insn "*movti_string"
+ [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
+ (match_operand:TI 1 "input_operand" "r,r,Q,Y,r,n"))]
+ "! TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
"*
{
{
default:
gcc_unreachable ();
-
case 0:
if (TARGET_STRING)
- return \"{stsi|stswi} %1,%P0,16\";
+ return \"stswi %1,%P0,16\";
case 1:
- case 2:
return \"#\";
- case 3:
+ case 2:
/* If the address is not used in the output, we can use lsi. Otherwise,
fall through to generating four loads. */
if (TARGET_STRING
- && ! reg_overlap_mentioned_p (operands[0], operands[1]))
- return \"{lsi|lswi} %0,%P1,16\";
+ && ! reg_overlap_mentioned_p (operands[0], operands[1]))
+ return \"lswi %0,%P1,16\";
/* ... fall through ... */
+ case 3:
case 4:
case 5:
return \"#\";
}
}"
- [(set_attr "type" "store,store,*,load,load,*")])
-
-(define_insn "*movti_string"
- [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
- (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
- "! TARGET_POWER && ! TARGET_POWERPC64
- && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
- "*
-{
- switch (which_alternative)
- {
- default:
- gcc_unreachable ();
- case 0:
- if (TARGET_STRING)
- return \"{stsi|stswi} %1,%P0,16\";
- case 1:
- case 2:
- return \"#\";
- case 3:
- /* If the address is not used in the output, we can use lsi. Otherwise,
- fall through to generating four loads. */
- if (TARGET_STRING
- && ! reg_overlap_mentioned_p (operands[0], operands[1]))
- return \"{lsi|lswi} %0,%P1,16\";
- /* ... fall through ... */
- case 4:
- case 5:
- return \"#\";
- }
-}"
- [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
+ [(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*")
(set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
(const_string "always")
(const_string "conditional")))])
(define_insn "*movti_ppc64"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
- (match_operand:TI 1 "input_operand" "r,r,m"))]
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=Y,r,r")
+ (match_operand:TI 1 "input_operand" "r,Y,r"))]
"(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
|| gpc_reg_operand (operands[1], TImode)))
&& VECTOR_MEM_NONE_P (TImode)"
"#"
- [(set_attr "type" "*,store,load")])
+ [(set_attr "type" "store,load,*")])
(define_split
[(set (match_operand:TI 0 "gpc_reg_operand" "")
(match_operand:SI 9 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
(match_operand:SI 10 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
- "{stsi|stswi} %2,%1,%O0"
+ "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
+ "stswi %2,%1,%O0"
[(set_attr "type" "store_ux")
(set_attr "cell_micro" "always")])
(match_operand:SI 8 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
(match_operand:SI 9 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
- "{stsi|stswi} %2,%1,%O0"
+ "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
+ "stswi %2,%1,%O0"
[(set_attr "type" "store_ux")
(set_attr "cell_micro" "always")])
(match_operand:SI 7 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
(match_operand:SI 8 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
- "{stsi|stswi} %2,%1,%O0"
+ "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
+ "stswi %2,%1,%O0"
[(set_attr "type" "store_ux")
(set_attr "cell_micro" "always")])
(match_operand:SI 6 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
(match_operand:SI 7 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
- "{stsi|stswi} %2,%1,%O0"
+ "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
+ "stswi %2,%1,%O0"
[(set_attr "type" "store_ux")
(set_attr "cell_micro" "always")])
(match_operand:SI 5 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
(match_operand:SI 6 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
- "{stsi|stswi} %2,%1,%O0"
+ "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
+ "stswi %2,%1,%O0"
[(set_attr "type" "store_ux")
(set_attr "cell_micro" "always")])
(match_operand:SI 4 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
(match_operand:SI 5 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
- "{stsi|stswi} %2,%1,%O0"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")])
-
-(define_insn "*stmsi8_power"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
- (match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "=q"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
- (match_operand:SI 4 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
- (match_operand:SI 5 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
- (match_operand:SI 6 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
- (match_operand:SI 7 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
- (match_operand:SI 8 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
- (match_operand:SI 9 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
- (match_operand:SI 10 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
- "{stsi|stswi} %2,%1,%O0"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")])
-
-(define_insn "*stmsi7_power"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
- (match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "=q"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
- (match_operand:SI 4 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
- (match_operand:SI 5 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
- (match_operand:SI 6 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
- (match_operand:SI 7 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
- (match_operand:SI 8 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
- (match_operand:SI 9 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
- "{stsi|stswi} %2,%1,%O0"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")])
-
-(define_insn "*stmsi6_power"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
- (match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "=q"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
- (match_operand:SI 4 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
- (match_operand:SI 5 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
- (match_operand:SI 6 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
- (match_operand:SI 7 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
- (match_operand:SI 8 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
- "{stsi|stswi} %2,%1,%O0"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")])
-
-(define_insn "*stmsi5_power"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
- (match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "=q"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
- (match_operand:SI 4 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
- (match_operand:SI 5 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
- (match_operand:SI 6 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
- (match_operand:SI 7 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
- "{stsi|stswi} %2,%1,%O0"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")])
-
-(define_insn "*stmsi4_power"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
- (match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "=q"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
- (match_operand:SI 4 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
- (match_operand:SI 5 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
- (match_operand:SI 6 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
- "{stsi|stswi} %2,%1,%O0"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")])
-
-(define_insn "*stmsi3_power"
- [(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
- (match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "=q"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
- (match_operand:SI 4 "gpc_reg_operand" "r"))
- (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
- (match_operand:SI 5 "gpc_reg_operand" "r"))])]
- "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
- "{stsi|stswi} %2,%1,%O0"
+ "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
+ "stswi %2,%1,%O0"
[(set_attr "type" "store_ux")
(set_attr "cell_micro" "always")])
\f
"")
(define_insn ""
- [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
- (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
- (use (match_operand:SI 2 "immediate_operand" "i"))
- (use (match_operand:SI 3 "immediate_operand" "i"))
- (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
- (clobber (reg:SI 6))
- (clobber (reg:SI 7))
- (clobber (reg:SI 8))
- (clobber (reg:SI 9))
- (clobber (reg:SI 10))
- (clobber (reg:SI 11))
- (clobber (reg:SI 12))
- (clobber (match_scratch:SI 5 "=q"))]
- "TARGET_STRING && TARGET_POWER
- && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
- || INTVAL (operands[2]) == 0)
- && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
- && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
- && REGNO (operands[4]) == 5"
- "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")
- (set_attr "length" "8")])
-
-(define_insn ""
[(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
(mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
(use (match_operand:SI 2 "immediate_operand" "i"))
(clobber (reg:SI 11))
(clobber (reg:SI 12))
(clobber (match_scratch:SI 5 "=X"))]
- "TARGET_STRING && ! TARGET_POWER
+ "TARGET_STRING
&& ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
|| INTVAL (operands[2]) == 0)
&& (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
&& REGNO (operands[4]) == 5"
- "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+ "lswi %4,%1,%2\;stswi %4,%0,%2"
[(set_attr "type" "store_ux")
(set_attr "cell_micro" "always")
(set_attr "length" "8")])
"")
(define_insn ""
- [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
- (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
- (use (match_operand:SI 2 "immediate_operand" "i"))
- (use (match_operand:SI 3 "immediate_operand" "i"))
- (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
- (clobber (reg:SI 6))
- (clobber (reg:SI 7))
- (clobber (reg:SI 8))
- (clobber (reg:SI 9))
- (clobber (reg:SI 10))
- (clobber (match_scratch:SI 5 "=q"))]
- "TARGET_STRING && TARGET_POWER
- && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
- && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
- && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
- && REGNO (operands[4]) == 5"
- "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")
- (set_attr "length" "8")])
-
-(define_insn ""
[(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
(mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
(use (match_operand:SI 2 "immediate_operand" "i"))
(clobber (reg:SI 9))
(clobber (reg:SI 10))
(clobber (match_scratch:SI 5 "=X"))]
- "TARGET_STRING && ! TARGET_POWER
+ "TARGET_STRING
&& INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
&& (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
&& REGNO (operands[4]) == 5"
- "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+ "lswi %4,%1,%2\;stswi %4,%0,%2"
[(set_attr "type" "store_ux")
(set_attr "cell_micro" "always")
(set_attr "length" "8")])
"")
(define_insn ""
- [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
- (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
- (use (match_operand:SI 2 "immediate_operand" "i"))
- (use (match_operand:SI 3 "immediate_operand" "i"))
- (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
- (clobber (reg:SI 6))
- (clobber (reg:SI 7))
- (clobber (reg:SI 8))
- (clobber (match_scratch:SI 5 "=q"))]
- "TARGET_STRING && TARGET_POWER
- && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
- && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
- && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
- && REGNO (operands[4]) == 5"
- "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")
- (set_attr "length" "8")])
-
-(define_insn ""
[(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
(mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
(use (match_operand:SI 2 "immediate_operand" "i"))
(clobber (reg:SI 7))
(clobber (reg:SI 8))
(clobber (match_scratch:SI 5 "=X"))]
- "TARGET_STRING && ! TARGET_POWER
+ "TARGET_STRING
&& INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
&& (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
&& REGNO (operands[4]) == 5"
- "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+ "lswi %4,%1,%2\;stswi %4,%0,%2"
[(set_attr "type" "store_ux")
(set_attr "cell_micro" "always")
(set_attr "length" "8")])
(use (match_operand:SI 2 "immediate_operand" "i"))
(use (match_operand:SI 3 "immediate_operand" "i"))
(clobber (match_scratch:DI 4 "=&r"))
- (clobber (match_scratch:SI 5 "=q"))]
- "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
- && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
- "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")
- (set_attr "length" "8")])
-
-(define_insn ""
- [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
- (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
- (use (match_operand:SI 2 "immediate_operand" "i"))
- (use (match_operand:SI 3 "immediate_operand" "i"))
- (clobber (match_scratch:DI 4 "=&r"))
(clobber (match_scratch:SI 5 "=X"))]
- "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
+ "TARGET_STRING && ! TARGET_POWERPC64
&& INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
- "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+ "lswi %4,%1,%2\;stswi %4,%0,%2"
[(set_attr "type" "store_ux")
(set_attr "cell_micro" "always")
(set_attr "length" "8")])
"")
(define_insn ""
- [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
- (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
- (use (match_operand:SI 2 "immediate_operand" "i"))
- (use (match_operand:SI 3 "immediate_operand" "i"))
- (clobber (match_scratch:SI 4 "=&r"))
- (clobber (match_scratch:SI 5 "=q"))]
- "TARGET_STRING && TARGET_POWER
- && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
- "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
- [(set_attr "type" "store_ux")
- (set_attr "cell_micro" "always")
- (set_attr "length" "8")])
-
-(define_insn ""
[(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
(mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
(use (match_operand:SI 2 "immediate_operand" "i"))
(use (match_operand:SI 3 "immediate_operand" "i"))
(clobber (match_scratch:SI 4 "=&r"))
(clobber (match_scratch:SI 5 "=X"))]
- "TARGET_STRING && ! TARGET_POWER
- && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
- "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+ "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
+ "lswi %4,%1,%2\;stswi %4,%0,%2"
[(set_attr "type" "store_ux")
(set_attr "cell_micro" "always")
(set_attr "length" "8")])
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
- {lux|lwzux} %3,%0,%2
- {lu|lwzu} %3,%2(%0)"
+ lwzux %3,%0,%2
+ lwzu %3,%2(%0)"
[(set_attr "type" "load_ux,load_u")])
(define_insn "*movsi_update2"
|| (REG_P (operands[0])
&& REGNO (operands[0]) == STACK_POINTER_REGNUM))"
"@
- {stux|stwux} %3,%0,%2
- {stu|stwu} %3,%2(%0)"
+ stwux %3,%0,%2
+ stwu %3,%2(%0)"
[(set_attr "type" "store_ux,store_u")])
;; This is an unconditional pattern; needed for stack allocation, even
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
- {stux|stwux} %3,%0,%2
- {stu|stwu} %3,%2(%0)"
+ stwux %3,%0,%2
+ stwu %3,%2(%0)"
[(set_attr "type" "store_ux,store_u")])
(define_insn "*movhi_update1"
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
- {lux|lwzux} %3,%0,%2
- {lu|lwzu} %3,%2(%0)"
+ lwzux %3,%0,%2
+ lwzu %3,%2(%0)"
[(set_attr "type" "load_ux,load_u")])
(define_insn "*movsf_update4"
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
- {stux|stwux} %3,%0,%2
- {stu|stwu} %3,%2(%0)"
+ stwux %3,%0,%2
+ stwu %3,%2(%0)"
[(set_attr "type" "store_ux,store_u")])
(define_insn "*movdf_update1"
stfdu %3,%2(%0)"
[(set_attr "type" "fpstore_ux,fpstore_u")])
-;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
-
-(define_insn "*lfq_power2"
- [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
- (match_operand:V2DF 1 "memory_operand" ""))]
- "TARGET_POWER2
- && TARGET_HARD_FLOAT && TARGET_FPRS"
- "lfq%U1%X1 %0,%1")
-
-(define_peephole2
- [(set (match_operand:DF 0 "gpc_reg_operand" "")
- (match_operand:DF 1 "memory_operand" ""))
- (set (match_operand:DF 2 "gpc_reg_operand" "")
- (match_operand:DF 3 "memory_operand" ""))]
- "TARGET_POWER2
- && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
- && registers_ok_for_quad_peep (operands[0], operands[2])
- && mems_ok_for_quad_peep (operands[1], operands[3])"
- [(set (match_dup 0)
- (match_dup 1))]
- "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
- operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
-
-(define_insn "*stfq_power2"
- [(set (match_operand:V2DF 0 "memory_operand" "")
- (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
- "TARGET_POWER2
- && TARGET_HARD_FLOAT && TARGET_FPRS"
- "stfq%U0%X0 %1,%0")
-
-
-(define_peephole2
- [(set (match_operand:DF 0 "memory_operand" "")
- (match_operand:DF 1 "gpc_reg_operand" ""))
- (set (match_operand:DF 2 "memory_operand" "")
- (match_operand:DF 3 "gpc_reg_operand" ""))]
- "TARGET_POWER2
- && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
- && registers_ok_for_quad_peep (operands[1], operands[3])
- && mems_ok_for_quad_peep (operands[0], operands[2])"
- [(set (match_dup 0)
- (match_dup 1))]
- "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
- operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
;; After inserting conditional returns we can sometimes have
;; unnecessary register moves. Unfortunately we cannot have a
"HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
{
if (TARGET_CMODEL != CMODEL_SMALL)
- return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;bl %z3\;%.";
+ return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
+ "bl %z3\;nop";
else
- return "addi %0,%1,%2@got@tlsgd\;bl %z3\;%.";
+ return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
}
"&& TARGET_TLS_MARKERS"
[(set (match_dup 0)
"addi %0,%1,%2@got@tlsgd"
"&& TARGET_CMODEL != CMODEL_SMALL"
[(set (match_dup 3)
- (const:TLSmode
- (plus:TLSmode (match_dup 1)
- (high:TLSmode
- (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))))
+ (high:TLSmode
+ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
(set (match_dup 0)
(lo_sum:TLSmode (match_dup 3)
(unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]
(define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
- (const:TLSmode
- (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
- (high:TLSmode
- (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
- UNSPEC_TLSGD)))))]
+ (high:TLSmode
+ (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
+ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
+ UNSPEC_TLSGD)))]
"HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
"addis %0,%1,%2@got@tlsgd@ha"
[(set_attr "length" "4")])
UNSPEC_TLSGD)
(clobber (reg:SI LR_REGNO))]
"HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
- "bl %z1(%3@tlsgd)\;%."
+ "bl %z1(%3@tlsgd)\;nop"
[(set_attr "type" "branch")
(set_attr "length" "8")])
"HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
{
if (TARGET_CMODEL != CMODEL_SMALL)
- return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;bl %z2\;%.";
+ return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
+ "bl %z2\;nop";
else
- return "addi %0,%1,%&@got@tlsld\;bl %z2\;%.";
+ return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
}
"&& TARGET_TLS_MARKERS"
[(set (match_dup 0)
"addi %0,%1,%&@got@tlsld"
"&& TARGET_CMODEL != CMODEL_SMALL"
[(set (match_dup 2)
- (const:TLSmode
- (plus:TLSmode (match_dup 1)
- (high:TLSmode
- (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))))
+ (high:TLSmode
+ (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
(set (match_dup 0)
(lo_sum:TLSmode (match_dup 2)
(unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
(define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
- (const:TLSmode
- (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
- (high:TLSmode
- (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))))]
+ (high:TLSmode
+ (unspec:TLSmode [(const_int 0)
+ (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
+ UNSPEC_TLSLD)))]
"HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
"addis %0,%1,%&@got@tlsld@ha"
[(set_attr "length" "4")])
(unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
(clobber (reg:SI LR_REGNO))]
"HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
- "bl %z1(%&@tlsld)\;%."
+ "bl %z1(%&@tlsld)\;nop"
[(set_attr "type" "branch")
(set_attr "length" "8")])
"l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
"&& TARGET_CMODEL != CMODEL_SMALL"
[(set (match_dup 3)
- (const:TLSmode
- (plus:TLSmode (match_dup 1)
- (high:TLSmode
- (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))))
+ (high:TLSmode
+ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
(set (match_dup 0)
(lo_sum:TLSmode (match_dup 3)
(unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
(define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
- (const:TLSmode
- (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
- (high:TLSmode
- (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
- UNSPEC_TLSGOTDTPREL)))))]
+ (high:TLSmode
+ (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
+ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
+ UNSPEC_TLSGOTDTPREL)))]
"HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
"addis %0,%1,%2@got@dtprel@ha"
[(set_attr "length" "4")])
"l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
"&& TARGET_CMODEL != CMODEL_SMALL"
[(set (match_dup 3)
- (const:TLSmode
- (plus:TLSmode (match_dup 1)
- (high:TLSmode
- (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))))
+ (high:TLSmode
+ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
(set (match_dup 0)
(lo_sum:TLSmode (match_dup 3)
(unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]
(define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
- (const:TLSmode
- (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
- (high:TLSmode
- (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
- UNSPEC_TLSGOTTPREL)))))]
+ (high:TLSmode
+ (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
+ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
+ UNSPEC_TLSGOTTPREL)))]
"HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
"addis %0,%1,%2@got@tprel@ha"
[(set_attr "length" "4")])
(unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
UNSPEC_TLSTLS))]
- "HAVE_AS_TLS"
+ "TARGET_ELF && HAVE_AS_TLS"
"add %0,%1,%2@tls")
+
+(define_expand "tls_get_tpointer"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "")
+ (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
+ "TARGET_XCOFF && HAVE_AS_TLS"
+ "
+{
+ emit_insn (gen_tls_get_tpointer_internal ());
+ emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
+ DONE;
+}")
+
+(define_insn "tls_get_tpointer_internal"
+ [(set (reg:SI 3)
+ (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
+ (clobber (reg:SI LR_REGNO))]
+ "TARGET_XCOFF && HAVE_AS_TLS"
+ "bla __get_tpointer")
+
+(define_expand "tls_get_addr<mode>"
+ [(set (match_operand:P 0 "gpc_reg_operand" "")
+ (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
+ (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
+ "TARGET_XCOFF && HAVE_AS_TLS"
+ "
+{
+ emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
+ emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
+ emit_insn (gen_tls_get_addr_internal<mode> ());
+ emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
+ DONE;
+}")
+
+(define_insn "tls_get_addr_internal<mode>"
+ [(set (reg:P 3)
+ (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
+ (clobber (reg:P 0))
+ (clobber (reg:P 4))
+ (clobber (reg:P 5))
+ (clobber (reg:P 11))
+ (clobber (reg:CC CR0_REGNO))
+ (clobber (reg:P LR_REGNO))]
+ "TARGET_XCOFF && HAVE_AS_TLS"
+ "bla __tls_get_addr")
\f
;; Next come insns related to the calling sequence.
;;
(define_expand "restore_stack_block"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 4) (match_dup 2))
- (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
+ (match_dup 5)
(set (match_operand 0 "register_operand" "")
(match_operand 1 "register_operand" ""))]
""
"
{
+ rtvec p;
+
operands[1] = force_reg (Pmode, operands[1]);
operands[2] = gen_reg_rtx (Pmode);
operands[3] = gen_frame_mem (Pmode, operands[0]);
operands[4] = gen_frame_mem (Pmode, operands[1]);
- operands[5] = gen_frame_mem (BLKmode, operands[0]);
+ p = rtvec_alloc (1);
+ RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
+ gen_frame_mem (BLKmode, operands[0]),
+ const0_rtx);
+ operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
}")
(define_expand "save_stack_nonlocal"
[(set (match_dup 2) (match_operand 1 "memory_operand" ""))
(set (match_dup 3) (match_dup 4))
(set (match_dup 5) (match_dup 2))
- (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
+ (match_dup 6)
(set (match_operand 0 "register_operand" "") (match_dup 3))]
""
"
{
int units_per_word = (TARGET_32BIT) ? 4 : 8;
+ rtvec p;
/* Restore the backchain from the first word, sp from the second. */
operands[2] = gen_reg_rtx (Pmode);
operands[1] = adjust_address_nv (operands[1], Pmode, 0);
operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
operands[5] = gen_frame_mem (Pmode, operands[3]);
- operands[6] = gen_frame_mem (BLKmode, operands[0]);
+ p = rtvec_alloc (1);
+ RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
+ gen_frame_mem (BLKmode, operands[0]),
+ const0_rtx);
+ operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
}")
\f
;; TOC register handling.
ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
operands[2] = gen_rtx_REG (Pmode, 2);
- return \"{l|lwz} %0,%1(%2)\";
+ return \"lwz %0,%1(%2)\";
}"
[(set_attr "type" "load")])
(minus:SI (match_operand:SI 2 "immediate_operand" "s")
(match_operand:SI 3 "immediate_operand" "s")))))]
"TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
- "{l|lwz} %0,%2-%3(%1)"
+ "lwz %0,%2-%3(%1)"
[(set_attr "type" "load")])
(define_insn "load_toc_v4_PIC_3b"
(minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
(match_operand:SI 3 "symbol_ref_operand" "s")))))]
"TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
- "{cau|addis} %0,%1,%2-%3@ha")
+ "addis %0,%1,%2-%3@ha")
(define_insn "load_toc_v4_PIC_3c"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
(match_operand:SI 3 "symbol_ref_operand" "s"))))]
"TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
- "{cal %0,%2-%3@l(%1)|addi %0,%1,%2-%3@l}")
+ "addi %0,%1,%2-%3@l")
;; If the TOC is shared over a translation unit, as happens with all
;; the kinds of PIC that we support, we need to restore the TOC
DONE;
}")
+;; Largetoc support
+(define_insn "*largetoc_high"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
+ (high:DI
+ (unspec [(match_operand:DI 1 "" "")
+ (match_operand:DI 2 "gpc_reg_operand" "b")]
+ UNSPEC_TOCREL)))]
+ "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
+ "addis %0,%2,%1@toc@ha")
+
+(define_insn "*largetoc_high_aix<mode>"
+ [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
+ (high:P
+ (unspec [(match_operand:P 1 "" "")
+ (match_operand:P 2 "gpc_reg_operand" "b")]
+ UNSPEC_TOCREL)))]
+ "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
+ "addis %0,%1@u(%2)")
+
+(define_insn "*largetoc_high_plus"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
+ (high:DI
+ (plus:DI
+ (unspec [(match_operand:DI 1 "" "")
+ (match_operand:DI 2 "gpc_reg_operand" "b")]
+ UNSPEC_TOCREL)
+ (match_operand 3 "const_int_operand" "n"))))]
+ "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
+ "addis %0,%2,%1+%3@toc@ha")
+
+(define_insn "*largetoc_high_plus_aix<mode>"
+ [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
+ (high:P
+ (plus:P
+ (unspec [(match_operand:P 1 "" "")
+ (match_operand:P 2 "gpc_reg_operand" "b")]
+ UNSPEC_TOCREL)
+ (match_operand 3 "const_int_operand" "n"))))]
+ "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
+ "addis %0,%1+%3@u(%2)")
+
+(define_insn "*largetoc_low"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+ (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
+ (match_operand:DI 2 "" "")))]
+ "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
+ "@
+ addi %0,%1,%2@l
+ addic %0,%1,%2@l")
+
+(define_insn "*largetoc_low_aix<mode>"
+ [(set (match_operand:P 0 "gpc_reg_operand" "=r")
+ (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
+ (match_operand:P 2 "" "")))]
+ "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
+ "la %0,%2@l(%1)")
+
+(define_insn_and_split "*tocref<mode>"
+ [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
+ (match_operand:P 1 "small_toc_ref" "R"))]
+ "TARGET_TOC"
+ "la %0,%a1"
+ "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
+ [(set (match_dup 0) (high:P (match_dup 1)))
+ (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
+
;; Elf specific ways of loading addresses for non-PIC code.
;; The output of this could be r0, but we make a very strong
;; preference for a base register because it will usually
[(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
(high:SI (match_operand 1 "" "")))]
"TARGET_ELF && ! TARGET_64BIT"
- "{liu|lis} %0,%1@ha")
+ "lis %0,%1@ha")
(define_insn "elf_low"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(match_operand 2 "" "")))]
"TARGET_ELF && ! TARGET_64BIT"
"@
- {cal|la} %0,%2@l(%1)
- {ai|addic} %0,%1,%K2")
-
-;; Largetoc support
-(define_insn "largetoc_high"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
- (const:DI
- (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
- (high:DI (match_operand:DI 2 "" "")))))]
- "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
- "{cau|addis} %0,%1,%2@ha")
-
-(define_insn "largetoc_low"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
- (match_operand:DI 2 "" "")))]
- "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
- "{cal %0,%2@l(%1)|addi %0,%1,%2@l}")
+ la %0,%2@l(%1)
+ addic %0,%1,%K2")
\f
;; Call and call_value insns
(define_expand "call"
(define_insn "call_indirect_aix<ptrsize>"
[(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
(match_operand 1 "" "g,g"))
- (use (match_operand:P 2 "memory_operand" "m,m"))
- (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "m,m"))
+ (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
+ (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
(use (reg:P STATIC_CHAIN_REGNUM))
(clobber (reg:P LR_REGNO))]
"DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
(define_insn "call_indirect_aix<ptrsize>_nor11"
[(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
(match_operand 1 "" "g,g"))
- (use (match_operand:P 2 "memory_operand" "m,m"))
- (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "m,m"))
+ (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
+ (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
(clobber (reg:P LR_REGNO))]
"DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
"<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
[(set (match_operand 0 "" "")
(call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
(match_operand 2 "" "g,g")))
- (use (match_operand:P 3 "memory_operand" "m,m"))
- (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "m,m"))
+ (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
+ (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
(use (reg:P STATIC_CHAIN_REGNUM))
(clobber (reg:P LR_REGNO))]
"DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
[(set (match_operand 0 "" "")
(call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
(match_operand 2 "" "g,g")))
- (use (match_operand:P 3 "memory_operand" "m,m"))
- (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "m,m"))
+ (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
+ (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
(clobber (reg:P LR_REGNO))]
"DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
"<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
"TARGET_32BIT
&& DEFAULT_ABI == ABI_AIX
&& (INTVAL (operands[2]) & CALL_LONG) == 0"
- "bl %z0\;%."
+ "bl %z0\;nop"
[(set_attr "type" "branch")
(set_attr "length" "8")])
"TARGET_64BIT
&& DEFAULT_ABI == ABI_AIX
&& (INTVAL (operands[2]) & CALL_LONG) == 0"
- "bl %z0\;%."
+ "bl %z0\;nop"
[(set_attr "type" "branch")
(set_attr "length" "8")])
"TARGET_32BIT
&& DEFAULT_ABI == ABI_AIX
&& (INTVAL (operands[3]) & CALL_LONG) == 0"
- "bl %z1\;%."
+ "bl %z1\;nop"
[(set_attr "type" "branch")
(set_attr "length" "8")])
"TARGET_64BIT
&& DEFAULT_ABI == ABI_AIX
&& (INTVAL (operands[3]) & CALL_LONG) == 0"
- "bl %z1\;%."
+ "bl %z1\;nop"
[(set_attr "type" "branch")
(set_attr "length" "8")])
""
"")
-(define_insn "probe_stack"
+(define_expand "probe_stack"
[(set (match_operand 0 "memory_operand" "=m")
(unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
""
- "*
+{
+ if (TARGET_64BIT)
+ emit_insn (gen_probe_stack_di (operands[0]));
+ else
+ emit_insn (gen_probe_stack_si (operands[0]));
+ DONE;
+})
+
+(define_insn "probe_stack_<mode>"
+ [(set (match_operand:P 0 "memory_operand" "=m")
+ (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
+ ""
{
operands[1] = gen_rtx_REG (Pmode, 0);
- return \"{st%U0%X0|stw%U0%X0} %1,%0\";
-}"
+ return "st<wd>%U0%X0 %1,%0";
+}
[(set_attr "type" "store")
(set_attr "length" "4")])
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
(set (match_scratch:SI 2 "=&r") (const_int 0))]
"TARGET_32BIT"
- "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
+ "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
[(set_attr "type" "three")
(set_attr "length" "12")])
(define_insn "stack_protect_setdi"
- [(set (match_operand:DI 0 "memory_operand" "=m")
- (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
+ [(set (match_operand:DI 0 "memory_operand" "=Y")
+ (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
(set (match_scratch:DI 2 "=&r") (const_int 0))]
"TARGET_64BIT"
- "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
+ "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
[(set_attr "type" "three")
(set_attr "length" "12")])
(clobber (match_scratch:SI 3 "=&r,&r"))]
"TARGET_32BIT"
"@
- {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
- {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
+ lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
+ lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
[(set_attr "length" "16,20")])
(define_insn "stack_protect_testdi"
[(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
- (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
- (match_operand:DI 2 "memory_operand" "m,m")]
+ (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
+ (match_operand:DI 2 "memory_operand" "Y,Y")]
UNSPEC_SP_TEST))
(set (match_scratch:DI 4 "=r,r") (const_int 0))
(clobber (match_scratch:DI 3 "=&r,&r"))]
"TARGET_64BIT"
"@
- ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
- ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
+ ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
+ ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
[(set_attr "length" "16,20")])
\f
(compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "reg_or_short_operand" "rI")))]
""
- "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
+ "cmp<wd>%I2 %0,%1,%2"
[(set_attr "type" "cmp")])
;; If we are comparing a register for equality with a large constant,
(compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
""
- "{cmpl%I2|cmplw%I2} %0,%1,%b2"
+ "cmplw%I2 %0,%1,%b2"
[(set_attr "type" "cmp")])
(define_insn "*cmpdi_internal2"
[(match_operand 2 "cc_reg_operand" "y")
(const_int 0)]))]
""
- "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
+ "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
[(set (attr "type")
(cond [(match_test "TARGET_MFCRF")
(const_string "mfcrf")
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
- "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
+ "mfcr %0\;rlwinm %0,%0,%D1,31,31"
[(set_attr "type" "mfcr")
(set_attr "length" "8")])
;; Same as above, but get the OV/ORDERED bit.
(define_insn "move_from_CR_ov_bit"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
+ (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
+ UNSPEC_MV_CR_OV))]
"TARGET_ISEL"
- "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
+ "mfcr %0\;rlwinm %0,%0,%t1,1"
[(set_attr "type" "mfcr")
(set_attr "length" "8")])
[(match_operand 2 "cc_reg_operand" "y")
(const_int 0)]))]
"TARGET_POWERPC64"
- "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
+ "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
[(set (attr "type")
(cond [(match_test "TARGET_MFCRF")
(const_string "mfcrf")
(match_op_dup 1 [(match_dup 2) (const_int 0)]))]
"TARGET_32BIT"
"@
- mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
+ mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
#"
[(set_attr "type" "delayed_compare")
(set_attr "length" "8,16")])
operands[4] = GEN_INT (count);
operands[5] = GEN_INT (put_bit);
- return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
+ return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
}"
[(set (attr "type")
(cond [(match_test "TARGET_MFCRF")
operands[5] = GEN_INT (count);
operands[6] = GEN_INT (put_bit);
- return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
+ return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
}"
[(set_attr "type" "delayed_compare")
(set_attr "length" "8,16")])
[(match_operand 5 "cc_reg_operand" "y")
(const_int 0)]))]
"REGNO (operands[2]) != REGNO (operands[5])"
- "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
+ "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
[(set_attr "type" "mfcr")
(set_attr "length" "12")])
[(match_operand 5 "cc_reg_operand" "y")
(const_int 0)]))]
"TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
- "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
+ "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
[(set_attr "type" "mfcr")
(set_attr "length" "12")])
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
- "!TARGET_POWER"
+ ""
"#"
- "!TARGET_POWER"
+ ""
[(set (match_dup 0)
(clz:GPR (match_dup 3)))
(set (match_dup 0)
(const_int 0)))
(set (match_operand:P 0 "gpc_reg_operand" "=r")
(eq:P (match_dup 1) (match_dup 2)))]
- "!TARGET_POWER && optimize_size"
+ "optimize_size"
"#"
- "!TARGET_POWER && optimize_size"
+ "optimize_size"
[(set (match_dup 0)
(clz:P (match_dup 4)))
(parallel [(set (match_dup 3)
operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
})
-(define_insn "*eqsi_power"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
- (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
- (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
- "TARGET_POWER"
- "@
- xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
- {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
- {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
- {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
- {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
- [(set_attr "type" "three,two,three,three,three")
- (set_attr "length" "12,8,12,12,12")])
-
;; We have insns of the form shown by the first define_insn below. If
;; there is something inside the comparison operation, we must split it.
(define_split
(clobber (match_operand:SI 5 "register_operand" ""))]
"! gpc_reg_operand (operands[2], SImode)"
[(set (match_dup 5) (match_dup 2))
- (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
+ (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
(match_dup 4)))])
(define_insn "*plus_eqsi"
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
"TARGET_32BIT"
"@
- xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
- {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
- {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
- {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
- {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
+ xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
+ subfic %0,%1,0\;addze %0,%3
+ xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
+ xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
+ subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
[(set_attr "type" "three,two,three,three,three")
(set_attr "length" "12,8,12,12,12")])
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
"TARGET_32BIT && optimize_size"
"@
- xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
- {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
- {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
- {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
- {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
+ xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
+ subfic %4,%1,0\;addze. %4,%3
+ xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
+ xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
+ subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
#
#
#
(plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"TARGET_32BIT && optimize_size"
"@
- xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
- {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
- {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
- {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
- {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
+ xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
+ subfic %0,%1,0\;addze. %0,%3
+ xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
+ xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
+ subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
#
#
#
(neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
(const_int 0))))]
""
- "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
+ "addic %0,%1,-1\;subfe %0,%0,%0"
[(set_attr "type" "two")
(set_attr "length" "8")])
operands[3] = operands[1];
})
-;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
-;; since it nabs/sr is just as fast.
-(define_insn "*ne0si"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
- (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
- (const_int 31)))
- (clobber (match_scratch:SI 2 "=&r"))]
- "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
- "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
- [(set_attr "type" "two")
- (set_attr "length" "8")])
-
-(define_insn "*ne0di"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
- (const_int 63)))
- (clobber (match_scratch:DI 2 "=&r"))]
- "TARGET_64BIT"
+(define_insn "*ne0_<mode>"
+ [(set (match_operand:P 0 "gpc_reg_operand" "=r")
+ (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
+ (const_int 0)))
+ (clobber (match_scratch:P 2 "=&r"))]
+ "!(TARGET_32BIT && TARGET_ISEL)"
"addic %2,%1,-1\;subfe %0,%2,%1"
[(set_attr "type" "two")
(set_attr "length" "8")])
-;; This is what (plus (ne X (const_int 0)) Y) looks like.
-(define_insn "*plus_ne0si"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (lshiftrt:SI
- (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
- (const_int 31))
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (clobber (match_scratch:SI 3 "=&r"))]
- "TARGET_32BIT"
- "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
- [(set_attr "type" "two")
- (set_attr "length" "8")])
-
-(define_insn "*plus_ne0di"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (plus:DI (lshiftrt:DI
- (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
- (const_int 63))
- (match_operand:DI 2 "gpc_reg_operand" "r")))
- (clobber (match_scratch:DI 3 "=&r"))]
- "TARGET_64BIT"
+(define_insn "*plus_ne0_<mode>"
+ [(set (match_operand:P 0 "gpc_reg_operand" "=r")
+ (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
+ (const_int 0))
+ (match_operand:P 2 "gpc_reg_operand" "r")))
+ (clobber (match_scratch:P 3 "=&r"))]
+ ""
"addic %3,%1,-1\;addze %0,%2"
[(set_attr "type" "two")
(set_attr "length" "8")])
-(define_insn "*compare_plus_ne0si"
+(define_insn "*compare_plus_ne0_<mode>"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (plus:SI (lshiftrt:SI
- (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
- (const_int 31))
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=&r,&r"))
- (clobber (match_scratch:SI 4 "=X,&r"))]
- "TARGET_32BIT"
+ (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
+ (const_int 0))
+ (match_operand:P 2 "gpc_reg_operand" "r,r"))
+ (const_int 0)))
+ (clobber (match_scratch:P 3 "=&r,&r"))
+ (clobber (match_scratch:P 4 "=X,&r"))]
+ ""
"@
- {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
+ addic %3,%1,-1\;addze. %3,%2
#"
[(set_attr "type" "compare")
(set_attr "length" "8,12")])
(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (plus:SI (lshiftrt:SI
- (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
- (const_int 31))
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_32BIT && reload_completed"
+ [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
+ (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
+ (const_int 0))
+ (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
+ (clobber (match_scratch:P 3 ""))
+ (clobber (match_scratch:P 4 ""))]
+ "reload_completed"
[(parallel [(set (match_dup 3)
- (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
- (const_int 31))
- (match_dup 2)))
+ (plus:P (ne:P (match_dup 1)
+ (const_int 0))
+ (match_dup 2)))
(clobber (match_dup 4))])
(set (match_dup 0)
(compare:CC (match_dup 3)
(const_int 0)))]
"")
-(define_insn "*compare_plus_ne0di"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (plus:DI (lshiftrt:DI
- (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
- (const_int 63))
- (match_operand:DI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=&r,&r"))]
- "TARGET_64BIT"
+; For combine.
+(define_insn "*compare_plus_ne0_<mode>_1"
+ [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
+ (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
+ (const_int 0))
+ (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
+ (clobber (match_scratch:P 3 "=&r,&r"))
+ (clobber (match_scratch:P 4 "=X,&r"))]
+ ""
"@
addic %3,%1,-1\;addze. %3,%2
#"
(set_attr "length" "8,12")])
(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC
- (plus:DI (lshiftrt:DI
- (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
- (const_int 63))
- (match_operand:DI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_64BIT && reload_completed"
- [(set (match_dup 3)
- (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
- (const_int 63))
- (match_dup 2)))
+ [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
+ (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
+ (const_int 0))
+ (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
+ (clobber (match_scratch:P 3 ""))
+ (clobber (match_scratch:P 4 ""))]
+ "reload_completed"
+ [(parallel [(set (match_dup 3)
+ (plus:P (ne:P (match_dup 1)
+ (const_int 0))
+ (match_dup 2)))
+ (clobber (match_dup 4))])
(set (match_dup 0)
(compare:CC (match_dup 3)
(const_int 0)))]
"")
-(define_insn "*plus_ne0si_compare"
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (plus:SI (lshiftrt:SI
- (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
- (const_int 31))
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
- (match_dup 2)))
- (clobber (match_scratch:SI 3 "=&r,&r"))]
- "TARGET_32BIT"
- "@
- {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "8,12")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (plus:SI (lshiftrt:SI
- (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
- (const_int 31))
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
- (match_dup 2)))
- (clobber (match_scratch:SI 3 ""))]
- "TARGET_32BIT && reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
- (match_dup 2)))
- (clobber (match_dup 3))])
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*plus_ne0di_compare"
+(define_insn "*plus_ne0_<mode>_compare"
[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
(compare:CC
- (plus:DI (lshiftrt:DI
- (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
- (const_int 63))
- (match_operand:DI 2 "gpc_reg_operand" "r,r"))
+ (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
+ (const_int 0))
+ (match_operand:P 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
- (match_dup 2)))
- (clobber (match_scratch:DI 3 "=&r,&r"))]
- "TARGET_64BIT"
+ (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
+ (plus:P (ne:P (match_dup 1)
+ (const_int 0))
+ (match_dup 2)))
+ (clobber (match_scratch:P 3 "=&r,&r"))]
+ ""
"@
addic %3,%1,-1\;addze. %0,%2
#"
(define_split
[(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
(compare:CC
- (plus:DI (lshiftrt:DI
- (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
- (const_int 63))
- (match_operand:DI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
- (match_dup 2)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_64BIT && reload_completed"
- [(parallel [(set (match_dup 0)
- (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
- (match_dup 2)))
- (clobber (match_dup 3))])
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,O")))
- (clobber (match_scratch:SI 3 "=r,X"))]
- "TARGET_POWER"
- "@
- doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
- {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
- [(set_attr "length" "12")])
-
-(define_insn ""
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC
- (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
+ (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
+ (const_int 0))
+ (match_operand:P 2 "gpc_reg_operand" ""))
(const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
- (le:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 3 "=r,X,r,X"))]
- "TARGET_POWER"
- "@
- doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
- {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
- #
- #"
- [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
- (set_attr "length" "12,12,16,16")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (le:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 3 ""))]
- "TARGET_POWER && reload_completed"
+ (set (match_operand:P 0 "gpc_reg_operand" "")
+ (plus:P (ne:P (match_dup 1)
+ (const_int 0))
+ (match_dup 2)))
+ (clobber (match_scratch:P 3 ""))]
+ "reload_completed"
[(parallel [(set (match_dup 0)
- (le:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 3))])
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
- (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,O"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
- "TARGET_POWER"
- "@
- doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
- {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
- [(set_attr "length" "12")])
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC
- (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
- "TARGET_POWER"
- "@
- doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
- {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
- #
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "12,12,16,16")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 4)
- (plus:SI (le:SI (match_dup 1) (match_dup 2))
- (match_dup 3)))
- (set (match_dup 0)
- (compare:CC (match_dup 4)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC
- (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
- (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWER"
- "@
- doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
- {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
- #
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "12,12,16,16")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
+ (plus:P (ne:P (match_dup 1)
+ (const_int 0))
+ (match_dup 2)))
+ (clobber (match_dup 3))])
(set (match_dup 4)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
- "TARGET_POWER"
- "@
- doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
- {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
- [(set_attr "length" "12")])
-
(define_insn "*leu<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=r")
(leu:P (match_operand:P 1 "gpc_reg_operand" "r")
(match_operand:P 2 "reg_or_short_operand" "rI")))]
""
- "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
+ "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
[(set_attr "type" "three")
(set_attr "length" "12")])
(leu:P (match_dup 1) (match_dup 2)))]
""
"@
- {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
+ subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
#"
[(set_attr "type" "compare")
(set_attr "length" "12,16")])
(match_operand:P 2 "reg_or_short_operand" "rI"))
(match_operand:P 3 "gpc_reg_operand" "r")))]
""
- "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
+ "subf%I2c %0,%1,%2\;addze %0,%3"
[(set_attr "type" "two")
(set_attr "length" "8")])
(clobber (match_scratch:SI 4 "=&r,&r"))]
"TARGET_32BIT"
"@
- {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
+ subf%I2c %4,%1,%2\;addze. %4,%3
#"
[(set_attr "type" "compare")
(set_attr "length" "8,12")])
(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"TARGET_32BIT"
"@
- {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
+ subf%I2c %0,%1,%2\;addze. %0,%3
#"
[(set_attr "type" "compare")
(set_attr "length" "8,12")])
(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_32BIT && reload_completed"
- [(set (match_dup 0)
- (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*neg_leu<mode>"
- [(set (match_operand:P 0 "gpc_reg_operand" "=r")
- (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
- (match_operand:P 2 "reg_or_short_operand" "rI"))))]
- ""
- "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
- [(set_attr "type" "three")
- (set_attr "length" "12")])
-
-(define_insn "*and_neg_leu<mode>"
- [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
- (and:P (neg:P
- (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
- (match_operand:P 2 "reg_or_short_operand" "rI")))
- (match_operand:P 3 "gpc_reg_operand" "r")))]
- ""
- "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
- [(set_attr "type" "three")
- (set_attr "length" "12")])
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (and:SI (neg:SI
- (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
- (match_operand:SI 3 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 4 "=&r,&r"))]
- "TARGET_32BIT"
- "@
- {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "12,16")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (and:SI (neg:SI
- (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" "")))
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_32BIT && reload_completed"
- [(set (match_dup 4)
- (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
- (match_dup 3)))
- (set (match_dup 0)
- (compare:CC (match_dup 4)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (and:SI (neg:SI
- (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
- (match_operand:SI 3 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
- (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
- "TARGET_32BIT"
- "@
- {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "12,16")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (and:SI (neg:SI
- (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" "")))
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
- "TARGET_32BIT && reload_completed"
- [(set (match_dup 0)
- (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
- (match_dup 3)))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "rI")))]
- "TARGET_POWER"
- "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
- [(set_attr "length" "12")])
-
-(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC
- (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (lt:SI (match_dup 1) (match_dup 2)))]
- "TARGET_POWER"
- "@
- doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "12,16")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+ [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
(compare:CC
- (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
+ (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "reg_or_short_operand" ""))
+ (match_operand:SI 3 "gpc_reg_operand" ""))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
- (lt:SI (match_dup 1) (match_dup 2)))]
- "TARGET_POWER && reload_completed"
+ (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
+ "TARGET_32BIT && reload_completed"
[(set (match_dup 0)
- (lt:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 3)
+ (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
+ (set (match_dup 4)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
- (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "rI"))
- (match_operand:SI 3 "gpc_reg_operand" "r")))]
- "TARGET_POWER"
- "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
- [(set_attr "length" "12")])
+(define_insn "*neg_leu<mode>"
+ [(set (match_operand:P 0 "gpc_reg_operand" "=r")
+ (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
+ (match_operand:P 2 "reg_or_short_operand" "rI"))))]
+ ""
+ "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
+ [(set_attr "type" "three")
+ (set_attr "length" "12")])
+
+(define_insn "*and_neg_leu<mode>"
+ [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
+ (and:P (neg:P
+ (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
+ (match_operand:P 2 "reg_or_short_operand" "rI")))
+ (match_operand:P 3 "gpc_reg_operand" "r")))]
+ ""
+ "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
+ [(set_attr "type" "three")
+ (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC
- (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r"))
+ (and:SI (neg:SI
+ (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
+ (match_operand:SI 3 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r,&r"))]
- "TARGET_POWER"
+ "TARGET_32BIT"
"@
- doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
+ subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
#"
[(set_attr "type" "compare")
(set_attr "length" "12,16")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
(compare:CC
- (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (match_operand:SI 3 "gpc_reg_operand" ""))
+ (and:SI (neg:SI
+ (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "reg_or_short_operand" "")))
+ (match_operand:SI 3 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
+ "TARGET_32BIT && reload_completed"
[(set (match_dup 4)
- (plus:SI (lt:SI (match_dup 1) (match_dup 2))
- (match_dup 3)))
+ (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
+ (match_dup 3)))
(set (match_dup 0)
(compare:CC (match_dup 4)
(const_int 0)))]
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
(compare:CC
- (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r"))
+ (and:SI (neg:SI
+ (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
+ (match_operand:SI 3 "gpc_reg_operand" "r,r"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
- (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWER"
+ (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
+ "TARGET_32BIT"
"@
- doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
+ subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
#"
[(set_attr "type" "compare")
(set_attr "length" "12,16")])
(define_split
[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
(compare:CC
- (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (match_operand:SI 3 "gpc_reg_operand" ""))
+ (and:SI (neg:SI
+ (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "reg_or_short_operand" "")))
+ (match_operand:SI 3 "gpc_reg_operand" ""))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
- (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWER && reload_completed"
+ (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
+ "TARGET_32BIT && reload_completed"
[(set (match_dup 0)
- (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
+ (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
+ (match_dup 3)))
(set (match_dup 4)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
- "TARGET_POWER"
- "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
- [(set_attr "length" "12")])
-
(define_insn_and_split "*ltu<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
(ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
(match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
""
"@
- {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
- {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
+ subfc %0,%2,%1\;subfe %0,%0,%0
+ addic %0,%1,%n2\;subfe %0,%0,%0"
[(set_attr "type" "two")
(set_attr "length" "8")])
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "rI")))
- (clobber (match_scratch:SI 3 "=r"))]
- "TARGET_POWER"
- "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
- [(set_attr "length" "12")])
-
-(define_insn ""
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ge:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "TARGET_POWER"
- "@
- doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "12,16")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ge:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 3 ""))]
- "TARGET_POWER && reload_completed"
- [(parallel [(set (match_dup 0)
- (ge:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 3))])
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
- (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "rI"))
- (match_operand:SI 3 "gpc_reg_operand" "r")))]
- "TARGET_POWER"
- "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
- [(set_attr "length" "12")])
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 4 "=&r,&r"))]
- "TARGET_POWER"
- "@
- doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "12,16")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 4)
- (plus:SI (ge:SI (match_dup 1) (match_dup 2))
- (match_dup 3)))
- (set (match_dup 0)
- (compare:CC (match_dup 4)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
- (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWER"
- "@
- doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "12,16")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
- "TARGET_POWER"
- "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
- [(set_attr "length" "12")])
-
(define_insn "*geu<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
(geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
(match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
""
"@
- {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
- {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
+ subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
+ addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
[(set_attr "type" "three")
(set_attr "length" "12")])
(geu:P (match_dup 1) (match_dup 2)))]
""
"@
- {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
- {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
+ subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
+ addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
#
#"
[(set_attr "type" "compare")
(match_operand:P 3 "gpc_reg_operand" "r,r")))]
""
"@
- {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
- {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
+ subfc %0,%2,%1\;addze %0,%3
+ addic %0,%1,%n2\;addze %0,%3"
[(set_attr "type" "two")
(set_attr "length" "8")])
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
"TARGET_32BIT"
"@
- {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
- {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
+ subfc %4,%2,%1\;addze. %4,%3
+ addic %4,%1,%n2\;addze. %4,%3
#
#"
[(set_attr "type" "compare")
(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"TARGET_32BIT"
"@
- {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
- {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
+ subfc %0,%2,%1\;addze. %0,%3
+ addic %0,%1,%n2\;addze. %0,%3
#
#"
[(set_attr "type" "compare")
(match_operand:P 2 "reg_or_short_operand" "r,I"))))]
""
"@
- {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
- {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
+ subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
+ subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
[(set_attr "type" "three")
(set_attr "length" "12")])
(match_operand:P 3 "gpc_reg_operand" "r,r")))]
""
"@
- {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
- {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
+ subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
+ addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
[(set_attr "type" "three")
(set_attr "length" "12")])
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
"TARGET_32BIT"
"@
- {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
- {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
+ subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
+ addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
#
#"
[(set_attr "type" "compare")
(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
"TARGET_32BIT"
"@
- {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
- {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
+ subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
+ addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
#
#"
[(set_attr "type" "compare")
(const_int 0)))]
"")
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "r")))]
- "TARGET_POWER"
- "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
- [(set_attr "length" "12")])
-
-(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC
- (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (gt:SI (match_dup 1) (match_dup 2)))]
- "TARGET_POWER"
- "@
- doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
- #"
- [(set_attr "type" "delayed_compare")
- (set_attr "length" "12,16")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (gt:SI (match_dup 1) (match_dup 2)))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (gt:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
(define_insn "*plus_gt0<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=&r")
(plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
(const_int 0))
(match_operand:P 2 "gpc_reg_operand" "r")))]
""
- "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
+ "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
[(set_attr "type" "three")
(set_attr "length" "12")])
(clobber (match_scratch:SI 3 "=&r,&r"))]
"TARGET_32BIT"
"@
- {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
+ addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
#"
[(set_attr "type" "compare")
(set_attr "length" "12,16")])
(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
"TARGET_32BIT"
"@
- {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
+ addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
#"
[(set_attr "type" "compare")
(set_attr "length" "12,16")])
(const_int 0)))]
"")
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
- (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "r"))
- (match_operand:SI 3 "gpc_reg_operand" "r")))]
- "TARGET_POWER"
- "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
- [(set_attr "length" "12")])
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,r"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 4 "=&r,&r"))]
- "TARGET_POWER"
- "@
- doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "12,16")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 4 ""))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 4)
- (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
- (set (match_dup 0)
- (compare:CC (match_dup 4)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "r,r"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
- (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWER"
- "@
- doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "12,16")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_short_operand" ""))
- (match_operand:SI 3 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "r"))))]
- "TARGET_POWER"
- "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
- [(set_attr "length" "12")])
-
(define_insn_and_split "*gtu<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=r")
(gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
(neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
(match_operand:P 2 "reg_or_short_operand" "rI"))))]
""
- "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
+ "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
[(set_attr "type" "two")
(set_attr "length" "8")])
(const_int 0)])
(const_int 0)))]
""
- "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
+ "crnot %E0,%j1"
[(set_attr "type" "cr_logical,delayed_cr")])
;; If we are comparing the result of two comparisons, this can be done
(define_insn "<return_str>return"
[(any_return)]
"<return_pred>"
- "{br|blr}"
+ "blr"
[(set_attr "type" "jmpreg")])
(define_expand "indirect_jump"
""
"@
bctr
- {br|blr}"
+ blr"
[(set_attr "type" "jmpreg")])
;; Table jump for switch statements:
""
"@
bctr
- {br|blr}"
+ blr"
[(set_attr "type" "jmpreg")])
(define_insn "nop"
[(const_int 0)]
""
- "{cror 0,0,0|nop}")
+ "nop")
(define_insn "group_ending_nop"
[(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
(use (match_operand 1 "" "")) ; iterations; zero if unknown
(use (match_operand 2 "" "")) ; max iterations
(use (match_operand 3 "" "")) ; loop level
- (use (match_operand 4 "" ""))] ; label
+ (use (match_operand 4 "" "")) ; label
+ (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0
""
"
{
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
- (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
+ (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
(plus:P (match_dup 1)
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
if (which_alternative != 0)
return \"#\";
else if (get_attr_length (insn) == 4)
- return \"{bdn|bdnz} %l0\";
+ return \"bdnz %l0\";
else
return \"bdz $+8\;b %l0\";
}"
(const_int 1))
(pc)
(label_ref (match_operand 0 "" ""))))
- (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
+ (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
(plus:P (match_dup 1)
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
else if (get_attr_length (insn) == 4)
return \"bdz %l0\";
else
- return \"{bdn|bdnz} $+8\;b %l0\";
+ return \"bdnz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
(set_attr "length" "*,12,16,16")])
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
- (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
+ (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
(plus:P (match_dup 1)
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
else if (get_attr_length (insn) == 4)
return \"bdz %l0\";
else
- return \"{bdn|bdnz} $+8\;b %l0\";
+ return \"bdnz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
(set_attr "length" "*,12,16,16")])
(const_int 1))
(pc)
(label_ref (match_operand 0 "" ""))))
- (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
+ (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
(plus:P (match_dup 1)
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
if (which_alternative != 0)
return \"#\";
else if (get_attr_length (insn) == 4)
- return \"{bdn|bdnz} %l0\";
+ return \"bdnz %l0\";
else
return \"bdz $+8\;b %l0\";
}"
(define_insn "trap"
[(trap_if (const_int 1) (const_int 0))]
""
- "{t 31,0,0|trap}"
+ "trap"
[(set_attr "type" "trap")])
(define_expand "ctrap<mode>4"
(match_operand:GPR 2 "reg_or_short_operand" "rI")])
(const_int 0))]
""
- "{t|t<wd>}%V0%I2 %1,%2"
+ "t<wd>%V0%I2 %1,%2"
[(set_attr "type" "trap")])
\f
;; Insns related to generating the function prologue and epilogue.
[(set (match_operand:SI 1 "memory_operand" "=m")
(match_operand:SI 2 "gpc_reg_operand" "r"))])]
"TARGET_MULTIPLE"
- "{stm|stmw} %2,%1"
+ "stmw %2,%1"
[(set_attr "type" "store_ux")])
; The following comment applies to:
[(set_attr "type" "branch")
(set_attr "length" "4")])
-; These are to explain that changes to the stack pointer should
-; not be moved over stores to stack memory.
+; This is to explain that changes to the stack pointer should
+; not be moved over loads from or stores to stack memory.
(define_insn "stack_tie"
- [(set (match_operand:BLK 0 "memory_operand" "+m")
- (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
- ""
- ""
- [(set_attr "length" "0")])
-
-; Like stack_tie, but depend on both fp and sp based memory.
-(define_insn "frame_tie"
- [(set (match_operand:BLK 0 "memory_operand" "+m")
- (unspec:BLK [(match_dup 0)
- (match_operand:BLK 1 "memory_operand" "m")] UNSPEC_TIE))]
+ [(match_parallel 0 "tie_operand"
+ [(set (mem:BLK (reg 1)) (const_int 0))])]
""
""
[(set_attr "length" "0")])
-
(define_expand "epilogue"
[(use (const_int 0))]
""
[(set (match_operand:SI 1 "gpc_reg_operand" "=r")
(match_operand:SI 2 "memory_operand" "m"))])]
"TARGET_MULTIPLE"
- "{lm|lmw} %1,%2"
+ "lmw %1,%2"
[(set_attr "type" "load_ux")
(set_attr "cell_micro" "always")])
[(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))]
- "TARGET_POWERPC"
+ ""
"*
{
if (GET_CODE (operands[0]) == REG)
""
"")
+(define_expand "rs6000_get_timebase"
+ [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
+ ""
+{
+ if (TARGET_POWERPC64)
+ emit_insn (gen_rs6000_mftb_di (operands[0]));
+ else
+ emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
+ DONE;
+})
+
+(define_insn "rs6000_get_timebase_ppc32"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
+ (clobber (match_scratch:SI 1 "=r"))
+ (clobber (match_scratch:CC 2 "=y"))]
+ "!TARGET_POWERPC64"
+{
+ if (WORDS_BIG_ENDIAN)
+ if (TARGET_MFCRF)
+ {
+ return "mfspr %0,269\;"
+ "mfspr %L0,268\;"
+ "mfspr %1,269\;"
+ "cmpw %2,%0,%1\;"
+ "bne- %2,$-16";
+ }
+ else
+ {
+ return "mftbu %0\;"
+ "mftb %L0\;"
+ "mftbu %1\;"
+ "cmpw %2,%0,%1\;"
+ "bne- %2,$-16";
+ }
+ else
+ if (TARGET_MFCRF)
+ {
+ return "mfspr %L0,269\;"
+ "mfspr %0,268\;"
+ "mfspr %1,269\;"
+ "cmpw %2,%L0,%1\;"
+ "bne- %2,$-16";
+ }
+ else
+ {
+ return "mftbu %L0\;"
+ "mftb %0\;"
+ "mftbu %1\;"
+ "cmpw %2,%L0,%1\;"
+ "bne- %2,$-16";
+ }
+})
+
+(define_insn "rs6000_mftb_<mode>"
+ [(set (match_operand:P 0 "gpc_reg_operand" "=r")
+ (unspec_volatile:P [(const_int 0)] UNSPECV_MFTB))]
+ ""
+{
+ if (TARGET_MFCRF)
+ return "mfspr %0,268";
+ else
+ return "mftb %0";
+})
+
\f
(include "sync.md")
projects / platform / upstream / gcc48.git / blobdiff