(attr_flag "backward"))])
(define_delay (and (eq_attr "type" "uncond_branch")
- (not (match_test "following_call (insn)")))
+ (not (match_test "pa_following_call (insn)")))
[(eq_attr "in_branch_delay" "true") (nil) (nil)])
;; Memory. Disregarding Cache misses, the Mustang memory times are:
;; We have a bypass for all computations in the FP unit which feed an
;; FP store as long as the sizes are the same.
-(define_bypass 2 "W1,W2" "W10,W11" "hppa_fpstore_bypass_p")
-(define_bypass 9 "W3" "W10,W11" "hppa_fpstore_bypass_p")
-(define_bypass 11 "W4" "W10,W11" "hppa_fpstore_bypass_p")
-(define_bypass 13 "W5" "W10,W11" "hppa_fpstore_bypass_p")
-(define_bypass 17 "W6" "W10,W11" "hppa_fpstore_bypass_p")
+(define_bypass 2 "W1,W2" "W10,W11" "pa_fpstore_bypass_p")
+(define_bypass 9 "W3" "W10,W11" "pa_fpstore_bypass_p")
+(define_bypass 11 "W4" "W10,W11" "pa_fpstore_bypass_p")
+(define_bypass 13 "W5" "W10,W11" "pa_fpstore_bypass_p")
+(define_bypass 17 "W6" "W10,W11" "pa_fpstore_bypass_p")
;; We have an "anti-bypass" for FP loads which feed an FP store.
-(define_bypass 4 "W8,W12" "W10,W11" "hppa_fpstore_bypass_p")
+(define_bypass 4 "W8,W12" "W10,W11" "pa_fpstore_bypass_p")
;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
;; floating point computations with non-floating point computations (fp loads
;; We have a bypass for all computations in the FP unit which feed an
;; FP store as long as the sizes are the same.
-(define_bypass 1 "X0" "X6,X7" "hppa_fpstore_bypass_p")
-(define_bypass 7 "X1" "X6,X7" "hppa_fpstore_bypass_p")
-(define_bypass 14 "X2" "X6,X7" "hppa_fpstore_bypass_p")
+(define_bypass 1 "X0" "X6,X7" "pa_fpstore_bypass_p")
+(define_bypass 7 "X1" "X6,X7" "pa_fpstore_bypass_p")
+(define_bypass 14 "X2" "X6,X7" "pa_fpstore_bypass_p")
;; We have an "anti-bypass" for FP loads which feed an FP store.
-(define_bypass 3 "X4,X8" "X6,X7" "hppa_fpstore_bypass_p")
+(define_bypass 3 "X4,X8" "X6,X7" "pa_fpstore_bypass_p")
;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
;; There's no value in modeling the ALU and MUL separately though
"i1_7100lc,i1_7100lc+mem_7100lc")
;; We have an "anti-bypass" for FP loads which feed an FP store.
-(define_bypass 3 "Y3,Y7,Y13,Y17" "Y5,Y6,Y11,Y12,Y15,Y16" "hppa_fpstore_bypass_p")
+(define_bypass 3 "Y3,Y7,Y13,Y17" "Y5,Y6,Y11,Y12,Y15,Y16" "pa_fpstore_bypass_p")
;; Scheduling for the PA8000 is somewhat different than scheduling for a
;; traditional architecture.
""
"
{
- emit_bcond_fp (operands);
+ pa_emit_bcond_fp (operands);
DONE;
}")
""
"
{
- emit_bcond_fp (operands);
+ pa_emit_bcond_fp (operands);
DONE;
}")
""
"*
{
- return output_cbranch (operands, 0, insn);
+ return pa_output_cbranch (operands, 0, insn);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
""
"*
{
- return output_cbranch (operands, 1, insn);
+ return pa_output_cbranch (operands, 1, insn);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_cbranch (operands, 0, insn);
+ return pa_output_cbranch (operands, 0, insn);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_cbranch (operands, 1, insn);
+ return pa_output_cbranch (operands, 1, insn);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_cbranch (operands, 0, insn);
+ return pa_output_cbranch (operands, 0, insn);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_cbranch (operands, 1, insn);
+ return pa_output_cbranch (operands, 1, insn);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
""
"*
{
- return output_bb (operands, 0, insn, 0);
+ return pa_output_bb (operands, 0, insn, 0);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_bb (operands, 0, insn, 0);
+ return pa_output_bb (operands, 0, insn, 0);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
""
"*
{
- return output_bb (operands, 1, insn, 0);
+ return pa_output_bb (operands, 1, insn, 0);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_bb (operands, 1, insn, 0);
+ return pa_output_bb (operands, 1, insn, 0);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
""
"*
{
- return output_bb (operands, 0, insn, 1);
+ return pa_output_bb (operands, 0, insn, 1);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_bb (operands, 0, insn, 1);
+ return pa_output_bb (operands, 0, insn, 1);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
""
"*
{
- return output_bb (operands, 1, insn, 1);
+ return pa_output_bb (operands, 1, insn, 1);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_bb (operands, 1, insn, 1);
+ return pa_output_bb (operands, 1, insn, 1);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
""
"*
{
- return output_bvb (operands, 0, insn, 0);
+ return pa_output_bvb (operands, 0, insn, 0);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_bvb (operands, 0, insn, 0);
+ return pa_output_bvb (operands, 0, insn, 0);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
""
"*
{
- return output_bvb (operands, 1, insn, 0);
+ return pa_output_bvb (operands, 1, insn, 0);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_bvb (operands, 1, insn, 0);
+ return pa_output_bvb (operands, 1, insn, 0);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
""
"*
{
- return output_bvb (operands, 0, insn, 1);
+ return pa_output_bvb (operands, 0, insn, 1);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_bvb (operands, 0, insn, 1);
+ return pa_output_bvb (operands, 0, insn, 1);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
""
"*
{
- return output_bvb (operands, 1, insn, 1);
+ return pa_output_bvb (operands, 1, insn, 1);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_bvb (operands, 1, insn, 1);
+ return pa_output_bvb (operands, 1, insn, 1);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b,n .+%0\", xoperands);
else
output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b .+%0\", xoperands);
- return output_lbranch (operands[0], insn, xdelay);
+ return pa_output_lbranch (operands[0], insn, xdelay);
}"
[(set_attr "type" "fbranch")
(set (attr "length")
output_asm_insn (\"ftest\;b,n .+%0\", xoperands);
else
output_asm_insn (\"ftest\;b .+%0\", xoperands);
- return output_lbranch (operands[0], insn, xdelay);
+ return pa_output_lbranch (operands[0], insn, xdelay);
}"
[(set_attr "type" "fbranch")
(set (attr "length")
""
"
{
- if (emit_move_sequence (operands, SImode, 0))
+ if (pa_emit_move_sequence (operands, SImode, 0))
DONE;
}")
""
"
{
- if (emit_move_sequence (operands, SImode, operands[2]))
+ if (pa_emit_move_sequence (operands, SImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
""
"
{
- if (emit_move_sequence (operands, SImode, operands[2]))
+ if (pa_emit_move_sequence (operands, SImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
""
"
{
- if (emit_move_sequence (operands, SImode, operands[2]))
+ if (pa_emit_move_sequence (operands, SImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
[(set (match_operand:SI 0 "register_operand" "=r")
(high:SI (match_operand 1 "" "")))]
"(!flag_pic || !symbolic_operand (operands[1], Pmode))
- && !is_function_label_plus_const (operands[1])"
+ && !pa_is_function_label_plus_const (operands[1])"
"*
{
if (symbolic_operand (operands[1], Pmode))
[(set (match_operand:SI 0 "register_operand" "=r")
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "immediate_operand" "i")))]
- "!is_function_label_plus_const (operands[2])"
+ "!pa_is_function_label_plus_const (operands[2])"
"*
{
gcc_assert (!flag_pic || !symbolic_operand (operands[2], Pmode));
""
"
{
- if (emit_move_sequence (operands, HImode, 0))
+ if (pa_emit_move_sequence (operands, HImode, 0))
DONE;
}")
""
"
{
- if (emit_move_sequence (operands, HImode, operands[2]))
+ if (pa_emit_move_sequence (operands, HImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
""
"
{
- if (emit_move_sequence (operands, HImode, operands[2]))
+ if (pa_emit_move_sequence (operands, HImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
""
"
{
- if (emit_move_sequence (operands, QImode, 0))
+ if (pa_emit_move_sequence (operands, QImode, 0))
DONE;
}")
""
"
{
- if (emit_move_sequence (operands, QImode, operands[2]))
+ if (pa_emit_move_sequence (operands, QImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
""
"
{
- if (emit_move_sequence (operands, QImode, operands[2]))
+ if (pa_emit_move_sequence (operands, QImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
}")
;; The operand constraints are written like this to support both compile-time
-;; and run-time determined byte counts. The expander and output_block_move
+;; and run-time determined byte counts. The expander and pa_output_block_move
;; only support compile-time determined counts at this time.
;;
;; If the count is run-time determined, the register with the byte count
(use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
(const_int 0)]
"!TARGET_64BIT && reload_completed"
- "* return output_block_move (operands, !which_alternative);"
+ "* return pa_output_block_move (operands, !which_alternative);"
[(set_attr "type" "multi,multi")])
(define_expand "movmemdi"
}")
;; The operand constraints are written like this to support both compile-time
-;; and run-time determined byte counts. The expander and output_block_move
+;; and run-time determined byte counts. The expander and pa_output_block_move
;; only support compile-time determined counts at this time.
;;
;; If the count is run-time determined, the register with the byte count
(use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
(const_int 0)]
"TARGET_64BIT && reload_completed"
- "* return output_block_move (operands, !which_alternative);"
+ "* return pa_output_block_move (operands, !which_alternative);"
[(set_attr "type" "multi,multi")])
(define_expand "setmemsi"
(use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
(const_int 0)]
"!TARGET_64BIT && reload_completed"
- "* return output_block_clear (operands, !which_alternative);"
+ "* return pa_output_block_clear (operands, !which_alternative);"
[(set_attr "type" "multi,multi")])
(define_expand "setmemdi"
(use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
(const_int 0)]
"TARGET_64BIT && reload_completed"
- "* return output_block_clear (operands, !which_alternative);"
+ "* return pa_output_block_clear (operands, !which_alternative);"
[(set_attr "type" "multi,multi")])
\f
;; Floating point move insns
&& operands[1] != CONST0_RTX (DFmode)
&& !TARGET_64BIT
&& !TARGET_SOFT_FLOAT"
- "* return (which_alternative == 0 ? output_move_double (operands)
+ "* return (which_alternative == 0 ? pa_output_move_double (operands)
: \"fldd%F1 %1,%0\");"
[(set_attr "type" "move,fpload")
(set_attr "length" "16,4")])
operands[1] = force_const_mem (DFmode, operands[1]);
}
- if (emit_move_sequence (operands, DFmode, 0))
+ if (pa_emit_move_sequence (operands, DFmode, 0))
DONE;
}")
""
"
{
- if (emit_move_sequence (operands, DFmode, operands[2]))
+ if (pa_emit_move_sequence (operands, DFmode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
""
"
{
- if (emit_move_sequence (operands, DFmode, operands[2]))
+ if (pa_emit_move_sequence (operands, DFmode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
|| operands[1] == CONST0_RTX (DFmode))
&& !(REG_P (operands[0]) && REG_P (operands[1])
&& FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
- return output_fp_move_double (operands);
- return output_move_double (operands);
+ return pa_output_fp_move_double (operands);
+ return pa_output_move_double (operands);
}"
[(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load,fpstore_load,store_fpload")
(set_attr "length" "4,8,4,8,16,4,8,16,12,12")])
&& TARGET_SOFT_FLOAT"
"*
{
- return output_move_double (operands);
+ return pa_output_move_double (operands);
}"
[(set_attr "type" "move,store,store,load,load")
(set_attr "length" "8,8,16,8,16")])
&& REGNO (operands[0]) >= 32)
FAIL;
- if (emit_move_sequence (operands, DImode, 0))
+ if (pa_emit_move_sequence (operands, DImode, 0))
DONE;
}")
""
"
{
- if (emit_move_sequence (operands, DImode, operands[2]))
+ if (pa_emit_move_sequence (operands, DImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
""
"
{
- if (emit_move_sequence (operands, DImode, operands[2]))
+ if (pa_emit_move_sequence (operands, DImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
""
"
{
- if (emit_move_sequence (operands, DImode, operands[2]))
+ if (pa_emit_move_sequence (operands, DImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
operands[0] = operand_subword (op0, 0, 0, DImode);
operands[1] = GEN_INT (INTVAL (op1) >> 32);
- output_asm_insn (singlemove_string (operands), operands);
+ output_asm_insn (pa_singlemove_string (operands), operands);
#endif
break;
operands[0] = operand_subword (op0, 0, 0, DImode);
operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
- output_asm_insn (singlemove_string (operands), operands);
+ output_asm_insn (pa_singlemove_string (operands), operands);
break;
default:
|| operands[1] == CONST0_RTX (DFmode))
&& !(REG_P (operands[0]) && REG_P (operands[1])
&& FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
- return output_fp_move_double (operands);
- return output_move_double (operands);
+ return pa_output_fp_move_double (operands);
+ return pa_output_move_double (operands);
}"
[(set_attr "type"
"move,store,store,load,load,multi,fpalu,fpload,fpstore,fpstore_load,store_fpload")
&& TARGET_SOFT_FLOAT"
"*
{
- return output_move_double (operands);
+ return pa_output_move_double (operands);
}"
[(set_attr "type" "move,store,store,load,load,multi")
(set_attr "length" "8,8,16,8,16,16")])
"GET_CODE (operands[1]) == CONST_DOUBLE
&& operands[1] != CONST0_RTX (SFmode)
&& ! TARGET_SOFT_FLOAT"
- "* return (which_alternative == 0 ? singlemove_string (operands)
+ "* return (which_alternative == 0 ? pa_singlemove_string (operands)
: \" fldw%F1 %1,%0\");"
[(set_attr "type" "move,fpload")
(set_attr "length" "8,4")])
&& REGNO (operands[0]) >= 32)
FAIL;
- if (emit_move_sequence (operands, SFmode, 0))
+ if (pa_emit_move_sequence (operands, SFmode, 0))
DONE;
}")
""
"
{
- if (emit_move_sequence (operands, SFmode, operands[2]))
+ if (pa_emit_move_sequence (operands, SFmode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
""
"
{
- if (emit_move_sequence (operands, SFmode, operands[2]))
+ if (pa_emit_move_sequence (operands, SFmode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
(plus:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(clobber (match_operand:SI 4 "register_operand" ""))]
- "! cint_ok_for_move (INTVAL (operands[2]))
+ "! pa_cint_ok_for_move (INTVAL (operands[2]))
&& VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
[(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
(plus:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(clobber (match_operand:SI 4 "register_operand" ""))]
- "! cint_ok_for_move (INTVAL (operands[2]))"
+ "! pa_cint_ok_for_move (INTVAL (operands[2]))"
[(set (match_dup 4) (match_dup 2))
(set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
(match_dup 1)))]
/* Try dividing the constant by 2, then 4, and finally 8 to see
if we can get a constant which can be loaded into a register
- in a single instruction (cint_ok_for_move).
+ in a single instruction (pa_cint_ok_for_move).
If that fails, try to negate the constant and subtract it
from our input operand. */
- if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
+ if (intval % 2 == 0 && pa_cint_ok_for_move (intval / 2))
{
operands[2] = GEN_INT (intval / 2);
operands[3] = const2_rtx;
}
- else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
+ else if (intval % 4 == 0 && pa_cint_ok_for_move (intval / 4))
{
operands[2] = GEN_INT (intval / 4);
operands[3] = GEN_INT (4);
}
- else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
+ else if (intval % 8 == 0 && pa_cint_ok_for_move (intval / 8))
{
operands[2] = GEN_INT (intval / 8);
operands[3] = GEN_INT (8);
}
- else if (cint_ok_for_move (-intval))
+ else if (pa_cint_ok_for_move (-intval))
{
emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
"!TARGET_64BIT"
- "* return output_mul_insn (0, insn);"
+ "* return pa_output_mul_insn (0, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
(define_insn ""
[(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
(clobber (reg:SI 25))
(clobber (reg:SI 2))]
"TARGET_64BIT"
- "* return output_mul_insn (0, insn);"
+ "* return pa_output_mul_insn (0, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
(define_expand "muldi3"
[(set (match_operand:DI 0 "register_operand" "")
operands[5] = gen_rtx_REG (SImode, 31);
operands[4] = gen_reg_rtx (SImode);
}
- if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
+ if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 0))
DONE;
}")
(clobber (reg:SI 31))]
"!TARGET_64BIT"
"*
- return output_div_insn (operands, 0, insn);"
+ return pa_output_div_insn (operands, 0, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
(define_insn ""
[(set (reg:SI 29)
(clobber (reg:SI 2))]
"TARGET_64BIT"
"*
- return output_div_insn (operands, 0, insn);"
+ return pa_output_div_insn (operands, 0, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
(define_expand "udivsi3"
[(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
operands[5] = gen_rtx_REG (SImode, 31);
operands[4] = gen_reg_rtx (SImode);
}
- if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
+ if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 1))
DONE;
}")
(clobber (reg:SI 31))]
"!TARGET_64BIT"
"*
- return output_div_insn (operands, 1, insn);"
+ return pa_output_div_insn (operands, 1, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
(define_insn ""
[(set (reg:SI 29)
(clobber (reg:SI 2))]
"TARGET_64BIT"
"*
- return output_div_insn (operands, 1, insn);"
+ return pa_output_div_insn (operands, 1, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
(define_expand "modsi3"
[(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
(clobber (reg:SI 31))]
"!TARGET_64BIT"
"*
- return output_mod_insn (0, insn);"
+ return pa_output_mod_insn (0, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
(define_insn ""
[(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
(clobber (reg:SI 2))]
"TARGET_64BIT"
"*
- return output_mod_insn (0, insn);"
+ return pa_output_mod_insn (0, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
(define_expand "umodsi3"
[(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
(clobber (reg:SI 31))]
"!TARGET_64BIT"
"*
- return output_mod_insn (1, insn);"
+ return pa_output_mod_insn (1, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
(define_insn ""
[(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
(clobber (reg:SI 2))]
"TARGET_64BIT"
"*
- return output_mod_insn (1, insn);"
+ return pa_output_mod_insn (1, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
;;- and instructions
;; We define DImode `and` so with DImode `not` we can get
(and:DI (match_operand:DI 1 "register_operand" "%?r,0")
(match_operand:DI 2 "and_operand" "rO,P")))]
"TARGET_64BIT"
- "* return output_64bit_and (operands); "
+ "* return pa_output_64bit_and (operands); "
[(set_attr "type" "binary")
(set_attr "length" "4")])
(and:SI (match_operand:SI 1 "register_operand" "%?r,0")
(match_operand:SI 2 "and_operand" "rO,P")))]
""
- "* return output_and (operands); "
+ "* return pa_output_and (operands); "
[(set_attr "type" "binary,shift")
(set_attr "length" "4,4")])
(ior:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "cint_ior_operand" "M,i")))]
"TARGET_64BIT"
- "* return output_64bit_ior (operands); "
+ "* return pa_output_64bit_ior (operands); "
[(set_attr "type" "binary,shift")
(set_attr "length" "4,4")])
(ior:SI (match_operand:SI 1 "register_operand" "0,0")
(match_operand:SI 2 "cint_ior_operand" "M,i")))]
""
- "* return output_ior (operands); "
+ "* return pa_output_ior (operands); "
[(set_attr "type" "binary,shift")
(set_attr "length" "4,4")])
(define_expand "prologue"
[(const_int 0)]
""
- "hppa_expand_prologue ();DONE;")
+ "pa_expand_prologue ();DONE;")
(define_expand "sibcall_epilogue"
[(return)]
""
"
{
- hppa_expand_epilogue ();
+ pa_expand_epilogue ();
DONE;
}")
x = gen_return ();
else
{
- hppa_expand_epilogue ();
+ pa_expand_epilogue ();
/* EH returns bypass the normal return stub. Thus, we must do an
interspace branch to return from functions that call eh_return.
if (get_attr_length (insn) < 16)
return \"b%* %l0\";
- return output_lbranch (operands[0], insn, 1);
+ return pa_output_lbranch (operands[0], insn, 1);
}"
[(set_attr "type" "uncond_branch")
(set_attr "pa_combine_type" "uncond_branch")
(set (attr "length")
- (cond [(match_test "jump_in_call_delay (insn)")
+ (cond [(match_test "pa_jump_in_call_delay (insn)")
(if_then_else (lt (abs (minus (match_dup 0)
(plus (pc) (const_int 8))))
(const_int MAX_12BIT_OFFSET))
"!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[0], 0);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[0], 0);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 0)"))])
(define_insn "call_symref_pic"
[(set (match_operand:SI 2 "register_operand" "=&r") (reg:SI 19))
"!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[0], 0);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[0], 0);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 0)"))])
;; This pattern is split if it is necessary to save and restore the
;; PIC register.
"TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[0], 0);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[0], 0);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 0)"))])
(define_insn "call_reg"
[(call (mem:SI (reg:SI 22))
"!TARGET_64BIT"
"*
{
- return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
+ return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
}"
[(set_attr "type" "dyncall")
- (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_indirect_call (insn)"))])
;; This pattern is split if it is necessary to save and restore the
;; PIC register.
"!TARGET_64BIT"
"*
{
- return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
+ return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
}"
[(set_attr "type" "dyncall")
- (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_indirect_call (insn)"))])
;; This pattern is split if it is necessary to save and restore the
;; PIC register.
"TARGET_64BIT"
"*
{
- return output_indirect_call (insn, operands[0]);
+ return pa_output_indirect_call (insn, operands[0]);
}"
[(set_attr "type" "dyncall")
- (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_indirect_call (insn)"))])
(define_expand "call_value"
[(parallel [(set (match_operand 0 "" "")
"!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[1], 0);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[1], 0);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 0)"))])
(define_insn "call_val_symref_pic"
[(set (match_operand:SI 3 "register_operand" "=&r") (reg:SI 19))
"!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[1], 0);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[1], 0);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 0)"))])
;; This pattern is split if it is necessary to save and restore the
;; PIC register.
"TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[1], 0);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[1], 0);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 0)"))])
(define_insn "call_val_reg"
[(set (match_operand 0 "" "")
"!TARGET_64BIT"
"*
{
- return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
+ return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
}"
[(set_attr "type" "dyncall")
- (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_indirect_call (insn)"))])
;; This pattern is split if it is necessary to save and restore the
;; PIC register.
"!TARGET_64BIT"
"*
{
- return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
+ return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
}"
[(set_attr "type" "dyncall")
- (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_indirect_call (insn)"))])
;; This pattern is split if it is necessary to save and restore the
;; PIC register.
"TARGET_64BIT"
"*
{
- return output_indirect_call (insn, operands[1]);
+ return pa_output_indirect_call (insn, operands[1]);
}"
[(set_attr "type" "dyncall")
- (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_indirect_call (insn)"))])
;; Call subroutine returning any type.
"!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[0], 1);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[0], 1);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 1)"))])
(define_insn "sibcall_internal_symref_64bit"
[(call (mem:SI (match_operand 0 "call_operand_address" ""))
"TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[0], 1);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[0], 1);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 1)"))])
(define_expand "sibcall_value"
[(set (match_operand 0 "" "")
"!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[1], 1);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[1], 1);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 1)"))])
(define_insn "sibcall_value_internal_symref_64bit"
[(set (match_operand 0 "" "")
"TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[1], 1);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[1], 1);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 1)"))])
(define_insn "nop"
[(const_int 0)]
(plus:SI (match_dup 0) (match_dup 1)))
(clobber (match_scratch:SI 4 "=X,r,r"))]
""
- "* return output_dbra (operands, insn, which_alternative); "
+ "* return pa_output_dbra (operands, insn, which_alternative); "
;; Do not expect to understand this the first time through.
[(set_attr "type" "cbranch,multi,multi")
(set (attr "length")
(set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
(match_dup 1))]
""
-"* return output_movb (operands, insn, which_alternative, 0); "
+"* return pa_output_movb (operands, insn, which_alternative, 0); "
;; Do not expect to understand this the first time through.
[(set_attr "type" "cbranch,multi,multi,multi")
(set (attr "length")
(set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
(match_dup 1))]
""
-"* return output_movb (operands, insn, which_alternative, 1); "
+"* return pa_output_movb (operands, insn, which_alternative, 1); "
;; Do not expect to understand this the first time through.
[(set_attr "type" "cbranch,multi,multi,multi")
(set (attr "length")
"(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
"*
{
- return output_parallel_addb (operands, insn);
+ return pa_output_parallel_addb (operands, insn);
}"
[(set_attr "type" "parallel_branch")
(set (attr "length")
"reload_completed"
"*
{
- return output_parallel_movb (operands, insn);
+ return pa_output_parallel_movb (operands, insn);
}"
[(set_attr "type" "parallel_branch")
(set (attr "length")
"reload_completed"
"*
{
- return output_parallel_movb (operands, insn);
+ return pa_output_parallel_movb (operands, insn);
}"
[(set_attr "type" "parallel_branch")
(set (attr "length")
"reload_completed"
"*
{
- return output_parallel_movb (operands, insn);
+ return pa_output_parallel_movb (operands, insn);
}"
[(set_attr "type" "parallel_branch")
(set (attr "length")
"reload_completed"
"*
{
- return output_parallel_movb (operands, insn);
+ return pa_output_parallel_movb (operands, insn);
}"
[(set_attr "type" "parallel_branch")
(set (attr "length")
(plus (match_operand 4 "register_operand" "f")
(match_operand 5 "register_operand" "f")))]
"TARGET_PA_11 && ! TARGET_SOFT_FLOAT
- && reload_completed && fmpyaddoperands (operands)"
+ && reload_completed && pa_fmpyaddoperands (operands)"
"*
{
if (GET_MODE (operands[0]) == DFmode)
(mult (match_operand 1 "register_operand" "f")
(match_operand 2 "register_operand" "f")))]
"TARGET_PA_11 && ! TARGET_SOFT_FLOAT
- && reload_completed && fmpyaddoperands (operands)"
+ && reload_completed && pa_fmpyaddoperands (operands)"
"*
{
if (GET_MODE (operands[0]) == DFmode)
(minus (match_operand 4 "register_operand" "f")
(match_operand 5 "register_operand" "f")))]
"TARGET_PA_11 && ! TARGET_SOFT_FLOAT
- && reload_completed && fmpysuboperands (operands)"
+ && reload_completed && pa_fmpysuboperands (operands)"
"*
{
if (GET_MODE (operands[0]) == DFmode)
(mult (match_operand 1 "register_operand" "f")
(match_operand 2 "register_operand" "f")))]
"TARGET_PA_11 && ! TARGET_SOFT_FLOAT
- && reload_completed && fmpysuboperands (operands)"
+ && reload_completed && pa_fmpysuboperands (operands)"
"*
{
if (GET_MODE (operands[0]) == DFmode)
output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
/* Finally, call $$sh_func_adrs to extract the function's real add24. */
- return output_millicode_call (insn,
- gen_rtx_SYMBOL_REF (SImode,
- \"$$sh_func_adrs\"));
+ return pa_output_millicode_call (insn,
+ gen_rtx_SYMBOL_REF (SImode,
+ \"$$sh_func_adrs\"));
}"
[(set_attr "type" "multi")
(set (attr "length")
- (plus (symbol_ref "attr_length_millicode_call (insn)")
+ (plus (symbol_ref "pa_attr_length_millicode_call (insn)")
(const_int 20)))])
;; On the PA, the PIC register is call clobbered, so it must
projects / platform / upstream / gcc.git / blobdiff