/* Definitions of target machine for GNU compiler, for the HP Spectrum.
- Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
- 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
+ Copyright (C) 1992-2014 Free Software Foundation, Inc.
Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support
and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for
Software Science at the University of Utah.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
+the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
-along with GCC; see the file COPYING. If not, write to
-the Free Software Foundation, 51 Franklin Street, Fifth Floor,
-Boston, MA 02110-1301, USA. */
-
-enum cmp_type /* comparison type */
-{
- CMP_SI, /* compare integers */
- CMP_SF, /* compare single precision floats */
- CMP_DF, /* compare double precision floats */
- CMP_MAX /* max comparison type */
-};
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
/* For long call handling. */
extern unsigned long total_code_bytes;
-/* Which processor to schedule for. */
-
-enum processor_type
-{
- PROCESSOR_700,
- PROCESSOR_7100,
- PROCESSOR_7100LC,
- PROCESSOR_7200,
- PROCESSOR_7300,
- PROCESSOR_8000
-};
-
-/* For -mschedule= option. */
-extern enum processor_type pa_cpu;
-
-/* For -munix= option. */
-extern int flag_pa_unix;
-
#define pa_cpu_attr ((enum attr_cpu)pa_cpu)
-/* Print subsidiary information on the compiler version in use. */
-
-#define TARGET_VERSION fputs (" (hppa)", stderr);
-
#define TARGET_PA_10 (!TARGET_PA_11 && !TARGET_PA_20)
/* Generate code for the HPPA 2.0 architecture in 64bit mode. */
#define TARGET_HPUX_11_11 0
#endif
+/* HP-UX 11i multibyte and UNIX 2003 extensions. */
+#ifndef TARGET_HPUX_11_31
+#define TARGET_HPUX_11_31 0
+#endif
+
+/* HP-UX long double library. */
+#ifndef HPUX_LONG_DOUBLE_LIBRARY
+#define HPUX_LONG_DOUBLE_LIBRARY 0
+#endif
+
+/* Linux kernel atomic operation support. */
+#ifndef TARGET_SYNC_LIBCALL
+#define TARGET_SYNC_LIBCALL 0
+#endif
+
/* The following three defines are potential target switches. The current
defines are optimal given the current capabilities of GAS and GNU ld. */
calls. They are used only in non-pic code. */
#define TARGET_LONG_ABS_CALL (TARGET_SOM && !TARGET_GAS)
-/* Define to a C expression evaluating to true to use long pic symbol
- difference calls. This is a call variant similar to the long pic
- pc-relative call. Long pic symbol difference calls are only used with
- the HP SOM linker. Currently, only the HP assembler supports these
- calls. GAS doesn't allow an arbitrary difference of two symbols. */
-#define TARGET_LONG_PIC_SDIFF_CALL (!TARGET_GAS)
-
-/* Define to a C expression evaluating to true to use long pic
- pc-relative calls. Long pic pc-relative calls are only used with
- GAS. Currently, they are usable for calls within a module but
- not for external calls. */
+/* Define to a C expression evaluating to true to use long PIC symbol
+ difference calls. Long PIC symbol difference calls are only used with
+ the HP assembler and linker. The HP assembler detects this instruction
+ sequence and treats it as long pc-relative call. Currently, GAS only
+ allows a difference of two symbols in the same subspace, and it doesn't
+ detect the sequence as a pc-relative call. */
+#define TARGET_LONG_PIC_SDIFF_CALL (!TARGET_GAS && TARGET_HPUX)
+
+/* Define to a C expression evaluating to true to use long PIC
+ pc-relative calls. Long PIC pc-relative calls are only used with
+ GAS. Currently, they are usable for calls which bind local to a
+ module but not for external calls. */
#define TARGET_LONG_PIC_PCREL_CALL 0
/* Define to a C expression evaluating to true to use SOM secondary
#define TARGET_HPUX_UNWIND_LIBRARY 0
#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY | MASK_BIG_SWITCH)
+#define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY)
#endif
#ifndef TARGET_CPU_DEFAULT
and the old mnemonics are dialect zero. */
#define ASSEMBLER_DIALECT (TARGET_PA_20 ? 1 : 0)
-#define OVERRIDE_OPTIONS override_options ()
-
/* Override some settings from dbxelf.h. */
/* We do not have to be compatible with dbx, so we enable gdb extensions
the stack pointer at the function's entry. Yuk! */
#define DEBUGGER_AUTO_OFFSET(X) \
((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
- + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
+ + (frame_pointer_needed ? 0 : pa_compute_frame_size (get_frame_size (), 0)))
#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
((GET_CODE (X) == PLUS ? OFFSET : 0) \
- + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
+ + (frame_pointer_needed ? 0 : pa_compute_frame_size (get_frame_size (), 0)))
#define TARGET_CPU_CPP_BUILTINS() \
do { \
#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
#endif
-/* This macro defines command-line switches that modify the default
- target name.
-
- The definition is be an initializer for an array of structures. Each
- array element has have three elements: the switch name, one of the
- enumeration codes ADD or DELETE to indicate whether the string should be
- inserted or deleted, and the string to be inserted or deleted. */
-#define MODIFY_TARGET_NAME {{"-32", DELETE, "64"}, {"-64", ADD, "64"}}
-
/* Make gcc agree with <machine/ansi.h> */
#define SIZE_TYPE "unsigned int"
#define PTRDIFF_TYPE "int"
#define WCHAR_TYPE "unsigned int"
#define WCHAR_TYPE_SIZE 32
-
-/* Show we can debug even without a frame pointer. */
-#define CAN_DEBUG_WITHOUT_FP
\f
/* target machine storage layout */
-typedef struct machine_function GTY(())
+typedef struct GTY(()) machine_function
{
/* Flag indicating that a .NSUBSPA directive has been output for
this function. */
#define BIGGEST_ALIGNMENT (2 * BITS_PER_WORD)
/* Get around hp-ux assembler bug, and make strcpy of constants fast. */
-#define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \
- ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN))
+#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
+ (TREE_CODE (EXP) == STRING_CST \
+ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
/* Make arrays of chars word-aligned for the same reasons. */
#define DATA_ALIGNMENT(TYPE, ALIGN) \
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
- (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
+ pa_modes_tieable_p (MODE1, MODE2)
/* Specify the registers used for certain standard purposes.
The values of these macros are register numbers. */
/* Register to use for pushing function arguments. */
#define STACK_POINTER_REGNUM 30
-/* Base register for access to local variables of the function. */
-#define FRAME_POINTER_REGNUM 3
+/* Fixed register for local variable access. Always eliminated. */
+#define FRAME_POINTER_REGNUM (TARGET_64BIT ? 61 : 89)
-/* Value should be nonzero if functions must have frame pointers. */
-#define FRAME_POINTER_REQUIRED \
- (current_function_calls_alloca)
+/* Base register for access to local variables of the function. */
+#define HARD_FRAME_POINTER_REGNUM 3
/* Don't allow hard registers to be renamed into r2 unless r2
is already live or already being saved (due to eh). */
#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
- ((NEW_REG) != 2 || df_regs_ever_live_p (2) || current_function_calls_eh_return)
-
-/* C statement to store the difference between the frame pointer
- and the stack pointer values immediately after the function prologue.
-
- Note, we always pretend that this is a leaf function because if
- it's not, there's no point in trying to eliminate the
- frame pointer. If it is a leaf function, we guessed right! */
-#define INITIAL_FRAME_POINTER_OFFSET(VAR) \
- do {(VAR) = - compute_frame_size (get_frame_size (), 0);} while (0)
+ ((NEW_REG) != 2 || df_regs_ever_live_p (2) || crtl->calls_eh_return)
/* Base register for access to arguments of the function. */
#define ARG_POINTER_REGNUM (TARGET_64BIT ? 29 : 3)
/* Function to return the rtx used to save the pic offset table register
across function calls. */
-extern struct rtx_def *hppa_pic_save_rtx (void);
+extern rtx hppa_pic_save_rtx (void);
#define DEFAULT_PCC_STRUCT_RETURN 0
is passed to a function. */
#define PA_STRUCT_VALUE_REGNUM 28
+/* Definitions for register eliminations.
+
+ We have two registers that can be eliminated. First, the frame pointer
+ register can often be eliminated in favor of the stack pointer register.
+ Secondly, the argument pointer register can always be eliminated in the
+ 32-bit runtimes. */
+
+/* This is an array of structures. Each structure initializes one pair
+ of eliminable registers. The "from" register number is given first,
+ followed by "to". Eliminations of the same "from" register are listed
+ in order of preference.
+
+ The argument pointer cannot be eliminated in the 64-bit runtime. It
+ is the same register as the hard frame pointer in the 32-bit runtime.
+ So, it does not need to be listed. */
+#define ELIMINABLE_REGS \
+{{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
+ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
+ { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
+
+/* Define the offset between two registers, one to be eliminated,
+ and the other its replacement, at the start of a routine. */
+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
+ ((OFFSET) = pa_initial_elimination_offset(FROM, TO))
+
/* Describe how we implement __builtin_eh_return. */
#define EH_RETURN_DATA_REGNO(N) \
((N) < 3 ? (N) + 20 : (N) == 3 ? 31 : INVALID_REGNUM)
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 29)
-#define EH_RETURN_HANDLER_RTX \
- gen_rtx_MEM (word_mode, \
- gen_rtx_PLUS (word_mode, frame_pointer_rtx, \
- TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20)))
+#define EH_RETURN_HANDLER_RTX pa_eh_return_handler_rtx ()
/* Offset from the frame pointer register value to the top of stack. */
#define FRAME_POINTER_CFA_OFFSET(FNDECL) 0
+/* The maximum number of hard registers that can be saved in the call
+ frame. The soft frame pointer is not included. */
+#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
+
/* A C expression whose value is RTL representing the location of the
incoming return address at the beginning of any function, before the
prologue. You only need to define this macro if you want to support
Column 0 is not used but unfortunately its register size is set to
4 bytes (sizeof CCmode) so it can't be used on 64-bit targets. */
-#define DWARF_ALT_FRAME_RETURN_COLUMN FIRST_PSEUDO_REGISTER
+#define DWARF_ALT_FRAME_RETURN_COLUMN (FIRST_PSEUDO_REGISTER - 1)
/* This macro chooses the encoding of pointers embedded in the exception
handling sections. If at all possible, this should be defined such
{ \
fputs (integer_asm_op (SIZE, FALSE), FILE); \
if ((ENCODING) & DW_EH_PE_indirect) \
- output_addr_const (FILE, get_deferred_plabel (ADDR)); \
+ output_addr_const (FILE, pa_get_deferred_plabel (ADDR)); \
else \
assemble_name (FILE, XSTR ((ADDR), 0)); \
fputs ("+8-$PIC_pcrel$0", FILE); \
/* True if register is floating-point. */
#define FP_REGNO_P(N) ((N) >= FP_REG_FIRST && (N) <= FP_REG_LAST)
-/* Given an rtx X being reloaded into a reg required to be
- in class CLASS, return the class of reg to actually use.
- In general this is just CLASS; but on some machines
- in some cases it is preferable to use a more restrictive class. */
-#define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
-
#define MAYBE_FP_REG_CLASS_P(CLASS) \
reg_classes_intersect_p ((CLASS), FP_REGS)
-/* On the PA it is not possible to directly move data between
- GENERAL_REGS and FP_REGS. On the 32-bit port, we use the
- location at SP-16. We don't expose this location in the RTL to
- avoid scheduling related problems. For example, the store and
- load could be separated by a call to a pure or const function
- which has no frame and uses SP-16. */
-#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
- (TARGET_64BIT \
- && (MAYBE_FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2) \
- || MAYBE_FP_REG_CLASS_P (CLASS2) != FP_REG_CLASS_P (CLASS1)))
-
\f
/* Stack layout; function entry, exit and calling. */
/* Define this if the above stack space is to be considered part of the
space allocated by the caller. */
-#define OUTGOING_REG_PARM_STACK_SPACE 1
+#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
/* Keep the stack pointer constant throughout the function.
This is both an optimization and a necessity: longjmp
marker, although the runtime documentation only describes a 16
byte marker. For compatibility, we allocate 48 bytes. */
#define STACK_POINTER_OFFSET \
- (TARGET_64BIT ? -(current_function_outgoing_args_size + 48): -32)
+ (TARGET_64BIT ? -(crtl->outgoing_args_size + 48): -32)
#define STACK_DYNAMIC_OFFSET(FNDECL) \
(TARGET_64BIT \
? (STACK_POINTER_OFFSET) \
- : ((STACK_POINTER_OFFSET) - current_function_outgoing_args_size))
-
-/* Value is 1 if returning from a function call automatically
- pops the arguments described by the number-of-args field in the call.
- FUNDECL is the declaration node of the function (as a tree),
- FUNTYPE is the data type of the function (as a tree),
- or for a library call it is an identifier node for the subroutine name. */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.
- VALTYPE is the data type of the value (as a tree).
- If the precise function being called is known, FUNC is its FUNCTION_DECL;
- otherwise, FUNC is 0. */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) function_value (VALTYPE, FUNC)
-
-/* Define how to find the value returned by a library function
- assuming the value has mode MODE. */
-
-#define LIBCALL_VALUE(MODE) \
- gen_rtx_REG (MODE, \
- (! TARGET_SOFT_FLOAT \
- && ((MODE) == SFmode || (MODE) == DFmode) ? 32 : 28))
-
-/* 1 if N is a possible register number for a function value
- as seen by the caller. */
-
-#define FUNCTION_VALUE_REGNO_P(N) \
- ((N) == 28 || (! TARGET_SOFT_FLOAT && (N) == 32))
+ : ((STACK_POINTER_OFFSET) - crtl->outgoing_args_size))
\f
/* Define a data type for recording info about an argument list
(CUM).words = 0, \
(CUM).incoming = 0, \
(CUM).indirect = (FNTYPE) && !(FNDECL), \
- (CUM).nargs_prototype = (FNTYPE && TYPE_ARG_TYPES (FNTYPE) \
+ (CUM).nargs_prototype = (FNTYPE && prototype_p (FNTYPE) \
? (list_length (TYPE_ARG_TYPES (FNTYPE)) - 1 \
+ (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
|| pa_return_in_memory (TREE_TYPE (FNTYPE), 0))) \
? (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
: int_size_in_bytes (TYPE)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-/* Update the data in CUM to advance over an argument
- of mode MODE and data type TYPE.
- (TYPE is null for libcalls where that information may not be available.) */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
-{ (CUM).nargs_prototype--; \
- (CUM).words += FUNCTION_ARG_SIZE(MODE, TYPE) \
- + (((CUM).words & 01) && (TYPE) != 0 \
- && FUNCTION_ARG_SIZE(MODE, TYPE) > 1); \
-}
-
/* Determine where to put an argument to a function.
Value is zero to push the argument on the stack,
or a hard register in which to store the argument.
/* If defined, a C expression which determines whether, and in which
direction, to pad out an argument with extra space. */
-#define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding ((MODE), (TYPE))
+#define FUNCTION_ARG_PADDING(MODE, TYPE) \
+ pa_function_arg_padding ((MODE), (TYPE))
/* Specify padding for the last element of a block move between registers
and memory.
so that there is only one element. This allows the object to be
correctly padded. */
#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
- function_arg_padding ((MODE), (TYPE))
-
-/* Do not expect to understand this without reading it several times. I'm
- tempted to try and simply it, but I worry about breaking something. */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
- function_arg (&CUM, MODE, TYPE, NAMED)
-
-/* If defined, a C expression that gives the alignment boundary, in
- bits, of an argument with the specified mode and type. If it is
- not defined, `PARM_BOUNDARY' is used for all arguments. */
-
-/* Arguments larger than one word are double word aligned. */
-
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
- (((TYPE) \
- ? (integer_zerop (TYPE_SIZE (TYPE)) \
- || !TREE_CONSTANT (TYPE_SIZE (TYPE)) \
- || int_size_in_bytes (TYPE) <= UNITS_PER_WORD) \
- : GET_MODE_SIZE(MODE) <= UNITS_PER_WORD) \
- ? PARM_BOUNDARY : MAX_PARM_BOUNDARY)
+ pa_function_arg_padding ((MODE), (TYPE))
\f
-extern GTY(()) rtx hppa_compare_op0;
-extern GTY(()) rtx hppa_compare_op1;
-extern enum cmp_type hppa_branch_type;
-
/* On HPPA, we emit profiling code as rtl via PROFILE_HOOK rather than
as assembly via FUNCTION_PROFILER. Just output a local label.
We can't use the function label because the GAS SOM target can't
#define EXIT_IGNORE_STACK \
(get_frame_size () != 0 \
- || current_function_calls_alloca || current_function_outgoing_args_size)
-
-/* Output assembler code for a block containing the constant parts
- of a trampoline, leaving space for the variable parts.\
-
- The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
- and then branches to the specified routine.
-
- This code template is copied from text segment to stack location
- and then patched with INITIALIZE_TRAMPOLINE to contain
- valid values, and then entered as a subroutine.
-
- It is best to keep this as small as possible to avoid having to
- flush multiple lines in the cache. */
-
-#define TRAMPOLINE_TEMPLATE(FILE) \
- { \
- if (!TARGET_64BIT) \
- { \
- fputs ("\tldw 36(%r22),%r21\n", FILE); \
- fputs ("\tbb,>=,n %r21,30,.+16\n", FILE); \
- if (ASSEMBLER_DIALECT == 0) \
- fputs ("\tdepi 0,31,2,%r21\n", FILE); \
- else \
- fputs ("\tdepwi 0,31,2,%r21\n", FILE); \
- fputs ("\tldw 4(%r21),%r19\n", FILE); \
- fputs ("\tldw 0(%r21),%r21\n", FILE); \
- if (TARGET_PA_20) \
- { \
- fputs ("\tbve (%r21)\n", FILE); \
- fputs ("\tldw 40(%r22),%r29\n", FILE); \
- fputs ("\t.word 0\n", FILE); \
- fputs ("\t.word 0\n", FILE); \
- } \
- else \
- { \
- fputs ("\tldsid (%r21),%r1\n", FILE); \
- fputs ("\tmtsp %r1,%sr0\n", FILE); \
- fputs ("\tbe 0(%sr0,%r21)\n", FILE); \
- fputs ("\tldw 40(%r22),%r29\n", FILE); \
- } \
- fputs ("\t.word 0\n", FILE); \
- fputs ("\t.word 0\n", FILE); \
- fputs ("\t.word 0\n", FILE); \
- fputs ("\t.word 0\n", FILE); \
- } \
- else \
- { \
- fputs ("\t.dword 0\n", FILE); \
- fputs ("\t.dword 0\n", FILE); \
- fputs ("\t.dword 0\n", FILE); \
- fputs ("\t.dword 0\n", FILE); \
- fputs ("\tmfia %r31\n", FILE); \
- fputs ("\tldd 24(%r31),%r1\n", FILE); \
- fputs ("\tldd 24(%r1),%r27\n", FILE); \
- fputs ("\tldd 16(%r1),%r1\n", FILE); \
- fputs ("\tbve (%r1)\n", FILE); \
- fputs ("\tldd 32(%r31),%r31\n", FILE); \
- fputs ("\t.dword 0 ; fptr\n", FILE); \
- fputs ("\t.dword 0 ; static link\n", FILE); \
- } \
- }
+ || cfun->calls_alloca || crtl->outgoing_args_size)
/* Length in units of the trampoline for entering a nested function. */
#define TRAMPOLINE_SIZE (TARGET_64BIT ? 72 : 52)
-/* Length in units of the trampoline instruction code. */
+/* Alignment required by the trampoline. */
-#define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40))
+#define TRAMPOLINE_ALIGNMENT BITS_PER_WORD
/* Minimum length of a cache line. A length of 16 will work on all
PA-RISC processors. All PA 1.1 processors have a cache line of
#define MIN_CACHELINE_SIZE 32
-/* Emit RTL insns to initialize the variable parts of a trampoline.
- FNADDR is an RTX for the address of the function's pure code.
- CXT is an RTX for the static chain value for the function.
-
- Move the function address to the trampoline template at offset 36.
- Move the static chain value to trampoline template at offset 40.
- Move the trampoline address to trampoline template at offset 44.
- Move r19 to trampoline template at offset 48. The latter two
- words create a plabel for the indirect call to the trampoline.
-
- A similar sequence is used for the 64-bit port but the plabel is
- at the beginning of the trampoline.
-
- Finally, the cache entries for the trampoline code are flushed.
- This is necessary to ensure that the trampoline instruction sequence
- is written to memory prior to any attempts at prefetching the code
- sequence. */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
-{ \
- rtx start_addr = gen_reg_rtx (Pmode); \
- rtx end_addr = gen_reg_rtx (Pmode); \
- rtx line_length = gen_reg_rtx (Pmode); \
- rtx tmp; \
- \
- if (!TARGET_64BIT) \
- { \
- tmp = memory_address (Pmode, plus_constant ((TRAMP), 36)); \
- emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \
- tmp = memory_address (Pmode, plus_constant ((TRAMP), 40)); \
- emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \
- \
- /* Create a fat pointer for the trampoline. */ \
- tmp = memory_address (Pmode, plus_constant ((TRAMP), 44)); \
- emit_move_insn (gen_rtx_MEM (Pmode, tmp), (TRAMP)); \
- tmp = memory_address (Pmode, plus_constant ((TRAMP), 48)); \
- emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
- gen_rtx_REG (Pmode, 19)); \
- \
- /* fdc and fic only use registers for the address to flush, \
- they do not accept integer displacements. We align the \
- start and end addresses to the beginning of their respective \
- cache lines to minimize the number of lines flushed. */ \
- tmp = force_reg (Pmode, (TRAMP)); \
- emit_insn (gen_andsi3 (start_addr, tmp, \
- GEN_INT (-MIN_CACHELINE_SIZE))); \
- tmp = force_reg (Pmode, \
- plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \
- emit_insn (gen_andsi3 (end_addr, tmp, \
- GEN_INT (-MIN_CACHELINE_SIZE))); \
- emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
- emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
- emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
- gen_reg_rtx (Pmode), \
- gen_reg_rtx (Pmode))); \
- } \
- else \
- { \
- tmp = memory_address (Pmode, plus_constant ((TRAMP), 56)); \
- emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \
- tmp = memory_address (Pmode, plus_constant ((TRAMP), 64)); \
- emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \
- \
- /* Create a fat pointer for the trampoline. */ \
- tmp = memory_address (Pmode, plus_constant ((TRAMP), 16)); \
- emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
- force_reg (Pmode, plus_constant ((TRAMP), 32))); \
- tmp = memory_address (Pmode, plus_constant ((TRAMP), 24)); \
- emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
- gen_rtx_REG (Pmode, 27)); \
- \
- /* fdc and fic only use registers for the address to flush, \
- they do not accept integer displacements. We align the \
- start and end addresses to the beginning of their respective \
- cache lines to minimize the number of lines flushed. */ \
- tmp = force_reg (Pmode, plus_constant ((TRAMP), 32)); \
- emit_insn (gen_anddi3 (start_addr, tmp, \
- GEN_INT (-MIN_CACHELINE_SIZE))); \
- tmp = force_reg (Pmode, \
- plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \
- emit_insn (gen_anddi3 (end_addr, tmp, \
- GEN_INT (-MIN_CACHELINE_SIZE))); \
- emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
- emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
- emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
- gen_reg_rtx (Pmode), \
- gen_reg_rtx (Pmode))); \
- } \
-}
-
-/* Perform any machine-specific adjustment in the address of the trampoline.
- ADDR contains the address that was passed to INITIALIZE_TRAMPOLINE.
- Adjust the trampoline address to point to the plabel at offset 44. */
-
-#define TRAMPOLINE_ADJUST_ADDRESS(ADDR) \
- if (!TARGET_64BIT) (ADDR) = memory_address (Pmode, plus_constant ((ADDR), 46))
-
-/* Implement `va_start' for varargs and stdarg. */
-
-#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
- hppa_va_start (valist, nextarg)
\f
/* Addressing modes, and classification of registers for them.
They give nonzero only if X is a hard reg of the suitable class
or a pseudo reg currently allocated to a suitable hard reg.
Since they use reg_renumber, they are safe only once reg_renumber
- has been allocated, which happens in local-alloc.c. */
+ has been allocated, which happens in reginfo.c during register
+ allocation. */
#define REGNO_OK_FOR_INDEX_P(X) \
((X) && ((X) < 32 \
- || (X >= FIRST_PSEUDO_REGISTER \
+ || ((X) == FRAME_POINTER_REGNUM) \
+ || ((X) >= FIRST_PSEUDO_REGISTER \
&& reg_renumber \
&& (unsigned) reg_renumber[X] < 32)))
#define REGNO_OK_FOR_BASE_P(X) \
((X) && ((X) < 32 \
- || (X >= FIRST_PSEUDO_REGISTER \
+ || ((X) == FRAME_POINTER_REGNUM) \
+ || ((X) >= FIRST_PSEUDO_REGISTER \
&& reg_renumber \
&& (unsigned) reg_renumber[X] < 32)))
#define REGNO_OK_FOR_FP_P(X) \
#define MAX_REGS_PER_ADDRESS 2
-/* Non-TLS symbolic references. */
-#define PA_SYMBOL_REF_TLS_P(RTX) \
- (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
+/* TLS symbolic reference. */
+#define PA_SYMBOL_REF_TLS_P(X) \
+ (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (X) != 0)
/* Recognize any constant value that is a valid address except
for symbolic addresses. We get better CSE by rejecting them
#define CONSTANT_ADDRESS_P(X) \
((GET_CODE (X) == LABEL_REF \
|| (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X)) \
- || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
+ || GET_CODE (X) == CONST_INT \
+ || (GET_CODE (X) == CONST && !tls_referenced_p (X)) \
|| GET_CODE (X) == HIGH) \
- && (reload_in_progress || reload_completed || ! symbolic_expression_p (X)))
+ && (reload_in_progress || reload_completed \
+ || ! pa_symbolic_expression_p (X)))
/* A C expression that is nonzero if we are using the new HP assembler. */
#define LEGITIMATE_64BIT_CONST_INT_P(X) \
((X) >= MIN_LEGIT_64BIT_CONST_INT && (X) < MAX_LEGIT_64BIT_CONST_INT)
-/* A C expression that is nonzero if X is a legitimate constant for an
- immediate operand.
-
- We include all constant integers and constant doubles, but not
- floating-point, except for floating-point zero. We reject LABEL_REFs
- if we're not using gas or the new HP assembler.
-
- In 64-bit mode, we reject CONST_DOUBLES. We also reject CONST_INTS
- that need more than three instructions to load prior to reload. This
- limit is somewhat arbitrary. It takes three instructions to load a
- CONST_INT from memory but two are memory accesses. It may be better
- to increase the allowed range for CONST_INTS. We may also be able
- to handle CONST_DOUBLES. */
-
-#define LEGITIMATE_CONSTANT_P(X) \
- ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
- || (X) == CONST0_RTX (GET_MODE (X))) \
- && (NEW_HP_ASSEMBLER \
- || TARGET_GAS \
- || GET_CODE (X) != LABEL_REF) \
- && (!TARGET_64BIT \
- || GET_CODE (X) != CONST_DOUBLE) \
- && (!TARGET_64BIT \
- || HOST_BITS_PER_WIDE_INT <= 32 \
- || GET_CODE (X) != CONST_INT \
- || reload_in_progress \
- || reload_completed \
- || LEGITIMATE_64BIT_CONST_INT_P (INTVAL (X)) \
- || cint_ok_for_move (INTVAL (X))) \
- && !function_label_operand (X, VOIDmode))
-
/* Target flags set on a symbol_ref. */
/* Set by ASM_OUTPUT_SYMBOL_REF when a symbol_ref is output. */
&& REG_OK_FOR_BASE_P (XEXP (OP, 0)) \
&& GET_CODE (XEXP (OP, 1)) == UNSPEC)
+/* Nonzero if 14-bit offsets can be used for all loads and stores.
+ This is not possible when generating PA 1.x code as floating point
+ loads and stores only support 5-bit offsets. Note that we do not
+ forbid the use of 14-bit offsets for integer modes. Instead, we
+ use secondary reloads to fix REG+D memory addresses for integer
+ mode floating-point loads and stores.
+
+ FIXME: the ELF32 linker clobbers the LSB of the FP register number
+ in PA 2.0 floating-point insns with long displacements. This is
+ because R_PARISC_DPREL14WR and other relocations like it are not
+ yet supported by GNU ld. For now, we reject long displacements
+ on this target. */
+
+#define INT14_OK_STRICT \
+ (TARGET_SOFT_FLOAT \
+ || TARGET_DISABLE_FPREGS \
+ || (TARGET_PA_20 && !TARGET_ELF32))
+
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
and check its validity for a certain class.
We have two alternate definitions for each of them.
The usual definition accepts all pseudo regs; the other rejects
them unless they have been allocated suitable hard regs.
- The symbol REG_OK_STRICT causes the latter definition to be used.
Most source files want to accept pseudo regs in the hope that
they will get allocated to the class that the insn wants them to be in.
After reload, it makes no difference, since pseudo regs have
been eliminated by then. */
-#ifndef REG_OK_STRICT
-
/* Nonzero if X is a hard reg that can be used as an index
or if it is a pseudo reg. */
#define REG_OK_FOR_INDEX_P(X) \
-(REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
+ (REGNO (X) && (REGNO (X) < 32 \
+ || REGNO (X) == FRAME_POINTER_REGNUM \
+ || REGNO (X) >= FIRST_PSEUDO_REGISTER))
+
/* Nonzero if X is a hard reg that can be used as a base reg
or if it is a pseudo reg. */
#define REG_OK_FOR_BASE_P(X) \
-(REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
-
-#else
+ (REGNO (X) && (REGNO (X) < 32 \
+ || REGNO (X) == FRAME_POINTER_REGNUM \
+ || REGNO (X) >= FIRST_PSEUDO_REGISTER))
/* Nonzero if X is a hard reg that can be used as an index. */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg. */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
+#define STRICT_REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-#endif
-\f
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
- valid memory address for an instruction. The MODE argument is the
- machine mode for the MEM expression that wants to use this address.
-
- On HP PA-RISC, the legitimate address forms are REG+SMALLINT,
- REG+REG, and REG+(REG*SCALE). The indexed address forms are only
- available with floating point loads and stores, and integer loads.
- We get better code by allowing indexed addresses in the initial
- RTL generation.
-
- The acceptance of indexed addresses as legitimate implies that we
- must provide patterns for doing indexed integer stores, or the move
- expanders must force the address of an indexed store to a register.
- We have adopted the latter approach.
-
- Another function of GO_IF_LEGITIMATE_ADDRESS is to ensure that
- the base register is a valid pointer for indexed instructions.
- On targets that have non-equivalent space registers, we have to
- know at the time of assembler output which register in a REG+REG
- pair is the base register. The REG_POINTER flag is sometimes lost
- in reload and the following passes, so it can't be relied on during
- code generation. Thus, we either have to canonicalize the order
- of the registers in REG+REG indexed addresses, or treat REG+REG
- addresses separately and provide patterns for both permutations.
-
- The latter approach requires several hundred additional lines of
- code in pa.md. The downside to canonicalizing is that a PLUS
- in the wrong order can't combine to form to make a scaled indexed
- memory operand. As we won't need to canonicalize the operands if
- the REG_POINTER lossage can be fixed, it seems better canonicalize.
-
- We initially break out scaled indexed addresses in canonical order
- in emit_move_sequence. LEGITIMIZE_ADDRESS also canonicalizes
- scaled indexed addresses during RTL generation. However, fold_rtx
- has its own opinion on how the operands of a PLUS should be ordered.
- If one of the operands is equivalent to a constant, it will make
- that operand the second operand. As the base register is likely to
- be equivalent to a SYMBOL_REF, we have made it the second operand.
-
- GO_IF_LEGITIMATE_ADDRESS accepts REG+REG as legitimate when the
- operands are in the order INDEX+BASE on targets with non-equivalent
- space registers, and in any order on targets with equivalent space
- registers. It accepts both MULT+BASE and BASE+MULT for scaled indexing.
-
- We treat a SYMBOL_REF as legitimate if it is part of the current
- function's constant-pool, because such addresses can actually be
- output as REG+SMALLINT.
-
- Note we only allow 5-bit immediates for access to a constant address;
- doing so avoids losing for loading/storing a FP register at an address
- which will not fit in 5 bits. */
+/* Nonzero if X is a hard reg that can be used as a base reg. */
+#define STRICT_REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
#define VAL_5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x10 < 0x20)
#define INT_5_BITS(X) VAL_5_BITS_P (INTVAL (X))
#define VAL_U5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x20)
#define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X))
+#define VAL_U6_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x40)
+#define INT_U6_BITS(X) VAL_U6_BITS_P (INTVAL (X))
+
#define VAL_11_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x400 < 0x800)
#define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X))
((TARGET_64BIT && (MODE) == DImode) \
|| (MODE) == SImode \
|| (MODE) == HImode \
- || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode)))
+ || (MODE) == SFmode \
+ || (MODE) == DFmode)
/* These are the modes that we allow for unscaled indexing. */
#define MODE_OK_FOR_UNSCALED_INDEXING_P(MODE) \
|| (MODE) == SImode \
|| (MODE) == HImode \
|| (MODE) == QImode \
- || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode)))
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
-{ \
- if ((REG_P (X) && REG_OK_FOR_BASE_P (X)) \
- || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC \
- || GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC) \
- && REG_P (XEXP (X, 0)) \
- && REG_OK_FOR_BASE_P (XEXP (X, 0)))) \
- goto ADDR; \
- else if (GET_CODE (X) == PLUS) \
- { \
- rtx base = 0, index = 0; \
- if (REG_P (XEXP (X, 1)) \
- && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
- base = XEXP (X, 1), index = XEXP (X, 0); \
- else if (REG_P (XEXP (X, 0)) \
- && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
- base = XEXP (X, 0), index = XEXP (X, 1); \
- if (base \
- && GET_CODE (index) == CONST_INT \
- && ((INT_14_BITS (index) \
- && (((MODE) != DImode \
- && (MODE) != SFmode \
- && (MODE) != DFmode) \
- /* The base register for DImode loads and stores \
- with long displacements must be aligned because \
- the lower three bits in the displacement are \
- assumed to be zero. */ \
- || ((MODE) == DImode \
- && (!TARGET_64BIT \
- || (INTVAL (index) % 8) == 0)) \
- /* Similarly, the base register for SFmode/DFmode \
- loads and stores with long displacements must \
- be aligned. \
- \
- FIXME: the ELF32 linker clobbers the LSB of \
- the FP register number in PA 2.0 floating-point \
- insns with long displacements. This is because \
- R_PARISC_DPREL14WR and other relocations like \
- it are not supported. For now, we reject long \
- displacements on this target. */ \
- || (((MODE) == SFmode || (MODE) == DFmode) \
- && (TARGET_SOFT_FLOAT \
- || (TARGET_PA_20 \
- && !TARGET_ELF32 \
- && (INTVAL (index) \
- % GET_MODE_SIZE (MODE)) == 0))))) \
- || INT_5_BITS (index))) \
- goto ADDR; \
- if (!TARGET_DISABLE_INDEXING \
- /* Only accept the "canonical" INDEX+BASE operand order \
- on targets with non-equivalent space registers. */ \
- && (TARGET_NO_SPACE_REGS \
- ? (base && REG_P (index)) \
- : (base == XEXP (X, 1) && REG_P (index) \
- && (reload_completed \
- || (reload_in_progress && HARD_REGISTER_P (base)) \
- || REG_POINTER (base)) \
- && (reload_completed \
- || (reload_in_progress && HARD_REGISTER_P (index)) \
- || !REG_POINTER (index)))) \
- && MODE_OK_FOR_UNSCALED_INDEXING_P (MODE) \
- && REG_OK_FOR_INDEX_P (index) \
- && borx_reg_operand (base, Pmode) \
- && borx_reg_operand (index, Pmode)) \
- goto ADDR; \
- if (!TARGET_DISABLE_INDEXING \
- && base \
- && GET_CODE (index) == MULT \
- && MODE_OK_FOR_SCALED_INDEXING_P (MODE) \
- && REG_P (XEXP (index, 0)) \
- && GET_MODE (XEXP (index, 0)) == Pmode \
- && REG_OK_FOR_INDEX_P (XEXP (index, 0)) \
- && GET_CODE (XEXP (index, 1)) == CONST_INT \
- && INTVAL (XEXP (index, 1)) \
- == (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
- && borx_reg_operand (base, Pmode)) \
- goto ADDR; \
- } \
- else if (GET_CODE (X) == LO_SUM \
- && GET_CODE (XEXP (X, 0)) == REG \
- && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
- && CONSTANT_P (XEXP (X, 1)) \
- && (TARGET_SOFT_FLOAT \
- /* We can allow symbolic LO_SUM addresses for PA2.0. */ \
- || (TARGET_PA_20 \
- && !TARGET_ELF32 \
- && GET_CODE (XEXP (X, 1)) != CONST_INT) \
- || ((MODE) != SFmode \
- && (MODE) != DFmode))) \
- goto ADDR; \
- else if (GET_CODE (X) == LO_SUM \
- && GET_CODE (XEXP (X, 0)) == SUBREG \
- && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG \
- && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0))) \
- && CONSTANT_P (XEXP (X, 1)) \
- && (TARGET_SOFT_FLOAT \
- /* We can allow symbolic LO_SUM addresses for PA2.0. */ \
- || (TARGET_PA_20 \
- && !TARGET_ELF32 \
- && GET_CODE (XEXP (X, 1)) != CONST_INT) \
- || ((MODE) != SFmode \
- && (MODE) != DFmode))) \
- goto ADDR; \
- else if (GET_CODE (X) == LABEL_REF \
- || (GET_CODE (X) == CONST_INT \
- && INT_5_BITS (X))) \
- goto ADDR; \
- /* Needed for -fPIC */ \
- else if (GET_CODE (X) == LO_SUM \
- && GET_CODE (XEXP (X, 0)) == REG \
- && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
- && GET_CODE (XEXP (X, 1)) == UNSPEC \
- && (TARGET_SOFT_FLOAT \
- || (TARGET_PA_20 && !TARGET_ELF32) \
- || ((MODE) != SFmode \
- && (MODE) != DFmode))) \
- goto ADDR; \
-}
-
-/* Look for machine dependent ways to make the invalid address AD a
- valid address.
-
- For the PA, transform:
-
- memory(X + <large int>)
-
- into:
-
- if (<large int> & mask) >= 16
- Y = (<large int> & ~mask) + mask + 1 Round up.
- else
- Y = (<large int> & ~mask) Round down.
- Z = X + Y
- memory (Z + (<large int> - Y));
-
- This makes reload inheritance and reload_cse work better since Z
- can be reused.
-
- There may be more opportunities to improve code with this hook. */
-#define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \
-do { \
- long offset, newoffset, mask; \
- rtx new, temp = NULL_RTX; \
- \
- mask = (GET_MODE_CLASS (MODE) == MODE_FLOAT \
- ? (TARGET_PA_20 && !TARGET_ELF32 ? 0x3fff : 0x1f) : 0x3fff); \
- \
- if (optimize && GET_CODE (AD) == PLUS) \
- temp = simplify_binary_operation (PLUS, Pmode, \
- XEXP (AD, 0), XEXP (AD, 1)); \
- \
- new = temp ? temp : AD; \
- \
- if (optimize \
- && GET_CODE (new) == PLUS \
- && GET_CODE (XEXP (new, 0)) == REG \
- && GET_CODE (XEXP (new, 1)) == CONST_INT) \
- { \
- offset = INTVAL (XEXP ((new), 1)); \
- \
- /* Choose rounding direction. Round up if we are >= halfway. */ \
- if ((offset & mask) >= ((mask + 1) / 2)) \
- newoffset = (offset & ~mask) + mask + 1; \
- else \
- newoffset = offset & ~mask; \
- \
- /* Ensure that long displacements are aligned. */ \
- if (!VAL_5_BITS_P (newoffset) \
- && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
- newoffset &= ~(GET_MODE_SIZE (MODE) -1); \
- \
- if (newoffset != 0 && VAL_14_BITS_P (newoffset)) \
- { \
- temp = gen_rtx_PLUS (Pmode, XEXP (new, 0), \
- GEN_INT (newoffset)); \
- AD = gen_rtx_PLUS (Pmode, temp, GEN_INT (offset - newoffset));\
- push_reload (XEXP (AD, 0), 0, &XEXP (AD, 0), 0, \
- BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, \
- (OPNUM), (TYPE)); \
- goto WIN; \
- } \
- } \
+ || (MODE) == SFmode \
+ || (MODE) == DFmode)
+
+/* Try a machine-dependent way of reloading an illegitimate address
+ operand. If we find one, push the reload and jump to WIN. This
+ macro is used in only one place: `find_reloads_address' in reload.c. */
+
+#define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND_L, WIN) \
+do { \
+ rtx new_ad = pa_legitimize_reload_address (AD, MODE, OPNUM, TYPE, IND_L); \
+ if (new_ad) \
+ { \
+ AD = new_ad; \
+ goto WIN; \
+ } \
} while (0)
-
-
-\f
-/* Try machine-dependent ways of modifying an illegitimate address
- to be legitimate. If we find one, return the new, valid address.
- This macro is used in only one place: `memory_address' in explow.c.
-
- OLDX is the address as it was before break_out_memory_refs was called.
- In some cases it is useful to look at this to decide what needs to be done.
-
- MODE and WIN are passed so that this macro can use
- GO_IF_LEGITIMATE_ADDRESS.
-
- It is always safe for this macro to do nothing. It exists to recognize
- opportunities to optimize the output. */
-
-#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
-{ rtx orig_x = (X); \
- (X) = hppa_legitimize_address (X, OLDX, MODE); \
- if ((X) != orig_x && memory_address_p (MODE, X)) \
- goto WIN; }
-
-/* Go to LABEL if ADDR (a legitimate address expression)
- has an effect that depends on the machine mode it is used for. */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
\f
#define TARGET_ASM_SELECT_SECTION pa_select_section
/* Return a nonzero value if DECL has a section attribute. */
#define IN_NAMED_SECTION_P(DECL) \
((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
- && DECL_SECTION_NAME (DECL) != NULL_TREE)
+ && DECL_SECTION_NAME (DECL) != NULL)
/* Define this macro if references to a symbol must be treated
differently depending on something about the variable or
(TREE_CODE (DECL) == FUNCTION_DECL \
|| (TREE_CODE (DECL) == VAR_DECL \
&& TREE_READONLY (DECL) && ! TREE_SIDE_EFFECTS (DECL) \
- && (! DECL_INITIAL (DECL) || ! reloc_needed (DECL_INITIAL (DECL))) \
+ && (! DECL_INITIAL (DECL) || ! pa_reloc_needed (DECL_INITIAL (DECL))) \
&& !flag_pic) \
|| CONSTANT_CLASS_P (DECL))
#define FUNCTION_NAME_P(NAME) (*(NAME) == '@')
/* Specify the machine mode that this machine uses for the index in the
- tablejump instruction. For small tables, an element consists of a
- ia-relative branch and its delay slot. When -mbig-switch is specified,
- we use a 32-bit absolute address for non-pic code, and a 32-bit offset
- for both 32 and 64-bit pic code. */
-#define CASE_VECTOR_MODE (TARGET_BIG_SWITCH ? SImode : DImode)
+ tablejump instruction. We use a 32-bit absolute address for non-pic code,
+ and a 32-bit offset for 32 and 64-bit pic code. */
+#define CASE_VECTOR_MODE SImode
/* Jump tables must be 32-bit aligned, no matter the size of the element. */
#define ADDR_VEC_ALIGN(ADDR_VEC) 2
arguments passed in registers to avoid infinite recursion during argument
setup for a function call. Why? Consider how we copy the stack slots
reserved for parameters when they may be trashed by a call. */
-#define MOVE_RATIO (TARGET_64BIT ? 8 : 4)
+#define MOVE_RATIO(speed) (TARGET_64BIT ? 8 : 4)
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
few bits. */
#define SHIFT_COUNT_TRUNCATED 1
-/* Compute extra cost of moving data between one register class
- and another.
-
- Make moves from SAR so expensive they should never happen. We used to
- have 0xffff here, but that generates overflow in rare cases.
-
- Copies involving a FP register and a non-FP register are relatively
- expensive because they must go through memory.
-
- Other copies are reasonably cheap. */
-#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
- (CLASS1 == SHIFT_REGS ? 0x100 \
- : FP_REG_CLASS_P (CLASS1) && ! FP_REG_CLASS_P (CLASS2) ? 16 \
- : FP_REG_CLASS_P (CLASS2) && ! FP_REG_CLASS_P (CLASS1) ? 16 \
- : 2)
-
/* Adjust the cost of branches. */
-#define BRANCH_COST (pa_cpu == PROCESSOR_8000 ? 2 : 1)
+#define BRANCH_COST(speed_p, predictable_p) (pa_cpu == PROCESSOR_8000 ? 2 : 1)
/* Handling the special cases is going to get too complicated for a macro,
just call `pa_adjust_insn_length' to do the real work. */
-#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
- LENGTH += pa_adjust_insn_length (INSN, LENGTH);
+#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
+ ((LENGTH) = pa_adjust_insn_length ((INSN), (LENGTH)))
/* Millicode insns are actually function calls with some special
constraints on arguments and register usage.
get_attr_type will try to recognize the given insn, so make sure to
filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
in particular. */
-#define INSN_REFERENCES_ARE_DELAYED(X) (insn_refs_are_delayed (X))
+#define INSN_REFERENCES_ARE_DELAYED(X) (pa_insn_refs_are_delayed (X))
\f
/* Control the assembler format that we output. */
#define TARGET_ASM_GLOBALIZE_LABEL pa_globalize_label
#define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
- output_ascii ((FILE), (P), (SIZE))
+ pa_output_ascii ((FILE), (P), (SIZE))
/* Jump tables are always placed in the text section. Technically, it
- is possible to put them in the readonly data section when -mbig-switch
- is specified. This has the benefit of getting the table out of .text
- and reducing branch lengths as a result. The downside is that an
- additional insn (addil) is needed to access the table when generating
- PIC code. The address difference table also has to use 32-bit
- pc-relative relocations. Currently, GAS does not support these
- relocations, although it is easily modified to do this operation.
+ is possible to put them in the readonly data section. This has the
+ benefit of getting the table out of .text and reducing branch lengths
+ as a result.
+
+ The downside is that an additional insn (addil) is needed to access
+ the table when generating PIC code. The address difference table
+ also has to use 32-bit pc-relative relocations. Currently, GAS does
+ not support these relocations, although it is easily modified to do
+ this operation.
+
The table entries need to look like "$L1+(.+8-$L0)-$PIC_pcrel$0"
when using ELF GAS. A simple difference can be used when using
SOM GAS or the HP assembler. The final downside is GDB complains
/* This is how to output an element of a case-vector that is absolute. */
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
- if (TARGET_BIG_SWITCH) \
- fprintf (FILE, "\t.word L$%04d\n", VALUE); \
- else \
- fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
+ fprintf (FILE, "\t.word L$%04d\n", VALUE)
/* This is how to output an element of a case-vector that is relative.
Since we always place jump tables in the text section, the difference
is absolute and requires no relocation. */
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
- if (TARGET_BIG_SWITCH) \
- fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL); \
- else \
- fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
+ fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL)
/* This is how to output an assembler line that says to advance the
location counter to a multiple of 2**LOG bytes. */
#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
pa_asm_output_aligned_local (FILE, NAME, SIZE, ALIGN)
-
-#define ASM_PN_FORMAT "%s___%lu"
-
/* All HP assemblers use "!" to separate logical lines. */
-#define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == '!')
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
- ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^')
+#define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == '!')
/* Print operand X (an rtx) in assembler syntax to file FILE.
CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
M modifier to handle preincrement addressing for memory refs.
F modifier to handle preincrement addressing for fp memory refs */
-#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
+#define PRINT_OPERAND(FILE, X, CODE) pa_print_operand (FILE, X, CODE)
\f
/* Print a memory address as an operand to reference that memory location. */
fputs ("RR'", FILE); \
else \
fputs ("RT'", FILE); \
- output_global_address (FILE, XEXP (addr, 1), 0); \
+ pa_output_global_address (FILE, XEXP (addr, 1), 0); \
fputs ("(", FILE); \
output_operand (XEXP (addr, 0), 0); \
fputs (")", FILE); \
/* Find the return address associated with the frame given by
FRAMEADDR. */
#define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
- (return_addr_rtx (COUNT, FRAMEADDR))
+ (pa_return_addr_rtx (COUNT, FRAMEADDR))
/* Used to mask out junk bits from the return address, such as
processor state, interrupt status, condition codes and the like. */
of the return address. */ \
(GEN_INT (-4))
-/* The number of Pmode words for the setjmp buffer. */
-#define JMP_BUF_SIZE 50
-
/* We need a libcall to canonicalize function pointers on TARGET_ELF32. */
#define CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL \
"__canonicalize_funcptr_for_compare"
#undef TARGET_HAVE_TLS
#define TARGET_HAVE_TLS true
#endif
+
+/* The maximum offset in bytes for a PA 1.X pc-relative call to the
+ head of the preceding stub table. The selected offsets have been
+ chosen so that approximately one call stub is allocated for every
+ 86.7 instructions. A long branch stub is two instructions when
+ not generating PIC code. For HP-UX and ELF targets, PIC stubs are
+ seven and four instructions, respectively. */
+#define MAX_PCREL17F_OFFSET \
+ (flag_pic ? (TARGET_HPUX ? 198164 : 221312) : 240000)
projects / platform / upstream / gcc.git / blobdiff