/* Subroutines used for MIPS code generation.
- Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
- 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
- Free Software Foundation, Inc.
+ Copyright (C) 1989-2014 Free Software Foundation, Inc.
Contributed by A. Lichnewsky, lich@inria.inria.fr.
Changes by Michael Meissner, meissner@osf.org.
64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
#include "recog.h"
#include "output.h"
#include "tree.h"
+#include "varasm.h"
+#include "stringpool.h"
+#include "stor-layout.h"
+#include "calls.h"
#include "function.h"
#include "expr.h"
#include "optabs.h"
#include "tm_p.h"
#include "ggc.h"
#include "gstab.h"
-#include "hashtab.h"
+#include "hash-table.h"
#include "debug.h"
#include "target.h"
#include "target-def.h"
-#include "integrate.h"
+#include "common/common-target.h"
#include "langhooks.h"
-#include "cfglayout.h"
#include "sched-int.h"
+#include "vec.h"
+#include "basic-block.h"
+#include "tree-ssa-alias.h"
+#include "internal-fn.h"
+#include "gimple-fold.h"
+#include "tree-eh.h"
+#include "gimple-expr.h"
+#include "is-a.h"
#include "gimple.h"
+#include "gimplify.h"
#include "bitmap.h"
#include "diagnostic.h"
#include "target-globals.h"
+#include "opts.h"
+#include "tree-pass.h"
+#include "context.h"
+#include "cgraph.h"
+#include "builtins.h"
/* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
#define UNSPEC_ADDRESS_P(X) \
preserve the maximum stack alignment. We therefore use a value
of 0x7ff0 in this case.
+ microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
+ so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
+
MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
up to 0x7f8 bytes and can usually save or restore all the registers
that we need to save or restore. (Note that we can only use these
to save and restore registers, and to allocate and deallocate the top
part of the frame. */
#define MIPS_MAX_FIRST_STACK_STEP \
- (!TARGET_MIPS16 ? 0x7ff0 \
- : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
+ (!TARGET_COMPRESSION ? 0x7ff0 \
+ : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
: TARGET_64BIT ? 0x100 : 0x400)
/* True if INSN is a mips.md pattern or asm statement. */
+/* ??? This test exists through the compiler, perhaps it should be
+ moved to rtl.h. */
#define USEFUL_INSN_P(INSN) \
(NONDEBUG_INSN_P (INSN) \
&& GET_CODE (PATTERN (INSN)) != USE \
- && GET_CODE (PATTERN (INSN)) != CLOBBER \
- && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
- && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
+ && GET_CODE (PATTERN (INSN)) != CLOBBER)
/* If INSN is a delayed branch sequence, return the first instruction
in the sequence, otherwise return INSN itself. */
#define SEQ_BEGIN(INSN) \
(INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
- ? XVECEXP (PATTERN (INSN), 0, 0) \
+ ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), 0, 0)) \
: (INSN))
/* Likewise for the last instruction in a delayed branch sequence. */
#define SEQ_END(INSN) \
(INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
- ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
+ ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), \
+ 0, \
+ XVECLEN (PATTERN (INSN), 0) - 1)) \
: (INSN))
/* Execute the following loop body with SUBINSN set to each instruction
ADDRESS_SYMBOLIC
};
-/* Enumerates the setting of the -mr10k-cache-barrier option. */
-enum mips_r10k_cache_barrier_setting {
- R10K_CACHE_BARRIER_NONE,
- R10K_CACHE_BARRIER_STORE,
- R10K_CACHE_BARRIER_LOAD_STORE
-};
-
/* Macros to create an enumeration identifier for a function prototype. */
#define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
#define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
enum mips_fp_condition {
MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
};
+#undef DECLARE_MIPS_COND
/* Index X provides the string representation of MIPS_FP_COND_<X>. */
#define STRINGIFY(X) #X
static const char *const mips_fp_conditions[] = {
MIPS_FP_CONDITIONS (STRINGIFY)
};
+#undef STRINGIFY
+
+/* A class used to control a comdat-style stub that we output in each
+ translation unit that needs it. */
+class mips_one_only_stub {
+public:
+ virtual ~mips_one_only_stub () {}
+
+ /* Return the name of the stub. */
+ virtual const char *get_name () = 0;
+
+ /* Output the body of the function to asm_out_file. */
+ virtual void output_body () = 0;
+};
+
+/* Tuning information that is automatically derived from other sources
+ (such as the scheduler). */
+static struct {
+ /* The architecture and tuning settings that this structure describes. */
+ enum processor arch;
+ enum processor tune;
+
+ /* True if this structure describes MIPS16 settings. */
+ bool mips16_p;
+
+ /* True if the structure has been initialized. */
+ bool initialized_p;
+
+ /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
+ when optimizing for speed. */
+ bool fast_mult_zero_zero_p;
+} mips_tuning_info;
/* Information about a function's frame layout. */
struct GTY(()) mips_frame_info {
};
struct GTY(()) machine_function {
+ /* The next floating-point condition-code register to allocate
+ for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
+ unsigned int next_fcc;
+
/* The register returned by mips16_gp_pseudo_reg; see there for details. */
rtx mips16_gp_pseudo_rtx;
written anything yet. */
const char *current_function_file = "";
-/* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
-int sdb_label_count;
-
/* Arrays that map GCC register numbers to debugger register numbers. */
int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
+/* Information about the current function's epilogue, used only while
+ expanding it. */
+static struct {
+ /* A list of queued REG_CFA_RESTORE notes. */
+ rtx cfa_restores;
+
+ /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
+ rtx cfa_reg;
+ HOST_WIDE_INT cfa_offset;
+
+ /* The offset of the CFA from the stack pointer while restoring
+ registers. */
+ HOST_WIDE_INT cfa_restore_sp_offset;
+} mips_epilogue;
+
/* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
struct mips_asm_switch mips_noreorder = { "reorder", 0 };
struct mips_asm_switch mips_nomacro = { "macro", 0 };
/* The ISA level associated with mips_arch. */
int mips_isa;
+/* The ISA revision level. This is 0 for MIPS I to V and N for
+ MIPS{32,64}rN. */
+int mips_isa_rev;
+
/* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
static const struct mips_cpu_info *mips_isa_option_info;
-/* Which ABI to use. */
-int mips_abi = MIPS_ABI_DEFAULT;
-
/* Which cost information to use. */
static const struct mips_rtx_cost_data *mips_cost;
/* The ambient target flags, excluding MASK_MIPS16. */
static int mips_base_target_flags;
-/* True if MIPS16 is the default mode. */
-bool mips_base_mips16;
+/* The default compression mode. */
+unsigned int mips_base_compression_flags;
/* The ambient values of other global variables. */
static int mips_base_schedule_insns; /* flag_schedule_insns */
static int mips_base_align_jumps; /* align_jumps */
static int mips_base_align_functions; /* align_functions */
-/* The -mcode-readable setting. */
-enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
-
-/* The -mr10k-cache-barrier setting. */
-static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier;
-
/* Index [M][R] is true if register R is allowed to hold a value of mode M. */
bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
can be split by mips_split_symbol. */
bool mips_split_hi_p[NUM_SYMBOL_TYPES];
+/* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
+ forced into a PC-relative constant pool. */
+bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES];
+
/* mips_lo_relocs[X] is the relocation to use when a symbol of type X
appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
if they are matched by a special .md file pattern. */
-static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
+const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
/* Likewise for HIGHs. */
-static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
+const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
/* Target state for MIPS16. */
struct target_globals *mips16_globals;
and returned from mips_sched_reorder2. */
static int cached_can_issue_more;
+/* The stubs for various MIPS16 support functions, if used. */
+static mips_one_only_stub *mips16_rdhwr_stub;
+static mips_one_only_stub *mips16_get_fcsr_stub;
+static mips_one_only_stub *mips16_set_fcsr_stub;
+
/* Index R is the smallest register class that contains register R. */
const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
- LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
- M16_REGS, M16_REGS, M16_REGS, M16_REGS,
- LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
- LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
- M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
- LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
- T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
- LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
+ LEA_REGS, LEA_REGS, M16_STORE_REGS, V1_REG,
+ M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS,
+ LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
+ LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
+ M16_REGS, M16_STORE_REGS, LEA_REGS, LEA_REGS,
+ LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
+ T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
+ LEA_REGS, M16_SP_REGS, LEA_REGS, LEA_REGS,
+
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
/* The value of TARGET_ATTRIBUTE_TABLE. */
static const struct attribute_spec mips_attribute_table[] = {
- /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
- { "long_call", 0, 0, false, true, true, NULL },
- { "far", 0, 0, false, true, true, NULL },
- { "near", 0, 0, false, true, true, NULL },
+ /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
+ om_diagnostic } */
+ { "long_call", 0, 0, false, true, true, NULL, false },
+ { "far", 0, 0, false, true, true, NULL, false },
+ { "near", 0, 0, false, true, true, NULL, false },
/* We would really like to treat "mips16" and "nomips16" as type
attributes, but GCC doesn't provide the hooks we need to support
the right conversion rules. As declaration attributes, they affect
code generation but don't carry other semantics. */
- { "mips16", 0, 0, true, false, false, NULL },
- { "nomips16", 0, 0, true, false, false, NULL },
+ { "mips16", 0, 0, true, false, false, NULL, false },
+ { "nomips16", 0, 0, true, false, false, NULL, false },
+ { "micromips", 0, 0, true, false, false, NULL, false },
+ { "nomicromips", 0, 0, true, false, false, NULL, false },
+ { "nocompression", 0, 0, true, false, false, NULL, false },
/* Allow functions to be specified as interrupt handlers */
- { "interrupt", 0, 0, false, true, true, NULL },
- { "use_shadow_register_set", 0, 0, false, true, true, NULL },
- { "keep_interrupts_masked", 0, 0, false, true, true, NULL },
- { "use_debug_exception_return", 0, 0, false, true, true, NULL },
- { NULL, 0, 0, false, false, false, NULL }
+ { "interrupt", 0, 0, false, true, true, NULL, false },
+ { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
+ { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
+ { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
+ { NULL, 0, 0, false, false, false, NULL, false }
};
\f
-/* A table describing all the processors GCC knows about. Names are
- matched in the order listed. The first mention of an ISA level is
- taken as the canonical name for that ISA.
-
- To ease comparison, please keep this table in the same order
- as GAS's mips_cpu_info_table. Please also make sure that
- MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
- options correctly. */
+/* A table describing all the processors GCC knows about; see
+ mips-cpus.def for details. */
static const struct mips_cpu_info mips_cpu_info_table[] = {
- /* Entries for generic ISAs. */
- { "mips1", PROCESSOR_R3000, 1, 0 },
- { "mips2", PROCESSOR_R6000, 2, 0 },
- { "mips3", PROCESSOR_R4000, 3, 0 },
- { "mips4", PROCESSOR_R8000, 4, 0 },
- /* Prefer not to use branch-likely instructions for generic MIPS32rX
- and MIPS64rX code. The instructions were officially deprecated
- in revisions 2 and earlier, but revision 3 is likely to downgrade
- that to a recommendation to avoid the instructions in code that
- isn't tuned to a specific processor. */
- { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
- { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
- { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
- /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
- { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
-
- /* MIPS I processors. */
- { "r3000", PROCESSOR_R3000, 1, 0 },
- { "r2000", PROCESSOR_R3000, 1, 0 },
- { "r3900", PROCESSOR_R3900, 1, 0 },
-
- /* MIPS II processors. */
- { "r6000", PROCESSOR_R6000, 2, 0 },
-
- /* MIPS III processors. */
- { "r4000", PROCESSOR_R4000, 3, 0 },
- { "vr4100", PROCESSOR_R4100, 3, 0 },
- { "vr4111", PROCESSOR_R4111, 3, 0 },
- { "vr4120", PROCESSOR_R4120, 3, 0 },
- { "vr4130", PROCESSOR_R4130, 3, 0 },
- { "vr4300", PROCESSOR_R4300, 3, 0 },
- { "r4400", PROCESSOR_R4000, 3, 0 },
- { "r4600", PROCESSOR_R4600, 3, 0 },
- { "orion", PROCESSOR_R4600, 3, 0 },
- { "r4650", PROCESSOR_R4650, 3, 0 },
- /* ST Loongson 2E/2F processors. */
- { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
- { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
-
- /* MIPS IV processors. */
- { "r8000", PROCESSOR_R8000, 4, 0 },
- { "r10000", PROCESSOR_R10000, 4, 0 },
- { "r12000", PROCESSOR_R10000, 4, 0 },
- { "r14000", PROCESSOR_R10000, 4, 0 },
- { "r16000", PROCESSOR_R10000, 4, 0 },
- { "vr5000", PROCESSOR_R5000, 4, 0 },
- { "vr5400", PROCESSOR_R5400, 4, 0 },
- { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
- { "rm7000", PROCESSOR_R7000, 4, 0 },
- { "rm9000", PROCESSOR_R9000, 4, 0 },
-
- /* MIPS32 processors. */
- { "4kc", PROCESSOR_4KC, 32, 0 },
- { "4km", PROCESSOR_4KC, 32, 0 },
- { "4kp", PROCESSOR_4KP, 32, 0 },
- { "4ksc", PROCESSOR_4KC, 32, 0 },
-
- /* MIPS32 Release 2 processors. */
- { "m4k", PROCESSOR_M4K, 33, 0 },
- { "4kec", PROCESSOR_4KC, 33, 0 },
- { "4kem", PROCESSOR_4KC, 33, 0 },
- { "4kep", PROCESSOR_4KP, 33, 0 },
- { "4ksd", PROCESSOR_4KC, 33, 0 },
-
- { "24kc", PROCESSOR_24KC, 33, 0 },
- { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
- { "24kf", PROCESSOR_24KF2_1, 33, 0 },
- { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
- { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
- { "24kx", PROCESSOR_24KF1_1, 33, 0 },
-
- { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
- { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
- { "24kef", PROCESSOR_24KF2_1, 33, 0 },
- { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
- { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
- { "24kex", PROCESSOR_24KF1_1, 33, 0 },
-
- { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
- { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
- { "34kf", PROCESSOR_24KF2_1, 33, 0 },
- { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
- { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
- { "34kx", PROCESSOR_24KF1_1, 33, 0 },
-
- { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
- { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
- { "74kf", PROCESSOR_74KF2_1, 33, 0 },
- { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
- { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
- { "74kx", PROCESSOR_74KF1_1, 33, 0 },
- { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
-
- { "1004kc", PROCESSOR_24KC, 33, 0 }, /* 1004K with MT/DSP. */
- { "1004kf2_1", PROCESSOR_24KF2_1, 33, 0 },
- { "1004kf", PROCESSOR_24KF2_1, 33, 0 },
- { "1004kf1_1", PROCESSOR_24KF1_1, 33, 0 },
-
- /* MIPS64 processors. */
- { "5kc", PROCESSOR_5KC, 64, 0 },
- { "5kf", PROCESSOR_5KF, 64, 0 },
- { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
- { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
- { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
- { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
- { "xlr", PROCESSOR_XLR, 64, 0 },
- { "loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY },
-
- /* MIPS64 Release 2 processors. */
- { "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
+#define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
+ { NAME, CPU, ISA, FLAGS },
+#include "mips-cpus.def"
+#undef MIPS_CPU
};
/* Default costs. If these are used for a processor we should look
1, /* branch_cost */
4 /* memory_latency */
},
+ /* Octeon II */
+ {
+ SOFT_FP_COSTS,
+ COSTS_N_INSNS (6), /* int_mult_si */
+ COSTS_N_INSNS (6), /* int_mult_di */
+ COSTS_N_INSNS (18), /* int_div_si */
+ COSTS_N_INSNS (35), /* int_div_di */
+ 4, /* branch_cost */
+ 4 /* memory_latency */
+ },
{ /* R3900 */
COSTS_N_INSNS (2), /* fp_add */
COSTS_N_INSNS (4), /* fp_mult_sf */
{ /* R4650 */
DEFAULT_COSTS
},
+ { /* R4700 */
+ DEFAULT_COSTS
+ },
{ /* R5000 */
COSTS_N_INSNS (6), /* fp_add */
COSTS_N_INSNS (4), /* fp_mult_sf */
1, /* branch_cost */
4 /* memory_latency */
},
+ { /* R5900 */
+ COSTS_N_INSNS (4), /* fp_add */
+ COSTS_N_INSNS (4), /* fp_mult_sf */
+ COSTS_N_INSNS (256), /* fp_mult_df */
+ COSTS_N_INSNS (8), /* fp_div_sf */
+ COSTS_N_INSNS (256), /* fp_div_df */
+ COSTS_N_INSNS (4), /* int_mult_si */
+ COSTS_N_INSNS (256), /* int_mult_di */
+ COSTS_N_INSNS (37), /* int_div_si */
+ COSTS_N_INSNS (256), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
{ /* R7000 */
/* The only costs that are changed here are
integer multiplication. */
COSTS_N_INSNS (72), /* int_div_di */
1, /* branch_cost */
4 /* memory_latency */
+ },
+ { /* XLP */
+ /* These costs are the same as 5KF above. */
+ COSTS_N_INSNS (4), /* fp_add */
+ COSTS_N_INSNS (4), /* fp_mult_sf */
+ COSTS_N_INSNS (5), /* fp_mult_df */
+ COSTS_N_INSNS (17), /* fp_div_sf */
+ COSTS_N_INSNS (32), /* fp_div_df */
+ COSTS_N_INSNS (4), /* int_mult_si */
+ COSTS_N_INSNS (11), /* int_mult_di */
+ COSTS_N_INSNS (36), /* int_div_si */
+ COSTS_N_INSNS (68), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* P5600 */
+ COSTS_N_INSNS (4), /* fp_add */
+ COSTS_N_INSNS (5), /* fp_mult_sf */
+ COSTS_N_INSNS (5), /* fp_mult_df */
+ COSTS_N_INSNS (17), /* fp_div_sf */
+ COSTS_N_INSNS (17), /* fp_div_df */
+ COSTS_N_INSNS (5), /* int_mult_si */
+ COSTS_N_INSNS (5), /* int_mult_di */
+ COSTS_N_INSNS (8), /* int_div_si */
+ COSTS_N_INSNS (8), /* int_div_di */
+ 2, /* branch_cost */
+ 10 /* memory_latency */
}
};
\f
-static rtx mips_find_pic_call_symbol (rtx, rtx);
+static rtx mips_find_pic_call_symbol (rtx_insn *, rtx, bool);
static int mips_register_move_cost (enum machine_mode, reg_class_t,
reg_class_t);
static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
\f
-/* This hash table keeps track of implicit "mips16" and "nomips16" attributes
- for -mflip_mips16. It maps decl names onto a boolean mode setting. */
-struct GTY (()) mflip_mips16_entry {
- const char *name;
- bool mips16_p;
-};
-static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
-
-/* Hash table callbacks for mflip_mips16_htab. */
-
-static hashval_t
-mflip_mips16_htab_hash (const void *entry)
+struct mips16_flip_traits : default_hashmap_traits
{
- return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
-}
+ static hashval_t hash (const char *s) { return htab_hash_string (s); }
+ static bool
+ equal_keys (const char *a, const char *b)
+ {
+ return !strcmp (a, b);
+ }
+};
-static int
-mflip_mips16_htab_eq (const void *entry, const void *name)
-{
- return strcmp (((const struct mflip_mips16_entry *) entry)->name,
- (const char *) name) == 0;
-}
+/* This hash table keeps track of implicit "mips16" and "nomips16" attributes
+ for -mflip_mips16. It maps decl names onto a boolean mode setting. */
+static GTY (()) hash_map<const char *, bool, mips16_flip_traits> *
+ mflip_mips16_htab;
/* True if -mflip-mips16 should next add an attribute for the default MIPS16
mode, false if it should next add an attribute for the opposite mode. */
static bool
mflip_mips16_use_mips16_p (tree decl)
{
- struct mflip_mips16_entry *entry;
const char *name;
- hashval_t hash;
- void **slot;
+ bool base_is_mips16 = (mips_base_compression_flags & MASK_MIPS16) != 0;
/* Use the opposite of the command-line setting for anonymous decls. */
if (!DECL_NAME (decl))
- return !mips_base_mips16;
+ return !base_is_mips16;
if (!mflip_mips16_htab)
- mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
- mflip_mips16_htab_eq, NULL);
+ mflip_mips16_htab
+ = hash_map<const char *, bool, mips16_flip_traits>::create_ggc (37);
name = IDENTIFIER_POINTER (DECL_NAME (decl));
- hash = htab_hash_string (name);
- slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
- entry = (struct mflip_mips16_entry *) *slot;
- if (!entry)
+
+ bool existed;
+ bool *slot = &mflip_mips16_htab->get_or_insert (name, &existed);
+ if (!existed)
{
mips16_flipper = !mips16_flipper;
- entry = ggc_alloc_mflip_mips16_entry ();
- entry->name = name;
- entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
- *slot = entry;
+ *slot = mips16_flipper ? !base_is_mips16 : base_is_mips16;
}
- return entry->mips16_p;
+ return *slot;
}
\f
/* Predicates to test for presence of "near" and "far"/"long_call"
|| lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
}
-/* Similar predicates for "mips16"/"nomips16" function attributes. */
-
-static bool
-mips_mips16_decl_p (const_tree decl)
-{
- return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
-}
-
-static bool
-mips_nomips16_decl_p (const_tree decl)
-{
- return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
-}
/* Check if the interrupt attribute is set for a function. */
TYPE_ATTRIBUTES (type)) != NULL;
}
-/* Return true if function DECL is a MIPS16 function. Return the ambient
- setting if DECL is null. */
+/* Return the set of compression modes that are explicitly required
+ by the attributes in ATTRIBUTES. */
-static bool
-mips_use_mips16_mode_p (tree decl)
+static unsigned int
+mips_get_compress_on_flags (tree attributes)
+{
+ unsigned int flags = 0;
+
+ if (lookup_attribute ("mips16", attributes) != NULL)
+ flags |= MASK_MIPS16;
+
+ if (lookup_attribute ("micromips", attributes) != NULL)
+ flags |= MASK_MICROMIPS;
+
+ return flags;
+}
+
+/* Return the set of compression modes that are explicitly forbidden
+ by the attributes in ATTRIBUTES. */
+
+static unsigned int
+mips_get_compress_off_flags (tree attributes)
{
+ unsigned int flags = 0;
+
+ if (lookup_attribute ("nocompression", attributes) != NULL)
+ flags |= MASK_MIPS16 | MASK_MICROMIPS;
+
+ if (lookup_attribute ("nomips16", attributes) != NULL)
+ flags |= MASK_MIPS16;
+
+ if (lookup_attribute ("nomicromips", attributes) != NULL)
+ flags |= MASK_MICROMIPS;
+
+ return flags;
+}
+
+/* Return the compression mode that should be used for function DECL.
+ Return the ambient setting if DECL is null. */
+
+static unsigned int
+mips_get_compress_mode (tree decl)
+{
+ unsigned int flags, force_on;
+
+ flags = mips_base_compression_flags;
if (decl)
{
/* Nested functions must use the same frame pointer as their
tree parent = decl_function_context (decl);
if (parent)
decl = parent;
- if (mips_mips16_decl_p (decl))
- return true;
- if (mips_nomips16_decl_p (decl))
- return false;
+ force_on = mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
+ if (force_on)
+ return force_on;
+ flags &= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
}
- return mips_base_mips16;
+ return flags;
+}
+
+/* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
+ flags FLAGS. */
+
+static const char *
+mips_get_compress_on_name (unsigned int flags)
+{
+ if (flags == MASK_MIPS16)
+ return "mips16";
+ return "micromips";
+}
+
+/* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
+ flags FLAGS. */
+
+static const char *
+mips_get_compress_off_name (unsigned int flags)
+{
+ if (flags == MASK_MIPS16)
+ return "nomips16";
+ if (flags == MASK_MICROMIPS)
+ return "nomicromips";
+ return "nocompression";
}
/* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
mips_insert_attributes (tree decl, tree *attributes)
{
const char *name;
- bool mips16_p, nomips16_p;
+ unsigned int compression_flags, nocompression_flags;
/* Check for "mips16" and "nomips16" attributes. */
- mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
- nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
+ compression_flags = mips_get_compress_on_flags (*attributes);
+ nocompression_flags = mips_get_compress_off_flags (*attributes);
+
if (TREE_CODE (decl) != FUNCTION_DECL)
{
- if (mips16_p)
- error ("%qs attribute only applies to functions", "mips16");
- if (nomips16_p)
- error ("%qs attribute only applies to functions", "nomips16");
+ if (nocompression_flags)
+ error ("%qs attribute only applies to functions",
+ mips_get_compress_off_name (nocompression_flags));
+
+ if (compression_flags)
+ error ("%qs attribute only applies to functions",
+ mips_get_compress_on_name (nocompression_flags));
}
else
{
- mips16_p |= mips_mips16_decl_p (decl);
- nomips16_p |= mips_nomips16_decl_p (decl);
- if (mips16_p || nomips16_p)
- {
- /* DECL cannot be simultaneously "mips16" and "nomips16". */
- if (mips16_p && nomips16_p)
- error ("%qE cannot have both %<mips16%> and "
- "%<nomips16%> attributes",
- DECL_NAME (decl));
- }
- else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
+ compression_flags |= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
+ nocompression_flags |=
+ mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
+
+ if (compression_flags && nocompression_flags)
+ error ("%qE cannot have both %qs and %qs attributes",
+ DECL_NAME (decl), mips_get_compress_on_name (compression_flags),
+ mips_get_compress_off_name (nocompression_flags));
+
+ if (compression_flags & MASK_MIPS16
+ && compression_flags & MASK_MICROMIPS)
+ error ("%qE cannot have both %qs and %qs attributes",
+ DECL_NAME (decl), "mips16", "micromips");
+
+ if (TARGET_FLIP_MIPS16
+ && !DECL_ARTIFICIAL (decl)
+ && compression_flags == 0
+ && nocompression_flags == 0)
{
/* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
"mips16" attribute, arbitrarily pick one. We must pick the same
setting for duplicate declarations of a function. */
name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
*attributes = tree_cons (get_identifier (name), NULL, *attributes);
+ name = "nomicromips";
+ *attributes = tree_cons (get_identifier (name), NULL, *attributes);
}
}
}
static tree
mips_merge_decl_attributes (tree olddecl, tree newdecl)
{
- /* The decls' "mips16" and "nomips16" attributes must match exactly. */
- if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
+ unsigned int diff;
+
+ diff = (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl))
+ ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl)));
+ if (diff)
error ("%qE redeclared with conflicting %qs attributes",
- DECL_NAME (newdecl), "mips16");
- if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
+ DECL_NAME (newdecl), mips_get_compress_on_name (diff));
+
+ diff = (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl))
+ ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl)));
+ if (diff)
error ("%qE redeclared with conflicting %qs attributes",
- DECL_NAME (newdecl), "nomips16");
+ DECL_NAME (newdecl), mips_get_compress_off_name (diff));
return merge_attributes (DECL_ATTRIBUTES (olddecl),
DECL_ATTRIBUTES (newdecl));
}
+
+/* Implement TARGET_CAN_INLINE_P. */
+
+static bool
+mips_can_inline_p (tree caller, tree callee)
+{
+ if (mips_get_compress_mode (callee) != mips_get_compress_mode (caller))
+ return false;
+ return default_target_can_inline_p (caller, callee);
+}
\f
/* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
}
}
\f
+/* Implement TARGET_LEGITIMATE_CONSTANT_P. */
+
+static bool
+mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
+{
+ return mips_const_insns (x) > 0;
+}
+\f
+/* Return a SYMBOL_REF for a MIPS16 function called NAME. */
+
+static rtx
+mips16_stub_function (const char *name)
+{
+ rtx x;
+
+ x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
+ SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
+ return x;
+}
+
+/* Return a legitimate call address for STUB, given that STUB is a MIPS16
+ support function. */
+
+static rtx
+mips16_stub_call_address (mips_one_only_stub *stub)
+{
+ rtx fn = mips16_stub_function (stub->get_name ());
+ SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL;
+ if (!call_insn_operand (fn, VOIDmode))
+ fn = force_reg (Pmode, fn);
+ return fn;
+}
+\f
+/* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */
+
+class mips16_rdhwr_one_only_stub : public mips_one_only_stub
+{
+ virtual const char *get_name ();
+ virtual void output_body ();
+};
+
+const char *
+mips16_rdhwr_one_only_stub::get_name ()
+{
+ return "__mips16_rdhwr";
+}
+
+void
+mips16_rdhwr_one_only_stub::output_body ()
+{
+ fprintf (asm_out_file,
+ "\t.set\tpush\n"
+ "\t.set\tmips32r2\n"
+ "\t.set\tnoreorder\n"
+ "\trdhwr\t$3,$29\n"
+ "\t.set\tpop\n"
+ "\tj\t$31\n");
+}
+
+/* A stub for moving the FCSR into GET_FCSR_REGNUM. */
+class mips16_get_fcsr_one_only_stub : public mips_one_only_stub
+{
+ virtual const char *get_name ();
+ virtual void output_body ();
+};
+
+const char *
+mips16_get_fcsr_one_only_stub::get_name ()
+{
+ return "__mips16_get_fcsr";
+}
+
+void
+mips16_get_fcsr_one_only_stub::output_body ()
+{
+ fprintf (asm_out_file,
+ "\tcfc1\t%s,$31\n"
+ "\tj\t$31\n", reg_names[GET_FCSR_REGNUM]);
+}
+
+/* A stub for moving SET_FCSR_REGNUM into the FCSR. */
+class mips16_set_fcsr_one_only_stub : public mips_one_only_stub
+{
+ virtual const char *get_name ();
+ virtual void output_body ();
+};
+
+const char *
+mips16_set_fcsr_one_only_stub::get_name ()
+{
+ return "__mips16_set_fcsr";
+}
+
+void
+mips16_set_fcsr_one_only_stub::output_body ()
+{
+ fprintf (asm_out_file,
+ "\tctc1\t%s,$31\n"
+ "\tj\t$31\n", reg_names[SET_FCSR_REGNUM]);
+}
+\f
/* Return true if symbols of type TYPE require a GOT access. */
static bool
return (GET_CODE (x) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (x)
&& !SYMBOL_REF_EXTERNAL_P (x)
- && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
+ && (mips_get_compress_mode (SYMBOL_REF_DECL (x)) & MASK_MIPS16));
}
/* Return true if SYMBOL_REF X binds locally. */
return SYMBOL_GOT_PAGE_OFST;
}
- if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
- return SYMBOL_FORCE_TO_MEM;
-
return SYMBOL_ABSOLUTE;
}
switch (*symbol_type)
{
case SYMBOL_ABSOLUTE:
- case SYMBOL_FORCE_TO_MEM:
- case SYMBOL_32_HIGH:
case SYMBOL_64_HIGH:
case SYMBOL_64_MID:
case SYMBOL_64_LOW:
static int
mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
{
+ if (mips_use_pcrel_pool_p[(int) type])
+ {
+ if (mode == MAX_MACHINE_MODE)
+ /* LEAs will be converted into constant-pool references by
+ mips_reorg. */
+ type = SYMBOL_PC_RELATIVE;
+ else
+ /* The constant must be loaded and then dereferenced. */
+ return 0;
+ }
+
switch (type)
{
case SYMBOL_ABSOLUTE:
/* The constant must be loaded using ADDIUPC or DADDIUPC first. */
return 0;
- case SYMBOL_FORCE_TO_MEM:
- /* LEAs will be converted into constant-pool references by
- mips_reorg. */
- if (mode == MAX_MACHINE_MODE)
- return 1;
-
- /* The constant must be loaded and then dereferenced. */
- return 0;
-
case SYMBOL_GOT_DISP:
/* The constant will have to be loaded from the GOT before it
is used in an address. */
case SYMBOL_GOTOFF_DISP:
case SYMBOL_GOTOFF_CALL:
case SYMBOL_GOTOFF_LOADGP:
- case SYMBOL_32_HIGH:
case SYMBOL_64_HIGH:
case SYMBOL_64_MID:
case SYMBOL_64_LOW:
values of mode MODE to or from addresses of type TYPE. Return 0 if
the given type of symbol is not valid in addresses.
- In both cases, treat extended MIPS16 instructions as two instructions. */
+ In both cases, instruction counts are based off BASE_INSN_LENGTH. */
static int
mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
}
\f
-/* A for_each_rtx callback. Stop the search if *X references a
- thread-local symbol. */
-
-static int
-mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
-{
- return mips_tls_symbol_p (*x);
-}
-
/* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
static bool
-mips_cannot_force_const_mem (rtx x)
+mips_cannot_force_const_mem (enum machine_mode mode, rtx x)
{
enum mips_symbol_type type;
rtx base, offset;
references, reload will consider forcing C into memory and using
one of the instruction's memory alternatives. Returning false
here will force it to use an input reload instead. */
- if (CONST_INT_P (x) && LEGITIMATE_CONSTANT_P (x))
+ if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
return true;
split_const (x, &base, &offset);
- if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)
- && type != SYMBOL_FORCE_TO_MEM)
+ if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type))
{
+ /* See whether we explicitly want these symbols in the pool. */
+ if (mips_use_pcrel_pool_p[(int) type])
+ return false;
+
/* The same optimization as for CONST_INT. */
if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
return true;
}
/* TLS symbols must be computed by mips_legitimize_move. */
- if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
+ if (tls_referenced_p (x))
return true;
return false;
return true;
/* In MIPS16 mode, the stack pointer can only address word and doubleword
- values, nothing smaller. There are two problems here:
-
- (a) Instantiating virtual registers can introduce new uses of the
- stack pointer. If these virtual registers are valid addresses,
- the stack pointer should be too.
-
- (b) Most uses of the stack pointer are not made explicit until
- FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
- We don't know until that stage whether we'll be eliminating to the
- stack pointer (which needs the restriction) or the hard frame
- pointer (which doesn't).
-
- All in all, it seems more consistent to only enforce this restriction
- during and after reload. */
+ values, nothing smaller. */
if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
- return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
+ return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
}
}
return false;
}
+
+/* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
+ indexed address instruction. Note that such addresses are
+ not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
+ sense, because their use is so restricted. */
+
+static bool
+mips_lx_address_p (rtx addr, enum machine_mode mode)
+{
+ if (GET_CODE (addr) != PLUS
+ || !REG_P (XEXP (addr, 0))
+ || !REG_P (XEXP (addr, 1)))
+ return false;
+ if (ISA_HAS_LBX && mode == QImode)
+ return true;
+ if (ISA_HAS_LHX && mode == HImode)
+ return true;
+ if (ISA_HAS_LWX && mode == SImode)
+ return true;
+ if (ISA_HAS_LDX && mode == DImode)
+ return true;
+ return false;
+}
\f
/* Return true if a value at OFFSET bytes from base register BASE can be
accessed using an unextended MIPS16 instruction. MODE is the mode of
mips16_unextended_reference_p (enum machine_mode mode, rtx base,
unsigned HOST_WIDE_INT offset)
{
- if (offset % GET_MODE_SIZE (mode) == 0)
+ if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0)
{
if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
return offset < 256U * GET_MODE_SIZE (mode);
}
/* Return the number of instructions needed to load or store a value
- of mode MODE at address X. Return 0 if X isn't valid for MODE.
+ of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
+ length of one instruction. Return 0 if X isn't valid for MODE.
Assume that multiword moves may need to be split into word moves
if MIGHT_SPLIT_P, otherwise assume that a single load or store is
- enough.
-
- For MIPS16 code, count extended instructions as two instructions. */
+ enough. */
int
mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
return 0;
}
-/* Return the number of instructions needed to load constant X.
- Return 0 if X isn't a valid constant. */
+/* Return true if X fits within an unsigned field of BITS bits that is
+ shifted left SHIFT bits before being used. */
-int
-mips_const_insns (rtx x)
+bool
+mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
{
- struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
- enum mips_symbol_type symbol_type;
- rtx offset;
+ return (x & ((1 << shift) - 1)) == 0 && x < ((unsigned) 1 << (shift + bits));
+}
- switch (GET_CODE (x))
- {
- case HIGH:
- if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
- &symbol_type)
- || !mips_split_p[symbol_type])
- return 0;
+/* Return true if X fits within a signed field of BITS bits that is
+ shifted left SHIFT bits before being used. */
- /* This is simply an LUI for normal mode. It is an extended
- LI followed by an extended SLL for MIPS16. */
- return TARGET_MIPS16 ? 4 : 1;
+bool
+mips_signed_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
+{
+ x += 1 << (bits + shift - 1);
+ return mips_unsigned_immediate_p (x, bits, shift);
+}
- case CONST_INT:
- if (TARGET_MIPS16)
- /* Unsigned 8-bit constants can be loaded using an unextended
- LI instruction. Unsigned 16-bit constants can be loaded
- using an extended LI. Negative constants must be loaded
- using LI and then negated. */
- return (IN_RANGE (INTVAL (x), 0, 255) ? 1
- : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
- : IN_RANGE (-INTVAL (x), 0, 255) ? 2
- : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
- : 0);
+/* Return true if X is legitimate for accessing values of mode MODE,
+ if it is based on a MIPS16 register, and if the offset satisfies
+ OFFSET_PREDICATE. */
+
+bool
+m16_based_address_p (rtx x, enum machine_mode mode,
+ insn_operand_predicate_fn offset_predicate)
+{
+ struct mips_address_info addr;
+
+ return (mips_classify_address (&addr, x, mode, false)
+ && addr.type == ADDRESS_REG
+ && M16_REG_P (REGNO (addr.reg))
+ && offset_predicate (addr.offset, mode));
+}
+
+/* Return true if X is a legitimate address that conforms to the requirements
+ for a microMIPS LWSP or SWSP insn. */
+
+bool
+lwsp_swsp_address_p (rtx x, enum machine_mode mode)
+{
+ struct mips_address_info addr;
+
+ return (mips_classify_address (&addr, x, mode, false)
+ && addr.type == ADDRESS_REG
+ && REGNO (addr.reg) == STACK_POINTER_REGNUM
+ && uw5_operand (addr.offset, mode));
+}
+
+/* Return true if X is a legitimate address with a 12-bit offset.
+ MODE is the mode of the value being accessed. */
+
+bool
+umips_12bit_offset_address_p (rtx x, enum machine_mode mode)
+{
+ struct mips_address_info addr;
+
+ return (mips_classify_address (&addr, x, mode, false)
+ && addr.type == ADDRESS_REG
+ && CONST_INT_P (addr.offset)
+ && UMIPS_12BIT_OFFSET_P (INTVAL (addr.offset)));
+}
+
+/* Return the number of instructions needed to load constant X,
+ assuming that BASE_INSN_LENGTH is the length of one instruction.
+ Return 0 if X isn't a valid constant. */
+
+int
+mips_const_insns (rtx x)
+{
+ struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
+ enum mips_symbol_type symbol_type;
+ rtx offset;
+
+ switch (GET_CODE (x))
+ {
+ case HIGH:
+ if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
+ &symbol_type)
+ || !mips_split_p[symbol_type])
+ return 0;
+
+ /* This is simply an LUI for normal mode. It is an extended
+ LI followed by an extended SLL for MIPS16. */
+ return TARGET_MIPS16 ? 4 : 1;
+
+ case CONST_INT:
+ if (TARGET_MIPS16)
+ /* Unsigned 8-bit constants can be loaded using an unextended
+ LI instruction. Unsigned 16-bit constants can be loaded
+ using an extended LI. Negative constants must be loaded
+ using LI and then negated. */
+ return (IN_RANGE (INTVAL (x), 0, 255) ? 1
+ : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
+ : IN_RANGE (-INTVAL (x), 0, 255) ? 2
+ : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
+ : 0);
return mips_build_integer (codes, INTVAL (x));
{
if (SMALL_INT (offset))
return n + 1;
- else if (!targetm.cannot_force_const_mem (x))
+ else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
return n + 1 + mips_build_integer (codes, INTVAL (offset));
}
}
/* X is a doubleword constant that can be handled by splitting it into
two words and loading each word separately. Return the number of
- instructions required to do this. */
+ instructions required to do this, assuming that BASE_INSN_LENGTH
+ is the length of one instruction. */
int
mips_split_const_insns (rtx x)
}
/* Return the number of instructions needed to implement INSN,
- given that it loads from or stores to MEM. Count extended
- MIPS16 instructions as two instructions. */
+ given that it loads from or stores to MEM. Assume that
+ BASE_INSN_LENGTH is the length of one instruction. */
int
-mips_load_store_insns (rtx mem, rtx insn)
+mips_load_store_insns (rtx mem, rtx_insn *insn)
{
enum machine_mode mode;
bool might_split_p;
mode = GET_MODE (mem);
/* Try to prove that INSN does not need to be split. */
- might_split_p = true;
- if (GET_MODE_BITSIZE (mode) == 64)
+ might_split_p = GET_MODE_SIZE (mode) > UNITS_PER_WORD;
+ if (might_split_p)
{
set = single_set (insn);
- if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
+ if (set && !mips_split_move_insn_p (SET_DEST (set), SET_SRC (set), insn))
might_split_p = false;
}
return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
}
-/* Return the number of instructions needed for an integer division. */
+/* Return the number of instructions needed for an integer division,
+ assuming that BASE_INSN_LENGTH is the length of one instruction. */
int
mips_idiv_insns (void)
how to force Pmode objects into the constant pool even when the
constant pool address is not itself legitimate. */
-rtx
+rtx_insn *
mips_emit_move (rtx dest, rtx src)
{
return (can_create_pseudo_p ()
: emit_move_insn_1 (dest, src));
}
+/* Emit a move from SRC to DEST, splitting compound moves into individual
+ instructions. SPLIT_TYPE is the type of split to perform. */
+
+static void
+mips_emit_move_or_split (rtx dest, rtx src, enum mips_split_type split_type)
+{
+ if (mips_split_move_p (dest, src, split_type))
+ mips_split_move (dest, src, split_type);
+ else
+ mips_emit_move (dest, src);
+}
+
/* Emit an instruction of the form (set TARGET (CODE OP0)). */
static void
/* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
-static void
+void
mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
{
emit_insn (gen_rtx_SET (VOIDmode, target,
ADDR is the legitimized form, and LAZY_P is true if the call
address is lazily-bound. */
-static rtx
+static rtx_insn *
mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
{
- rtx insn, reg;
+ rtx_insn *insn;
+ rtx reg;
insn = emit_call_insn (pattern);
gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
emit_insn (gen_update_got_version ());
}
+
+ if (TARGET_MIPS16
+ && TARGET_EXPLICIT_RELOCS
+ && TARGET_CALL_CLOBBERED_GP)
+ {
+ rtx post_call_tmp_reg = gen_rtx_REG (word_mode, POST_CALL_TMP_REG);
+ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), post_call_tmp_reg);
+ }
+
return insn;
}
\f
/* If OP is an UNSPEC address, return the address to which it refers,
otherwise return OP itself. */
-static rtx
+rtx
mips_strip_unspec_address (rtx op)
{
rtx base, offset;
split_const (op, &base, &offset);
if (UNSPEC_ADDRESS_P (base))
- op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
+ op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset));
return op;
}
static rtx
gen_load_const_gp (rtx reg)
{
- return (Pmode == SImode
- ? gen_load_const_gp_si (reg)
- : gen_load_const_gp_di (reg));
+ return PMODE_INSN (gen_load_const_gp, (reg));
}
/* Return a pseudo register that contains the value of $gp throughout
{
if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
{
- rtx insn, scan;
+ rtx_insn *scan;
cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
scan = NEXT_INSN (scan);
- insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
- emit_insn_after (insn, scan);
+ rtx set = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
+ rtx_insn *insn = emit_insn_after (set, scan);
+ INSN_LOCATION (insn) = 0;
pop_topmost_sequence ();
}
if (type == SYMBOL_GOTOFF_CALL)
return mips_unspec_call (high, lo_sum_symbol);
else
- return (Pmode == SImode
- ? gen_unspec_gotsi (high, lo_sum_symbol)
- : gen_unspec_gotdi (high, lo_sum_symbol));
+ return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol));
}
/* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
high = mips_force_temporary (temp, high);
reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
}
- return plus_constant (reg, offset);
+ return plus_constant (Pmode, reg, offset);
}
\f
/* The __tls_get_attr symbol. */
/* Return a pseudo register that contains the current thread pointer. */
-static rtx
-mips_get_tp (void)
+rtx
+mips_expand_thread_pointer (rtx tp)
{
- rtx tp;
+ rtx fn;
- tp = gen_reg_rtx (Pmode);
- if (Pmode == DImode)
- emit_insn (gen_tls_get_tp_di (tp));
+ if (TARGET_MIPS16)
+ {
+ if (!mips16_rdhwr_stub)
+ mips16_rdhwr_stub = new mips16_rdhwr_one_only_stub ();
+ fn = mips16_stub_call_address (mips16_rdhwr_stub);
+ emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn)));
+ }
else
- emit_insn (gen_tls_get_tp_si (tp));
+ emit_insn (PMODE_INSN (gen_tls_get_tp, (tp)));
return tp;
}
+static rtx
+mips_get_tp (void)
+{
+ return mips_expand_thread_pointer (gen_reg_rtx (Pmode));
+}
+
/* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
its address. The return value will be both a valid address and a valid
SET_SRC (either a REG or a LO_SUM). */
static rtx
mips_legitimize_tls_address (rtx loc)
{
- rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
+ rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset;
enum tls_model model;
- if (TARGET_MIPS16)
- {
- sorry ("MIPS16 TLS");
- return gen_reg_rtx (Pmode);
- }
-
model = SYMBOL_REF_TLS_MODEL (loc);
/* Only TARGET_ABICALLS code can have more than one module; other
code must be be static and should not use a GOT. All TLS models
UNSPEC_TLS_LDM);
emit_libcall_block (insn, tmp1, v0, eqv);
- tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
- dest = gen_rtx_LO_SUM (Pmode, tmp2,
- mips_unspec_address (loc, SYMBOL_DTPREL));
+ offset = mips_unspec_address (loc, SYMBOL_DTPREL);
+ if (mips_split_p[SYMBOL_DTPREL])
+ {
+ tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
+ dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
+ }
+ else
+ dest = expand_binop (Pmode, add_optab, tmp1, offset,
+ 0, 0, OPTAB_DIRECT);
break;
case TLS_MODEL_INITIAL_EXEC:
break;
case TLS_MODEL_LOCAL_EXEC:
- tp = mips_get_tp ();
- tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
- dest = gen_rtx_LO_SUM (Pmode, tmp1,
- mips_unspec_address (loc, SYMBOL_TPREL));
+ tmp1 = mips_get_tp ();
+ offset = mips_unspec_address (loc, SYMBOL_TPREL);
+ if (mips_split_p[SYMBOL_TPREL])
+ {
+ tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL);
+ dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
+ }
+ else
+ dest = expand_binop (Pmode, add_optab, tmp1, offset,
+ 0, 0, OPTAB_DIRECT);
break;
default:
return dest;
}
\f
+/* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16,
+ using a stub. */
+
+void
+mips16_expand_get_fcsr (rtx target)
+{
+ if (!mips16_get_fcsr_stub)
+ mips16_get_fcsr_stub = new mips16_get_fcsr_one_only_stub ();
+ rtx fn = mips16_stub_call_address (mips16_get_fcsr_stub);
+ emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16, (fn)));
+ emit_move_insn (target, gen_rtx_REG (SImode, GET_FCSR_REGNUM));
+}
+
+/* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */
+
+void
+mips16_expand_set_fcsr (rtx newval)
+{
+ if (!mips16_set_fcsr_stub)
+ mips16_set_fcsr_stub = new mips16_set_fcsr_one_only_stub ();
+ rtx fn = mips16_stub_call_address (mips16_set_fcsr_stub);
+ emit_move_insn (gen_rtx_REG (SImode, SET_FCSR_REGNUM), newval);
+ emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16, (fn)));
+}
+\f
/* If X is not a valid address for mode MODE, force it into a register. */
static rtx
forced into memory, as it usually produces better code. */
split_const (src, &base, &offset);
if (offset != const0_rtx
- && (targetm.cannot_force_const_mem (src)
+ && (targetm.cannot_force_const_mem (mode, src)
|| (!TARGET_MIPS16 && can_create_pseudo_p ())))
{
base = mips_force_temporary (dest, base);
{
enum mips_symbol_context context;
- if (GET_CODE (*loc) == LO_SUM)
+ /* Ignore things like "g" constraints in asms. We make no particular
+ guarantee about which symbolic constants are acceptable as asm operands
+ versus which must be forced into a GPR. */
+ if (GET_CODE (*loc) == LO_SUM || GET_CODE (*loc) == ASM_OPERANDS)
return -1;
if (MEM_P (*loc))
return pattern;
}
\f
-/* We need a lot of little routines to check the range of MIPS16 immediate
- operands. */
-
-static int
-m16_check_op (rtx op, int low, int high, int mask)
-{
- return (CONST_INT_P (op)
- && IN_RANGE (INTVAL (op), low, high)
- && (INTVAL (op) & mask) == 0);
-}
-
-int
-m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return m16_check_op (op, 0x1, 0x8, 0);
-}
-
-int
-m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return m16_check_op (op, -0x8, 0x7, 0);
-}
-
-int
-m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return m16_check_op (op, -0x7, 0x8, 0);
-}
-
-int
-m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return m16_check_op (op, -0x10, 0xf, 0);
-}
-
-int
-m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return m16_check_op (op, -0xf, 0x10, 0);
-}
-
-int
-m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
-}
-
-int
-m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
-}
-
-int
-m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return m16_check_op (op, -0x80, 0x7f, 0);
-}
-
-int
-m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return m16_check_op (op, -0x7f, 0x80, 0);
-}
-
-int
-m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return m16_check_op (op, 0x0, 0xff, 0);
-}
-
-int
-m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return m16_check_op (op, -0xff, 0x0, 0);
-}
-
-int
-m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return m16_check_op (op, -0x1, 0xfe, 0);
-}
-
-int
-m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return m16_check_op (op, 0x0, 0xff << 2, 3);
-}
-
-int
-m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return m16_check_op (op, -0xff << 2, 0x0, 3);
-}
-
-int
-m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
-}
-
-int
-m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
-}
-\f
/* The cost of loading values from the constant pool. It should be
larger than the cost of any constant we want to synthesize inline. */
#define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
else
cost = single_cost;
return (cost
- + rtx_cost (XEXP (x, 0), SET, speed)
- + rtx_cost (XEXP (x, 1), GET_CODE (x), speed));
+ + set_src_cost (XEXP (x, 0), speed)
+ + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed));
}
/* Return the cost of floating-point multiplications of mode MODE. */
return COSTS_N_INSNS (1);
}
+/* Return the cost of moving between two registers of mode MODE,
+ assuming that the move will be in pieces of at most UNITS bytes. */
+
+static int
+mips_set_reg_reg_piece_cost (enum machine_mode mode, unsigned int units)
+{
+ return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units);
+}
+
+/* Return the cost of moving between two registers of mode MODE. */
+
+static int
+mips_set_reg_reg_cost (enum machine_mode mode)
+{
+ switch (GET_MODE_CLASS (mode))
+ {
+ case MODE_CC:
+ return mips_set_reg_reg_piece_cost (mode, GET_MODE_SIZE (CCmode));
+
+ case MODE_FLOAT:
+ case MODE_COMPLEX_FLOAT:
+ case MODE_VECTOR_FLOAT:
+ if (TARGET_HARD_FLOAT)
+ return mips_set_reg_reg_piece_cost (mode, UNITS_PER_HWFPVALUE);
+ /* Fall through */
+
+ default:
+ return mips_set_reg_reg_piece_cost (mode, UNITS_PER_WORD);
+ }
+}
+
/* Implement TARGET_RTX_COSTS. */
static bool
-mips_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
+mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
+ int *total, bool speed)
{
enum machine_mode mode = GET_MODE (x);
bool float_mode_p = FLOAT_MODE_P (mode);
return true;
}
/* Check for a scaled indexed address. */
- if (mips_lwxs_address_p (addr))
+ if (mips_lwxs_address_p (addr)
+ || mips_lx_address_p (addr, mode))
{
*total = COSTS_N_INSNS (2);
return true;
&& UINTVAL (XEXP (x, 1)) == 0xffffffff)
{
*total = (mips_zero_extend_cost (mode, XEXP (x, 0))
- + rtx_cost (XEXP (x, 0), SET, speed));
+ + set_src_cost (XEXP (x, 0), speed));
+ return true;
+ }
+ if (ISA_HAS_CINS && CONST_INT_P (XEXP (x, 1)))
+ {
+ rtx op = XEXP (x, 0);
+ if (GET_CODE (op) == ASHIFT
+ && CONST_INT_P (XEXP (op, 1))
+ && mask_low_and_shift_p (mode, XEXP (x, 1), XEXP (op, 1), 32))
+ {
+ *total = COSTS_N_INSNS (1) + set_src_cost (XEXP (op, 0), speed);
+ return true;
+ }
+ }
+ /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
+ a single instruction. */
+ if (!TARGET_MIPS16
+ && GET_CODE (XEXP (x, 0)) == NOT
+ && GET_CODE (XEXP (x, 1)) == NOT)
+ {
+ cost = GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1;
+ *total = (COSTS_N_INSNS (cost)
+ + set_src_cost (XEXP (XEXP (x, 0), 0), speed)
+ + set_src_cost (XEXP (XEXP (x, 1), 0), speed));
return true;
}
+
/* Fall through. */
case IOR:
case LO_SUM:
/* Low-part immediates need an extended MIPS16 instruction. */
*total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
- + rtx_cost (XEXP (x, 0), SET, speed));
+ + set_src_cost (XEXP (x, 0), speed));
return true;
case LT:
case MINUS:
if (float_mode_p
- && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
+ && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3)
&& TARGET_FUSED_MADD
&& !HONOR_NANS (mode)
&& !HONOR_SIGNED_ZEROS (mode))
if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
{
*total = (mips_fp_mult_cost (mode)
- + rtx_cost (XEXP (XEXP (op0, 0), 0), SET, speed)
- + rtx_cost (XEXP (op0, 1), SET, speed)
- + rtx_cost (op1, SET, speed));
+ + set_src_cost (XEXP (XEXP (op0, 0), 0), speed)
+ + set_src_cost (XEXP (op0, 1), speed)
+ + set_src_cost (op1, speed));
return true;
}
if (GET_CODE (op1) == MULT)
{
*total = (mips_fp_mult_cost (mode)
- + rtx_cost (op0, SET, speed)
- + rtx_cost (XEXP (op1, 0), SET, speed)
- + rtx_cost (XEXP (op1, 1), SET, speed));
+ + set_src_cost (op0, speed)
+ + set_src_cost (XEXP (op1, 0), speed)
+ + set_src_cost (XEXP (op1, 1), speed));
return true;
}
}
{
/* If this is part of a MADD or MSUB, treat the PLUS as
being free. */
- if (ISA_HAS_FP4
+ if ((ISA_HAS_FP_MADD4_MSUB4 || ISA_HAS_FP_MADD3_MSUB3)
&& TARGET_FUSED_MADD
&& GET_CODE (XEXP (x, 0)) == MULT)
*total = 0;
case NEG:
if (float_mode_p
- && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
+ && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3)
&& TARGET_FUSED_MADD
&& !HONOR_NANS (mode)
&& HONOR_SIGNED_ZEROS (mode))
&& GET_CODE (XEXP (op, 0)) == MULT)
{
*total = (mips_fp_mult_cost (mode)
- + rtx_cost (XEXP (XEXP (op, 0), 0), SET, speed)
- + rtx_cost (XEXP (XEXP (op, 0), 1), SET, speed)
- + rtx_cost (XEXP (op, 1), SET, speed));
+ + set_src_cost (XEXP (XEXP (op, 0), 0), speed)
+ + set_src_cost (XEXP (XEXP (op, 0), 1), speed)
+ + set_src_cost (XEXP (op, 1), speed));
return true;
}
}
? mips_cost->int_mult_si * 3 + 6
: COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
else if (!speed)
- *total = (ISA_HAS_MUL3 ? 1 : 2);
+ *total = COSTS_N_INSNS (ISA_HAS_MUL3 ? 1 : 2) + 1;
else if (mode == DImode)
*total = mips_cost->int_mult_di;
else
case DIV:
/* Check for a reciprocal. */
if (float_mode_p
- && ISA_HAS_FP4
+ && ISA_HAS_FP_RECIP_RSQRT (mode)
&& flag_unsafe_math_optimizations
&& XEXP (x, 0) == CONST1_RTX (mode))
{
if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
/* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
division as being free. */
- *total = rtx_cost (XEXP (x, 1), SET, speed);
+ *total = set_src_cost (XEXP (x, 1), speed);
else
*total = (mips_fp_div_cost (mode)
- + rtx_cost (XEXP (x, 1), SET, speed));
+ + set_src_cost (XEXP (x, 1), speed));
return true;
}
/* Fall through. */
&& CONST_INT_P (XEXP (x, 1))
&& exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
{
- *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), SET, speed);
+ *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed);
return true;
}
*total = COSTS_N_INSNS (mips_idiv_insns ());
return false;
case ZERO_EXTEND:
+ if (outer_code == SET
+ && ISA_HAS_BADDU
+ && (GET_CODE (XEXP (x, 0)) == TRUNCATE
+ || GET_CODE (XEXP (x, 0)) == SUBREG)
+ && GET_MODE (XEXP (x, 0)) == QImode
+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
+ {
+ *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed);
+ return true;
+ }
*total = mips_zero_extend_cost (mode, XEXP (x, 0));
return false;
*total = mips_cost->fp_add;
return false;
+ case SET:
+ if (register_operand (SET_DEST (x), VOIDmode)
+ && reg_or_0_operand (SET_SRC (x), VOIDmode))
+ {
+ *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x)));
+ return true;
+ }
+ return false;
+
default:
return false;
}
/* Implement TARGET_ADDRESS_COST. */
static int
-mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
+mips_address_cost (rtx addr, enum machine_mode mode,
+ addr_space_t as ATTRIBUTE_UNUSED,
+ bool speed ATTRIBUTE_UNUSED)
{
- return mips_address_insns (addr, SImode, false);
+ return mips_address_insns (addr, mode, false);
}
\f
/* Information about a single instruction in a multi-instruction
};
typedef struct mips_multi_member mips_multi_member;
-/* Vector definitions for the above. */
-DEF_VEC_O(mips_multi_member);
-DEF_VEC_ALLOC_O(mips_multi_member, heap);
-
/* The instructions that make up the current multi-insn sequence. */
-static VEC (mips_multi_member, heap) *mips_multi_members;
+static vec<mips_multi_member> mips_multi_members;
/* How many instructions (as opposed to labels) are in the current
multi-insn sequence. */
static void
mips_multi_start (void)
{
- VEC_truncate (mips_multi_member, mips_multi_members, 0);
+ mips_multi_members.truncate (0);
mips_multi_num_insns = 0;
}
static struct mips_multi_member *
mips_multi_add (void)
{
- return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0);
+ mips_multi_member empty;
+ return mips_multi_members.safe_push (empty);
}
/* Add a normal insn with the given asm format to the current multi-insn
static unsigned int
mips_multi_last_index (void)
{
- return VEC_length (mips_multi_member, mips_multi_members) - 1;
+ return mips_multi_members.length () - 1;
}
/* Add a copy of an existing instruction to the current multi-insn
struct mips_multi_member *member;
member = mips_multi_add ();
- memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i),
- sizeof (*member));
+ memcpy (member, &mips_multi_members[i], sizeof (*member));
gcc_assert (!member->is_label_p);
}
static void
mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
{
- VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x;
+ mips_multi_members[i].operands[op] = x;
}
/* Write out the asm code for the current multi-insn sequence. */
struct mips_multi_member *member;
unsigned int i;
- FOR_EACH_VEC_ELT (mips_multi_member, mips_multi_members, i, member)
+ FOR_EACH_VEC_ELT (mips_multi_members, i, member)
if (member->is_label_p)
fprintf (asm_out_file, "%s\n", member->format);
else
return simplify_gen_subreg (word_mode, op, mode, byte);
}
-/* Return true if a 64-bit move from SRC to DEST should be split into two. */
+/* Return true if SRC should be moved into DEST using "MULT $0, $0".
+ SPLIT_TYPE is the condition under which moves should be split. */
+
+static bool
+mips_mult_move_p (rtx dest, rtx src, enum mips_split_type split_type)
+{
+ return ((split_type != SPLIT_FOR_SPEED
+ || mips_tuning_info.fast_mult_zero_zero_p)
+ && src == const0_rtx
+ && REG_P (dest)
+ && GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
+ && (ISA_HAS_DSP_MULT
+ ? ACC_REG_P (REGNO (dest))
+ : MD_REG_P (REGNO (dest))));
+}
+
+/* Return true if a move from SRC to DEST should be split into two.
+ SPLIT_TYPE describes the split condition. */
bool
-mips_split_64bit_move_p (rtx dest, rtx src)
+mips_split_move_p (rtx dest, rtx src, enum mips_split_type split_type)
{
- if (TARGET_64BIT)
+ /* Check whether the move can be done using some variant of MULT $0,$0. */
+ if (mips_mult_move_p (dest, src, split_type))
return false;
/* FPR-to-FPR moves can be done in a single instruction, if they're
allowed at all. */
- if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
+ unsigned int size = GET_MODE_SIZE (GET_MODE (dest));
+ if (size == 8 && FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
return false;
/* Check for floating-point loads and stores. */
- if (ISA_HAS_LDC1_SDC1)
+ if (size == 8 && ISA_HAS_LDC1_SDC1)
{
if (FP_REG_RTX_P (dest) && MEM_P (src))
return false;
if (FP_REG_RTX_P (src) && MEM_P (dest))
return false;
}
- return true;
+
+ /* Otherwise split all multiword moves. */
+ return size > UNITS_PER_WORD;
}
-/* Split a doubleword move from SRC to DEST. On 32-bit targets,
- this function handles 64-bit moves for which mips_split_64bit_move_p
- holds. For 64-bit targets, this function handles 128-bit moves. */
+/* Split a move from SRC to DEST, given that mips_split_move_p holds.
+ SPLIT_TYPE describes the split condition. */
void
-mips_split_doubleword_move (rtx dest, rtx src)
+mips_split_move (rtx dest, rtx src, enum mips_split_type split_type)
{
rtx low_dest;
+ gcc_checking_assert (mips_split_move_p (dest, src, split_type));
if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
{
if (!TARGET_64BIT && GET_MODE (dest) == DImode)
}
}
}
+
+/* Return the split type for instruction INSN. */
+
+static enum mips_split_type
+mips_insn_split_type (rtx insn)
+{
+ basic_block bb = BLOCK_FOR_INSN (insn);
+ if (bb)
+ {
+ if (optimize_bb_for_speed_p (bb))
+ return SPLIT_FOR_SPEED;
+ else
+ return SPLIT_FOR_SIZE;
+ }
+ /* Once CFG information has been removed, we should trust the optimization
+ decisions made by previous passes and only split where necessary. */
+ return SPLIT_IF_NECESSARY;
+}
+
+/* Return true if a move from SRC to DEST in INSN should be split. */
+
+bool
+mips_split_move_insn_p (rtx dest, rtx src, rtx insn)
+{
+ return mips_split_move_p (dest, src, mips_insn_split_type (insn));
+}
+
+/* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
+ holds. */
+
+void
+mips_split_move_insn (rtx dest, rtx src, rtx insn)
+{
+ mips_split_move (dest, src, mips_insn_split_type (insn));
+}
\f
/* Return the appropriate instructions to move SRC into DEST. Assume
that SRC is operand 1 and DEST is operand 0. */
mode = GET_MODE (dest);
dbl_p = (GET_MODE_SIZE (mode) == 8);
- if (dbl_p && mips_split_64bit_move_p (dest, src))
+ if (mips_split_move_p (dest, src, SPLIT_IF_NECESSARY))
return "#";
if ((src_code == REG && GP_REG_P (REGNO (src)))
if (GP_REG_P (REGNO (dest)))
return "move\t%0,%z1";
+ if (mips_mult_move_p (dest, src, SPLIT_IF_NECESSARY))
+ {
+ if (ISA_HAS_DSP_MULT)
+ return "mult\t%q0,%.,%.";
+ else
+ return "mult\t%.,%.";
+ }
+
/* Moves to HI are handled by special .md insns. */
if (REGNO (dest) == LO_REGNUM)
return "mtlo\t%z1";
retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
return dbl_p ? retval : retval + 1;
}
-
- if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
- return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
}
if (src_code == MEM)
}
}
-/* Convert a comparison into something that can be used in a branch or
- conditional move. On entry, *OP0 and *OP1 are the values being
- compared and *CODE is the code used to compare them.
+/* Allocate a floating-point condition-code register of mode MODE.
- Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
- If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
- otherwise any standard branch condition can be used. The standard branch
- conditions are:
+ These condition code registers are used for certain kinds
+ of compound operation, such as compare and branches, vconds,
+ and built-in functions. At expand time, their use is entirely
+ controlled by MIPS-specific code and is entirely internal
+ to these compound operations.
- - EQ or NE between two registers.
- - any comparison between a register and zero. */
+ We could (and did in the past) expose condition-code values
+ as pseudo registers and leave the register allocator to pick
+ appropriate registers. The problem is that it is not practically
+ possible for the rtl optimizers to guarantee that no spills will
+ be needed, even when AVOID_CCMODE_COPIES is defined. We would
+ therefore need spill and reload sequences to handle the worst case.
-static void
-mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
+ Although such sequences do exist, they are very expensive and are
+ not something we'd want to use. This is especially true of CCV2 and
+ CCV4, where all the shuffling would greatly outweigh whatever benefit
+ the vectorization itself provides.
+
+ The main benefit of having more than one condition-code register
+ is to allow the pipelining of operations, especially those involving
+ comparisons and conditional moves. We don't really expect the
+ registers to be live for long periods, and certainly never want
+ them to be live across calls.
+
+ Also, there should be no penalty attached to using all the available
+ registers. They are simply bits in the same underlying FPU control
+ register.
+
+ We therefore expose the hardware registers from the outset and use
+ a simple round-robin allocation scheme. */
+
+static rtx
+mips_allocate_fcc (enum machine_mode mode)
+{
+ unsigned int regno, count;
+
+ gcc_assert (TARGET_HARD_FLOAT && ISA_HAS_8CC);
+
+ if (mode == CCmode)
+ count = 1;
+ else if (mode == CCV2mode)
+ count = 2;
+ else if (mode == CCV4mode)
+ count = 4;
+ else
+ gcc_unreachable ();
+
+ cfun->machine->next_fcc += -cfun->machine->next_fcc & (count - 1);
+ if (cfun->machine->next_fcc > ST_REG_LAST - ST_REG_FIRST)
+ cfun->machine->next_fcc = 0;
+ regno = ST_REG_FIRST + cfun->machine->next_fcc;
+ cfun->machine->next_fcc += count;
+ return gen_rtx_REG (mode, regno);
+}
+
+/* Convert a comparison into something that can be used in a branch or
+ conditional move. On entry, *OP0 and *OP1 are the values being
+ compared and *CODE is the code used to compare them.
+
+ Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
+ If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
+ otherwise any standard branch condition can be used. The standard branch
+ conditions are:
+
+ - EQ or NE between two registers.
+ - any comparison between a register and zero. */
+
+static void
+mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
{
rtx cmp_op0 = *op0;
rtx cmp_op1 = *op1;
cmp_code = *code;
*code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
*op0 = (ISA_HAS_8CC
- ? gen_reg_rtx (CCmode)
+ ? mips_allocate_fcc (CCmode)
: gen_rtx_REG (CCmode, FPSW_REGNUM));
*op1 = const0_rtx;
mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
bool reversed_p;
reversed_p = mips_reversed_fp_cond (&cond);
- cmp_result = gen_reg_rtx (CCV2mode);
+ cmp_result = mips_allocate_fcc (CCV2mode);
emit_insn (gen_scc_ps (cmp_result,
gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
if (reversed_p)
/* The EABI conventions have traditionally been defined in terms
of TYPE_MODE, regardless of the actual type. */
info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
- || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
+ || mode == V2SFmode)
&& GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
break;
|| SCALAR_FLOAT_TYPE_P (type)
|| VECTOR_FLOAT_TYPE_P (type))
&& (GET_MODE_CLASS (mode) == MODE_FLOAT
- || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
+ || mode == V2SFmode)
&& GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
break;
&& (type == 0 || FLOAT_TYPE_P (type))
&& (GET_MODE_CLASS (mode) == MODE_FLOAT
|| GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
- || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
+ || mode == V2SFmode)
&& GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
/* ??? According to the ABI documentation, the real and imaginary
/* Implement TARGET_STRICT_ARGUMENT_NAMING. */
static bool
-mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
+mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
{
return !TARGET_OLDABI;
}
/* Implement TARGET_FUNCTION_ARG. */
static rtx
-mips_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
+mips_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
const_tree type, bool named)
{
+ CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
struct mips_arg_info info;
/* We will be called with a mode of VOIDmode after the last argument
&& type != 0
&& TREE_CODE (type) == RECORD_TYPE
&& TYPE_SIZE_UNIT (type)
- && host_integerp (TYPE_SIZE_UNIT (type), 1))
+ && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type)))
{
tree field;
if (TREE_CODE (field) == FIELD_DECL
&& SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
&& TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
- && host_integerp (bit_position (field), 0)
+ && tree_fits_shwi_p (bit_position (field))
&& int_bit_position (field) % BITS_PER_WORD == 0)
break;
/* Implement TARGET_FUNCTION_ARG_ADVANCE. */
static void
-mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
+mips_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
const_tree type, bool named)
{
+ CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
struct mips_arg_info info;
mips_get_arg_info (&info, cum, mode, type, named);
/* Implement TARGET_ARG_PARTIAL_BYTES. */
static int
-mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
+mips_arg_partial_bytes (cumulative_args_t cum,
enum machine_mode mode, tree type, bool named)
{
struct mips_arg_info info;
- mips_get_arg_info (&info, cum, mode, type, named);
+ mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named);
return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
}
/* Return nonzero when an argument must be passed by reference. */
static bool
-mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
+mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
enum machine_mode mode, const_tree type,
bool named ATTRIBUTE_UNUSED)
{
/* Implement TARGET_CALLEE_COPIES. */
static bool
-mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
+mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
enum machine_mode mode ATTRIBUTE_UNUSED,
const_tree type ATTRIBUTE_UNUSED, bool named)
{
mips_return_mode_in_fpr_p (enum machine_mode mode)
{
return ((GET_MODE_CLASS (mode) == MODE_FLOAT
- || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
+ || mode == V2SFmode
|| GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
&& GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
}
}
-/* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
- VALTYPE is the return type and MODE is VOIDmode. For libcalls,
- VALTYPE is null and MODE is the mode of the return value. */
+/* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
+ For normal calls, VALTYPE is the return type and MODE is VOIDmode.
+ For libcalls, VALTYPE is null and MODE is the mode of the return value. */
-rtx
-mips_function_value (const_tree valtype, const_tree func, enum machine_mode mode)
+static rtx
+mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
+ enum machine_mode mode)
{
if (valtype)
{
tree fields[2];
int unsigned_p;
+ const_tree func;
+
+ if (fn_decl_or_type && DECL_P (fn_decl_or_type))
+ func = fn_decl_or_type;
+ else
+ func = NULL;
mode = TYPE_MODE (valtype);
unsigned_p = TYPE_UNSIGNED (valtype);
return gen_rtx_REG (mode, GP_RETURN);
}
+/* Implement TARGET_FUNCTION_VALUE. */
+
+static rtx
+mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
+ bool outgoing ATTRIBUTE_UNUSED)
+{
+ return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
+}
+
+/* Implement TARGET_LIBCALL_VALUE. */
+
+static rtx
+mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
+{
+ return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
+}
+
+/* Implement TARGET_FUNCTION_VALUE_REGNO_P.
+
+ On the MIPS, R2 R3 and F0 F2 are the only register thus used.
+ Currently, R2 and F0 are only implemented here (C has no complex type). */
+
+static bool
+mips_function_value_regno_p (const unsigned int regno)
+{
+ if (regno == GP_RETURN
+ || regno == FP_RETURN
+ || (LONG_DOUBLE_TYPE_SIZE == 128
+ && FP_RETURN != GP_RETURN
+ && regno == FP_RETURN + 2))
+ return true;
+
+ return false;
+}
+
/* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
all BLKmode objects are returned in memory. Under the n32, n64
and embedded ABIs, small structures are returned in a register.
/* Implement TARGET_SETUP_INCOMING_VARARGS. */
static void
-mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
+mips_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
tree type, int *pretend_size ATTRIBUTE_UNUSED,
int no_rtl)
{
/* The caller has advanced CUM up to, but not beyond, the last named
argument. Advance a local copy of CUM past the last "real" named
argument, to find out how many registers are left over. */
- local_cum = *cum;
- mips_function_arg_advance (&local_cum, mode, type, true);
+ local_cum = *get_cumulative_args (cum);
+ mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type,
+ true);
/* Found out how many registers we need to save. */
gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
{
rtx ptr, mem;
- ptr = plus_constant (virtual_incoming_args_rtx,
+ ptr = plus_constant (Pmode, virtual_incoming_args_rtx,
REG_PARM_STACK_SPACE (cfun->decl)
- gp_saved * UNITS_PER_WORD);
mem = gen_frame_mem (BLKmode, ptr);
{
rtx ptr, mem;
- ptr = plus_constant (virtual_incoming_args_rtx, off);
+ ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off);
mem = gen_frame_mem (mode, ptr);
set_mem_alias_set (mem, get_varargs_alias_set ());
mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
layout_type (record);
return record;
}
- else if (TARGET_IRIX6)
- /* On IRIX 6, this type is 'char *'. */
- return build_pointer_type (char_type_node);
else
/* Otherwise, we use 'void *'. */
return ptr_type_node;
words used by named arguments. */
t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
if (cum->stack_words > 0)
- t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
- size_int (cum->stack_words * UNITS_PER_WORD));
+ t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD);
t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
fpr_offset &= -UNITS_PER_FPVALUE;
if (fpr_offset)
- t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
- size_int (-fpr_offset));
+ t = fold_build_pointer_plus_hwi (t, -fpr_offset);
t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
}
else
{
- nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
+ nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size);
std_expand_builtin_va_start (valist, nextarg);
}
}
+/* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
+ types as well. */
+
+static tree
+mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
+ gimple_seq *post_p)
+{
+ tree addr, t, type_size, rounded_size, valist_tmp;
+ unsigned HOST_WIDE_INT align, boundary;
+ bool indirect;
+
+ indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
+ if (indirect)
+ type = build_pointer_type (type);
+
+ align = PARM_BOUNDARY / BITS_PER_UNIT;
+ boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type);
+
+ /* When we align parameter on stack for caller, if the parameter
+ alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
+ aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
+ here with caller. */
+ if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
+ boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
+
+ boundary /= BITS_PER_UNIT;
+
+ /* Hoist the valist value into a temporary for the moment. */
+ valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
+
+ /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
+ requires greater alignment, we must perform dynamic alignment. */
+ if (boundary > align)
+ {
+ t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
+ fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
+ gimplify_and_add (t, pre_p);
+
+ t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
+ fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist),
+ valist_tmp,
+ build_int_cst (TREE_TYPE (valist), -boundary)));
+ gimplify_and_add (t, pre_p);
+ }
+ else
+ boundary = align;
+
+ /* If the actual alignment is less than the alignment of the type,
+ adjust the type accordingly so that we don't assume strict alignment
+ when dereferencing the pointer. */
+ boundary *= BITS_PER_UNIT;
+ if (boundary < TYPE_ALIGN (type))
+ {
+ type = build_variant_type_copy (type);
+ TYPE_ALIGN (type) = boundary;
+ }
+
+ /* Compute the rounded size of the type. */
+ type_size = size_in_bytes (type);
+ rounded_size = round_up (type_size, align);
+
+ /* Reduce rounded_size so it's sharable with the postqueue. */
+ gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue);
+
+ /* Get AP. */
+ addr = valist_tmp;
+ if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size))
+ {
+ /* Small args are padded downward. */
+ t = fold_build2_loc (input_location, GT_EXPR, sizetype,
+ rounded_size, size_int (align));
+ t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node,
+ size_binop (MINUS_EXPR, rounded_size, type_size));
+ addr = fold_build_pointer_plus (addr, t);
+ }
+
+ /* Compute new value for AP. */
+ t = fold_build_pointer_plus (valist_tmp, rounded_size);
+ t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
+ gimplify_and_add (t, pre_p);
+
+ addr = fold_convert (build_pointer_type (type), addr);
+
+ if (indirect)
+ addr = build_va_arg_indirect_ref (addr);
+
+ return build_va_arg_indirect_ref (addr);
+}
+
/* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
static tree
type = build_pointer_type (type);
if (!EABI_FLOAT_VARARGS_P)
- addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
+ addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
else
{
tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
}
/* [2] Emit code to branch if off == 0. */
- t = build2 (NE_EXPR, boolean_type_node, off,
+ t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off),
build_int_cst (TREE_TYPE (off), 0));
addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
t = fold_convert (sizetype, t);
t = fold_build1 (NEGATE_EXPR, sizetype, t);
- t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
+ t = fold_build_pointer_plus (top, t);
if (BYTES_BIG_ENDIAN && rsize > size)
- {
- u = size_int (rsize - size);
- t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
- }
+ t = fold_build_pointer_plus_hwi (t, rsize - size);
COND_EXPR_THEN (addr) = t;
if (osize > UNITS_PER_WORD)
{
/* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
- u = size_int (osize - 1);
- t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl),
- unshare_expr (ovfl), u);
- t = fold_convert (sizetype, t);
- u = size_int (-osize);
- t = build2 (BIT_AND_EXPR, sizetype, t, u);
- t = fold_convert (TREE_TYPE (ovfl), t);
+ t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1);
+ u = build_int_cst (TREE_TYPE (t), -osize);
+ t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
unshare_expr (ovfl), t);
}
u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
if (BYTES_BIG_ENDIAN && osize > size)
- {
- u = size_int (osize - size);
- t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
- }
+ t = fold_build_pointer_plus_hwi (t, osize - size);
/* String [9] and [10, 11] together. */
if (align)
return addr;
}
\f
+/* Declare a unique, locally-binding function called NAME, then start
+ its definition. */
+
+static void
+mips_start_unique_function (const char *name)
+{
+ tree decl;
+
+ decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
+ get_identifier (name),
+ build_function_type_list (void_type_node, NULL_TREE));
+ DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
+ NULL_TREE, void_type_node);
+ TREE_PUBLIC (decl) = 1;
+ TREE_STATIC (decl) = 1;
+
+ cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
+
+ targetm.asm_out.unique_section (decl, 0);
+ switch_to_section (get_named_section (decl, NULL, 0));
+
+ targetm.asm_out.globalize_label (asm_out_file, name);
+ fputs ("\t.hidden\t", asm_out_file);
+ assemble_name (asm_out_file, name);
+ putc ('\n', asm_out_file);
+}
+
/* Start a definition of function NAME. MIPS16_P indicates whether the
function contains MIPS16 code. */
else
fprintf (asm_out_file, "\t.set\tnomips16\n");
+ if (TARGET_MICROMIPS)
+ fprintf (asm_out_file, "\t.set\tmicromips\n");
+#ifdef HAVE_GAS_MICROMIPS
+ else
+ fprintf (asm_out_file, "\t.set\tnomicromips\n");
+#endif
+
if (!flag_inhibit_size_directive)
{
fputs ("\t.ent\t", asm_out_file);
fputs ("\n", asm_out_file);
}
}
+
+/* If *STUB_PTR points to a stub, output a comdat-style definition for it,
+ then free *STUB_PTR. */
+
+static void
+mips_finish_stub (mips_one_only_stub **stub_ptr)
+{
+ mips_one_only_stub *stub = *stub_ptr;
+ if (!stub)
+ return;
+
+ const char *name = stub->get_name ();
+ mips_start_unique_function (name);
+ mips_start_function_definition (name, false);
+ stub->output_body ();
+ mips_end_function_definition (name);
+ delete stub;
+ *stub_ptr = 0;
+}
\f
/* Return true if calls to X can use R_MIPS_CALL* relocations. */
}
}
\f
+struct local_alias_traits : default_hashmap_traits
+{
+ static hashval_t hash (rtx);
+ static bool equal_keys (rtx, rtx);
+};
+
/* Each locally-defined hard-float MIPS16 function has a local symbol
associated with it. This hash table maps the function symbol (FUNC)
to the local symbol (LOCAL). */
-struct GTY(()) mips16_local_alias {
- rtx func;
- rtx local;
-};
-static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
+static GTY (()) hash_map<rtx, rtx, local_alias_traits> *mips16_local_aliases;
/* Hash table callbacks for mips16_local_aliases. */
-static hashval_t
-mips16_local_aliases_hash (const void *entry)
+hashval_t
+local_alias_traits::hash (rtx func)
{
- const struct mips16_local_alias *alias;
-
- alias = (const struct mips16_local_alias *) entry;
- return htab_hash_string (XSTR (alias->func, 0));
+ return htab_hash_string (XSTR (func, 0));
}
-static int
-mips16_local_aliases_eq (const void *entry1, const void *entry2)
+bool
+local_alias_traits::equal_keys (rtx func1, rtx func2)
{
- const struct mips16_local_alias *alias1, *alias2;
-
- alias1 = (const struct mips16_local_alias *) entry1;
- alias2 = (const struct mips16_local_alias *) entry2;
- return rtx_equal_p (alias1->func, alias2->func);
+ return rtx_equal_p (func1, func2);
}
/* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
static rtx
mips16_local_alias (rtx func)
{
- struct mips16_local_alias *alias, tmp_alias;
- void **slot;
-
/* Create the hash table if this is the first call. */
if (mips16_local_aliases == NULL)
- mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
- mips16_local_aliases_eq, NULL);
+ mips16_local_aliases
+ = hash_map<rtx, rtx, local_alias_traits>::create_ggc (37);
/* Look up the function symbol, creating a new entry if need be. */
- tmp_alias.func = func;
- slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
+ bool existed;
+ rtx *slot = &mips16_local_aliases->get_or_insert (func, &existed);
gcc_assert (slot != NULL);
- alias = (struct mips16_local_alias *) *slot;
- if (alias == NULL)
+ if (!existed)
{
const char *func_name, *local_name;
rtx local;
SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
/* Create a new structure to represent the mapping. */
- alias = ggc_alloc_mips16_local_alias ();
- alias->func = func;
- alias->local = local;
- *slot = alias;
+ *slot = local;
}
- return alias->local;
+ return *slot;
}
\f
/* A chained list of functions for which mips16_build_call_stub has already
};
static struct mips16_stub *mips16_stubs;
-/* Return a SYMBOL_REF for a MIPS16 function called NAME. */
-
-static rtx
-mips16_stub_function (const char *name)
-{
- rtx x;
-
- x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
- SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
- return x;
-}
-
/* Return the two-character string that identifies floating-point
return mode MODE in the name of a MIPS16 function stub. */
else
mips_output_64bit_xfer (direction, gparg, fparg);
- mips_function_arg_advance (&cum, mode, NULL, true);
+ mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true);
}
}
/* Build a decl for the stub. */
stubdecl = build_decl (BUILTINS_LOCATION,
FUNCTION_DECL, get_identifier (stubname),
- build_function_type (void_type_node, NULL_TREE));
- DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
+ build_function_type_list (void_type_node, NULL_TREE));
+ set_decl_section_name (stubdecl, secname);
DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
RESULT_DECL, NULL_TREE, void_type_node);
automatically redirects the JAL to the stub, otherwise the JAL
continues to call FN directly. */
-static rtx
+static rtx_insn *
mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
{
const char *fnname;
bool fp_ret_p;
struct mips16_stub *l;
- rtx insn, fn;
+ rtx_insn *insn;
+ rtx pattern, fn;
/* We don't need to do anything if we aren't in MIPS16 mode, or if
we were invoked with the -msoft-float option. */
if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
- return NULL_RTX;
+ return NULL;
/* Figure out whether the value might come back in a floating-point
register. */
arguments and the value will not be returned in a floating-point
register. */
if (fp_code == 0 && !fp_ret_p)
- return NULL_RTX;
+ return NULL;
/* We don't need to do anything if this is a call to a special
MIPS16 support function. */
fn = *fn_ptr;
if (mips16_stub_function_p (fn))
- return NULL_RTX;
+ return NULL;
+
+ /* If we're calling a locally-defined MIPS16 function, we know that
+ it will return values in both the "soft-float" and "hard-float"
+ registers. There is no need to use a stub to move the latter
+ to the former. */
+ if (fp_code == 0 && mips16_local_function_p (fn))
+ return NULL;
/* This code will only work for o32 and o64 abis. The other ABI's
require more sophisticated support. */
|| !call_insn_operand (fn, VOIDmode))
{
char buf[30];
- rtx stub_fn, insn, addr;
+ rtx stub_fn, addr;
+ rtx_insn *insn;
bool lazy_p;
/* If this is a locally-defined and locally-binding function,
if (mips16_local_function_p (fn))
{
*fn_ptr = mips16_local_alias (fn);
- return NULL_RTX;
+ return NULL;
}
/* Create a SYMBOL_REF for the libgcc.a function. */
stubid = get_identifier (stubname);
stubdecl = build_decl (BUILTINS_LOCATION,
FUNCTION_DECL, stubid,
- build_function_type (void_type_node, NULL_TREE));
- DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
+ build_function_type_list (void_type_node,
+ NULL_TREE));
+ set_decl_section_name (stubdecl, secname);
DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
RESULT_DECL, NULL_TREE,
void_type_node);
assemble_start_function (stubdecl, stubname);
mips_start_function_definition (stubname, false);
- if (!fp_ret_p)
+ if (fp_ret_p)
+ {
+ fprintf (asm_out_file, "\t.cfi_startproc\n");
+
+ /* Create a fake CFA 4 bytes below the stack pointer.
+ This works around unwinders (like libgcc's) that expect
+ the CFA for non-signal frames to be unique. */
+ fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n");
+
+ /* "Save" $sp in itself so we don't use the fake CFA.
+ This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
+ fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n");
+ }
+ else
{
/* Load the address of the MIPS16 function into $25. Do this
first so that targets with coprocessor interlocks can use
registers. */
mips_output_args_xfer (fp_code, 't');
- if (!fp_ret_p)
- {
- /* Jump to the previously-loaded address. */
- output_asm_insn ("jr\t%^", NULL);
- }
- else
+ if (fp_ret_p)
{
/* Save the return address in $18 and call the non-MIPS16 function.
The stub's caller knows that $18 might be clobbered, even though
fprintf (asm_out_file, "\tmove\t%s,%s\n",
reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
+ fprintf (asm_out_file, "\t.cfi_register 31,18\n");
/* Move the result from floating-point registers to
general registers. */
gcc_unreachable ();
}
fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
+ fprintf (asm_out_file, "\t.cfi_endproc\n");
+ }
+ else
+ {
+ /* Jump to the previously-loaded address. */
+ output_asm_insn ("jr\t%^", NULL);
}
#ifdef ASM_DECLARE_FUNCTION_SIZE
error ("cannot handle inconsistent calls to %qs", fnname);
if (retval == NULL_RTX)
- insn = gen_call_internal_direct (fn, args_size);
+ pattern = gen_call_internal_direct (fn, args_size);
else
- insn = gen_call_value_internal_direct (retval, fn, args_size);
- insn = mips_emit_call_insn (insn, fn, fn, false);
+ pattern = gen_call_value_internal_direct (retval, fn, args_size);
+ insn = mips_emit_call_insn (pattern, fn, fn, false);
/* If we are calling a stub which handles a floating-point return
value, we need to arrange to save $18 in the prologue. We do this
Return the call itself. */
-rtx
+rtx_insn *
mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
rtx args_size, rtx aux, bool lazy_p)
{
- rtx orig_addr, pattern, insn;
+ rtx orig_addr, pattern;
+ rtx_insn *insn;
int fp_code;
fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
return insn;
}
- ;
+
orig_addr = addr;
if (!call_insn_operand (addr, VOIDmode))
{
{
emit_call_insn (call_pattern);
if (!find_reg_note (insn, REG_NORETURN, 0))
- /* Pick a temporary register that is suitable for both MIPS16 and
- non-MIPS16 code. $4 and $5 are used for returning complex double
- values in soft-float code, so $6 is the first suitable candidate. */
- mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
+ mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode,
+ POST_CALL_TMP_REG));
+}
+
+/* Return true if a call to DECL may need to use JALX. */
+
+static bool
+mips_call_may_need_jalx_p (tree decl)
+{
+ /* If the current translation unit would use a different mode for DECL,
+ assume that the call needs JALX. */
+ if (mips_get_compress_mode (decl) != TARGET_COMPRESSION)
+ return true;
+
+ /* mips_get_compress_mode is always accurate for locally-binding
+ functions in the current translation unit. */
+ if (!DECL_EXTERNAL (decl) && targetm.binds_local_p (decl))
+ return false;
+
+ /* When -minterlink-compressed is in effect, assume that functions
+ could use a different encoding mode unless an attribute explicitly
+ tells us otherwise. */
+ if (TARGET_INTERLINK_COMPRESSED)
+ {
+ if (!TARGET_COMPRESSION
+ && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl)) ==0)
+ return true;
+ if (TARGET_COMPRESSION
+ && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl)) == 0)
+ return true;
+ }
+
+ return false;
}
/* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
return false;
- /* We can't do a sibcall if the called function is a MIPS16 function
- because there is no direct "jx" instruction equivalent to "jalx" to
- switch the ISA mode. We only care about cases where the sibling
- and normal calls would both be direct. */
+ /* Direct Js are only possible to functions that use the same ISA encoding.
+ There is no JX counterpoart of JALX. */
if (decl
- && mips_use_mips16_mode_p (decl)
- && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
+ && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode)
+ && mips_call_may_need_jalx_p (decl))
return false;
- /* When -minterlink-mips16 is in effect, assume that non-locally-binding
- functions could be MIPS16 ones unless an attribute explicitly tells
- us otherwise. */
- if (TARGET_INTERLINK_MIPS16
- && decl
- && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
- && !mips_nomips16_decl_p (decl)
- && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
+ /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
+ require $gp to be valid on entry, so sibcalls can only use stubs
+ if $gp is call-clobbered. */
+ if (decl
+ && TARGET_CALL_SAVED_GP
+ && !TARGET_ABICALLS_PIC0
+ && !targetm.binds_local_p (decl))
return false;
/* Otherwise OK. */
return true;
}
\f
-/* Emit code to move general operand SRC into condition-code
- register DEST given that SCRATCH is a scratch TFmode FPR.
- The sequence is:
+/* Implement MOVE_BY_PIECES_P. */
- FP1 = SRC
- FP2 = 0.0f
- DEST = FP2 < FP1
+bool
+mips_move_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
+{
+ if (HAVE_movmemsi)
+ {
+ /* movmemsi is meant to generate code that is at least as good as
+ move_by_pieces. However, movmemsi effectively uses a by-pieces
+ implementation both for moves smaller than a word and for
+ word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
+ bytes. We should allow the tree-level optimisers to do such
+ moves by pieces, as it often exposes other optimization
+ opportunities. We might as well continue to use movmemsi at
+ the rtl level though, as it produces better code when
+ scheduling is disabled (such as at -O). */
+ if (currently_expanding_to_rtl)
+ return false;
+ if (align < BITS_PER_WORD)
+ return size < UNITS_PER_WORD;
+ return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT;
+ }
+ /* The default value. If this becomes a target hook, we should
+ call the default definition instead. */
+ return (move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1)
+ < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
+}
- where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
+/* Implement STORE_BY_PIECES_P. */
-void
-mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
+bool
+mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
{
- rtx fp1, fp2;
+ /* Storing by pieces involves moving constants into registers
+ of size MIN (ALIGN, BITS_PER_WORD), then storing them.
+ We need to decide whether it is cheaper to load the address of
+ constant data into a register and use a block move instead. */
+
+ /* If the data is only byte aligned, then:
+
+ (a1) A block move of less than 4 bytes would involve three 3 LBs and
+ 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
+ instead.
+
+ (a2) A block move of 4 bytes from aligned source data can use an
+ LW/SWL/SWR sequence. This is often better than the 4 LIs and
+ 4 SBs that we would generate when storing by pieces. */
+ if (align <= BITS_PER_UNIT)
+ return size < 4;
+
+ /* If the data is 2-byte aligned, then:
+
+ (b1) A block move of less than 4 bytes would use a combination of LBs,
+ LHs, SBs and SHs. We get better code by using single-instruction
+ LIs, SBs and SHs instead.
+
+ (b2) A block move of 4 bytes from aligned source data would again use
+ an LW/SWL/SWR sequence. In most cases, loading the address of
+ the source data would require at least one extra instruction.
+ It is often more efficient to use 2 single-instruction LIs and
+ 2 SHs instead.
+
+ (b3) A block move of up to 3 additional bytes would be like (b1).
- /* Change the source to SFmode. */
- if (MEM_P (src))
- src = adjust_address (src, SFmode, 0);
- else if (REG_P (src) || GET_CODE (src) == SUBREG)
- src = gen_rtx_REG (SFmode, true_regnum (src));
+ (b4) A block move of 8 bytes from aligned source data can use two
+ LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
+ sequences are better than the 4 LIs and 4 SHs that we'd generate
+ when storing by pieces.
- fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
- fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
+ The reasoning for higher alignments is similar:
- mips_emit_move (copy_rtx (fp1), src);
- mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
- emit_insn (gen_slt_sf (dest, fp2, fp1));
+ (c1) A block move of less than 4 bytes would be the same as (b1).
+
+ (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
+ loading the address of the source data would typically require
+ at least one extra instruction. It is generally better to use
+ LUI/ORI/SW instead.
+
+ (c3) A block move of up to 3 additional bytes would be like (b1).
+
+ (c4) A block move of 8 bytes can use two LW/SW sequences or a single
+ LD/SD sequence, and in these cases we've traditionally preferred
+ the memory copy over the more bulky constant moves. */
+ return size < 8;
}
-\f
+
/* Emit straight-line code to move LENGTH bytes from SRC to DEST.
Assume that the areas do not overlap. */
else
{
rtx part = adjust_address (src, BLKmode, offset);
- if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
+ set_mem_size (part, delta);
+ if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0, 0))
gcc_unreachable ();
}
}
else
{
rtx part = adjust_address (dest, BLKmode, offset);
+ set_mem_size (part, delta);
if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
gcc_unreachable ();
}
mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
HOST_WIDE_INT bytes_per_iter)
{
- rtx label, src_reg, dest_reg, final_src, test;
+ rtx_code_label *label;
+ rtx src_reg, dest_reg, final_src, test;
HOST_WIDE_INT leftover;
leftover = length % bytes_per_iter;
mips_block_move_straight (dest, src, bytes_per_iter);
/* Move on to the next block. */
- mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
- mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
+ mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
+ mips_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
/* Emit the loop condition. */
test = gen_rtx_NE (VOIDmode, src_reg, final_src);
void
mips_expand_synci_loop (rtx begin, rtx end)
{
- rtx inc, label, end_label, cmp_result, mask, length;
+ rtx inc, cmp_result, mask, length;
+ rtx_code_label *label, *end_label;
/* Create end_label. */
end_label = gen_label_rtx ();
/* Load INC with the cache line size (rdhwr INC,$1). */
inc = gen_reg_rtx (Pmode);
- emit_insn (Pmode == SImode
- ? gen_rdhwr_synci_step_si (inc)
- : gen_rdhwr_synci_step_di (inc));
+ emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc)));
/* Check if inc is 0. */
cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
length = mips_force_binary (Pmode, MINUS, end, begin);
/* Loop back to here. */
- label = gen_label_rtx ();
+ label = gen_label_rtx ();
emit_label (label);
emit_insn (gen_synci (begin));
}
/* Return true if it is possible to use left/right accesses for a
- bitfield of WIDTH bits starting BITPOS bits into *OP. When
- returning true, update *OP, *LEFT and *RIGHT as follows:
-
- *OP is a BLKmode reference to the whole field.
+ bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
+ When returning true, update *LEFT and *RIGHT as follows:
*LEFT is a QImode reference to the first byte if big endian or
the last byte if little endian. This address can be used in the
can be used in the patterning right-side instruction. */
static bool
-mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
+mips_get_unaligned_mem (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
rtx *left, rtx *right)
{
rtx first, last;
- /* Check that the operand really is a MEM. Not all the extv and
- extzv predicates are checked. */
- if (!MEM_P (*op))
- return false;
-
/* Check that the size is valid. */
if (width != 32 && (!TARGET_64BIT || width != 64))
return false;
/* Reject aligned bitfields: we want to use a normal load or store
instead of a left/right pair. */
- if (MEM_ALIGN (*op) >= width)
+ if (MEM_ALIGN (op) >= width)
return false;
- /* Adjust *OP to refer to the whole field. This also has the effect
- of legitimizing *OP's address for BLKmode, possibly simplifying it. */
- *op = adjust_address (*op, BLKmode, 0);
- set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
-
- /* Get references to both ends of the field. We deliberately don't
- use the original QImode *OP for FIRST since the new BLKmode one
- might have a simpler address. */
- first = adjust_address (*op, QImode, 0);
- last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
+ /* Get references to both ends of the field. */
+ first = adjust_address (op, QImode, 0);
+ last = adjust_address (op, QImode, width / BITS_PER_UNIT - 1);
/* Allocate to LEFT and RIGHT according to endianness. LEFT should
correspond to the MSB and RIGHT to the LSB. */
bool
mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
- HOST_WIDE_INT bitpos)
+ HOST_WIDE_INT bitpos, bool unsigned_p)
{
rtx left, right, temp;
+ rtx dest1 = NULL_RTX;
/* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
- be a paradoxical word_mode subreg. This is the only case in which
- we allow the destination to be larger than the source. */
- if (GET_CODE (dest) == SUBREG
- && GET_MODE (dest) == DImode
- && GET_MODE (SUBREG_REG (dest)) == SImode)
- dest = SUBREG_REG (dest);
-
- /* After the above adjustment, the destination must be the same
- width as the source. */
- if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
- return false;
+ be a DImode, create a new temp and emit a zero extend at the end. */
+ if (GET_MODE (dest) == DImode
+ && REG_P (dest)
+ && GET_MODE_BITSIZE (SImode) == width)
+ {
+ dest1 = dest;
+ dest = gen_reg_rtx (SImode);
+ }
- if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
+ if (!mips_get_unaligned_mem (src, width, bitpos, &left, &right))
return false;
temp = gen_reg_rtx (GET_MODE (dest));
emit_insn (gen_mov_lwl (temp, src, left));
emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
}
+
+ /* If we were loading 32bits and the original register was DI then
+ sign/zero extend into the orignal dest. */
+ if (dest1)
+ {
+ if (unsigned_p)
+ emit_insn (gen_zero_extendsidi2 (dest1, dest));
+ else
+ emit_insn (gen_extendsidi2 (dest1, dest));
+ }
return true;
}
rtx left, right;
enum machine_mode mode;
- if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
+ if (!mips_get_unaligned_mem (dest, width, bitpos, &left, &right))
return false;
mode = mode_for_size (width, MODE_INT, 0);
bool
mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
{
- rtx size;
-
- if (!MEM_P (x))
- return false;
-
- size = MEM_SIZE (x);
- return size && INTVAL (size) == GET_MODE_SIZE (mode);
+ return (MEM_P (x)
+ && MEM_SIZE_KNOWN_P (x)
+ && MEM_SIZE (x) == GET_MODE_SIZE (mode));
}
/* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
{
memset (mips_split_p, '\0', sizeof (mips_split_p));
memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
+ memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p));
memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
- if (ABI_HAS_64BIT_SYMBOLS)
+ if (TARGET_MIPS16_PCREL_LOADS)
+ mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true;
+ else
{
- if (TARGET_EXPLICIT_RELOCS)
+ if (ABI_HAS_64BIT_SYMBOLS)
{
- mips_split_p[SYMBOL_64_HIGH] = true;
- mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
- mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
+ if (TARGET_EXPLICIT_RELOCS)
+ {
+ mips_split_p[SYMBOL_64_HIGH] = true;
+ mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
+ mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
- mips_split_p[SYMBOL_64_MID] = true;
- mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
- mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
+ mips_split_p[SYMBOL_64_MID] = true;
+ mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
+ mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
- mips_split_p[SYMBOL_64_LOW] = true;
- mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
- mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
+ mips_split_p[SYMBOL_64_LOW] = true;
+ mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
+ mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
- mips_split_p[SYMBOL_ABSOLUTE] = true;
- mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
+ mips_split_p[SYMBOL_ABSOLUTE] = true;
+ mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
+ }
}
- }
- else
- {
- if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
+ else
{
- mips_split_p[SYMBOL_ABSOLUTE] = true;
- mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
- mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
-
- mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
+ if (TARGET_EXPLICIT_RELOCS
+ || mips_split_addresses_p ()
+ || TARGET_MIPS16)
+ {
+ mips_split_p[SYMBOL_ABSOLUTE] = true;
+ mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
+ mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
+ }
}
}
mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
- mips_split_p[SYMBOL_DTPREL] = true;
- mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
- mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
-
- mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
+ if (TARGET_MIPS16_PCREL_LOADS)
+ {
+ mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true;
+ mips_use_pcrel_pool_p[SYMBOL_TPREL] = true;
+ }
+ else
+ {
+ mips_split_p[SYMBOL_DTPREL] = true;
+ mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
+ mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
- mips_split_p[SYMBOL_TPREL] = true;
- mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
- mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
+ mips_split_p[SYMBOL_TPREL] = true;
+ mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
+ mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
+ }
+ mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
mips_lo_relocs[SYMBOL_HALF] = "%half(";
}
'^' Print the name of the pic call-through register (t9 or $25).
'+' Print the name of the gp register (usually gp or $28).
'$' Print the name of the stack pointer register (sp or $29).
+ ':' Print "c" to use the compact version if the delay slot is a nop.
+ '!' Print "s" to use the short version if the delay slot contains a
+ 16-bit instruction.
See also mips_init_print_operand_pucnt. */
fputs (reg_names[STACK_POINTER_REGNUM], file);
break;
+ case ':':
+ /* When final_sequence is 0, the delay slot will be a nop. We can
+ use the compact version for microMIPS. */
+ if (final_sequence == 0)
+ putc ('c', file);
+ break;
+
+ case '!':
+ /* If the delay slot instruction is short, then use the
+ compact version. */
+ if (final_sequence == 0
+ || get_attr_length (final_sequence->insn (1)) == 2)
+ putc ('s', file);
+ break;
+
default:
gcc_unreachable ();
break;
{
const char *p;
- for (p = "()[]<>*#/?~.@^+$"; *p; p++)
+ for (p = "()[]<>*#/?~.@^+$:!"; *p; p++)
mips_print_operand_punct[(unsigned char) *p] = true;
}
'D' Print the second part of a double-word register or memory operand.
'L' Print the low-order register in a double-word register operand.
'M' Print high-order register in a double-word register operand.
- 'z' Print $0 if OP is zero, otherwise print OP normally. */
+ 'z' Print $0 if OP is zero, otherwise print OP normally.
+ 'b' Print the address of a memory operand, without offset. */
static void
mips_print_operand (FILE *file, rtx op, int letter)
case 't':
{
int truth = (code == NE) == (letter == 'T');
- fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
+ fputc ("zfnt"[truth * 2 + ST_REG_P (REGNO (XEXP (op, 0)))], file);
}
break;
case MEM:
if (letter == 'D')
- output_address (plus_constant (XEXP (op, 0), 4));
+ output_address (plus_constant (Pmode, XEXP (op, 0), 4));
+ else if (letter == 'b')
+ {
+ gcc_assert (REG_P (XEXP (op, 0)));
+ mips_print_operand (file, XEXP (op, 0), 0);
+ }
else if (letter && letter != 'z')
output_operand_lossage ("invalid use of '%%%c'", letter);
else
if (decl && DECL_SECTION_NAME (decl))
{
- const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
- if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
+ const char *name = DECL_SECTION_NAME (decl);
+ if (DECL_COMDAT_GROUP (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
{
char *rname = ASTRDUP (name);
rname[14] = 'd';
const char *name;
/* Reject anything that isn't in a known small-data section. */
- name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
+ name = DECL_SECTION_NAME (decl);
if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
return false;
offset += cfun->machine->frame.hard_frame_pointer_offset;
}
- /* sdbout_parms does not want this to crash for unrecognized cases. */
-#if 0
- else if (reg != arg_pointer_rtx)
- fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
- addr);
-#endif
-
return offset;
}
\f
return NULL_RTX;
}
+/* DSP ALU can bypass data with no delays for the following pairs. */
+enum insn_code dspalu_bypass_table[][2] =
+{
+ {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc},
+ {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb},
+ {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb},
+ {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb},
+ {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph},
+ {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph},
+ {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph},
+ {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv}
+};
+
+int
+mips_dspalu_bypass_p (rtx out_insn, rtx in_insn)
+{
+ int i;
+ int num_bypass = ARRAY_SIZE (dspalu_bypass_table);
+ enum insn_code out_icode = (enum insn_code) INSN_CODE (out_insn);
+ enum insn_code in_icode = (enum insn_code) INSN_CODE (in_insn);
+
+ for (i = 0; i < num_bypass; i++)
+ {
+ if (out_icode == dspalu_bypass_table[i][0]
+ && in_icode == dspalu_bypass_table[i][1])
+ return true;
+ }
+
+ return false;
+}
/* Implement ASM_OUTPUT_ASCII. */
void
fprintf (stream, "\"\n");
}
-/* Emit either a label, .comm, or .lcomm directive. When using assembler
- macros, mark the symbol as written so that mips_asm_output_external
- won't emit an .extern for it. STREAM is the output file, NAME is the
- name of the symbol, INIT_STRING is the string that should be written
- before the symbol and FINAL_STRING is the string that should be
- written after it. FINAL_STRING is a printf format that consumes the
- remaining arguments. */
+/* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
+ Update *ADDR with the operand that should be printed. */
-void
-mips_declare_object (FILE *stream, const char *name, const char *init_string,
- const char *final_string, ...)
+const char *
+mips_output_tls_reloc_directive (rtx *addr)
{
- va_list ap;
+ enum mips_symbol_type type;
+
+ type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA);
+ *addr = mips_strip_unspec_address (*addr);
+ switch (type)
+ {
+ case SYMBOL_DTPREL:
+ return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0";
+
+ case SYMBOL_TPREL:
+ return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0";
+
+ default:
+ gcc_unreachable ();
+ }
+}
+
+/* Emit either a label, .comm, or .lcomm directive. When using assembler
+ macros, mark the symbol as written so that mips_asm_output_external
+ won't emit an .extern for it. STREAM is the output file, NAME is the
+ name of the symbol, INIT_STRING is the string that should be written
+ before the symbol and FINAL_STRING is the string that should be
+ written after it. FINAL_STRING is a printf format that consumes the
+ remaining arguments. */
+
+void
+mips_declare_object (FILE *stream, const char *name, const char *init_string,
+ const char *final_string, ...)
+{
+ va_list ap;
fputs (init_string, stream);
assemble_name (stream, name);
default_file_start ();
/* Generate a special section to describe the ABI switches used to
- produce the resultant binary. This is unnecessary on IRIX and
- causes unwanted warnings from the native linker. */
- if (!TARGET_IRIX6)
- {
- /* Record the ABI itself. Modern versions of binutils encode
- this information in the ELF header flags, but GDB needs the
- information in order to correctly debug binaries produced by
- older binutils. See the function mips_gdbarch_init in
- gdb/mips-tdep.c. */
- fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
- mips_mdebug_abi_name ());
-
- /* There is no ELF header flag to distinguish long32 forms of the
- EABI from long64 forms. Emit a special section to help tools
- such as GDB. Do the same for o64, which is sometimes used with
- -mlong64. */
- if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
- fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
- "\t.previous\n", TARGET_LONG64 ? 64 : 32);
+ produce the resultant binary. */
+
+ /* Record the ABI itself. Modern versions of binutils encode
+ this information in the ELF header flags, but GDB needs the
+ information in order to correctly debug binaries produced by
+ older binutils. See the function mips_gdbarch_init in
+ gdb/mips-tdep.c. */
+ fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
+ mips_mdebug_abi_name ());
+
+ /* There is no ELF header flag to distinguish long32 forms of the
+ EABI from long64 forms. Emit a special section to help tools
+ such as GDB. Do the same for o64, which is sometimes used with
+ -mlong64. */
+ if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
+ fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
+ "\t.previous\n", TARGET_LONG64 ? 64 : 32);
+
+ /* Record the NaN encoding. */
+ if (HAVE_AS_NAN || mips_nan != MIPS_IEEE_754_DEFAULT)
+ fprintf (asm_out_file, "\t.nan\t%s\n",
+ mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
#ifdef HAVE_AS_GNU_ATTRIBUTE
- {
- int attr;
-
- /* No floating-point operations, -mno-float. */
- if (TARGET_NO_FLOAT)
- attr = 0;
- /* Soft-float code, -msoft-float. */
- else if (!TARGET_HARD_FLOAT_ABI)
- attr = 3;
- /* Single-float code, -msingle-float. */
- else if (!TARGET_DOUBLE_FLOAT)
- attr = 2;
- /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
- else if (!TARGET_64BIT && TARGET_FLOAT64)
- attr = 4;
- /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
- else
- attr = 1;
-
- fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
- }
+ {
+ int attr;
+
+ /* No floating-point operations, -mno-float. */
+ if (TARGET_NO_FLOAT)
+ attr = 0;
+ /* Soft-float code, -msoft-float. */
+ else if (!TARGET_HARD_FLOAT_ABI)
+ attr = 3;
+ /* Single-float code, -msingle-float. */
+ else if (!TARGET_DOUBLE_FLOAT)
+ attr = 2;
+ /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
+ else if (!TARGET_64BIT && TARGET_FLOAT64)
+ attr = 4;
+ /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
+ else
+ attr = 1;
+
+ fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
+ }
#endif
- }
/* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
if (TARGET_ABICALLS)
ASM_COMMENT_START,
mips_small_data_threshold, mips_arch_info->name, mips_isa);
}
+
+/* Implement TARGET_ASM_CODE_END. */
+
+static void
+mips_code_end (void)
+{
+ mips_finish_stub (&mips16_rdhwr_stub);
+ mips_finish_stub (&mips16_get_fcsr_stub);
+ mips_finish_stub (&mips16_set_fcsr_stub);
+}
\f
/* Make the last instruction frame-related and note that it performs
the operation described by FRAME_PATTERN. */
static void
mips_set_frame_expr (rtx frame_pattern)
{
- rtx insn;
+ rtx_insn *insn;
insn = get_last_insn ();
RTX_FRAME_RELATED_P (insn) = 1;
{
rtx set;
- /* If we're saving the return address register and the DWARF return
- address column differs from the hard register number, adjust the
- note reg to refer to the former. */
- if (REGNO (reg) == RETURN_ADDR_REGNUM
- && DWARF_FRAME_RETURN_COLUMN != RETURN_ADDR_REGNUM)
- reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
-
set = gen_rtx_SET (VOIDmode, mem, reg);
RTX_FRAME_RELATED_P (set) = 1;
return set;
}
+
+/* Record that the epilogue has restored call-saved register REG. */
+
+static void
+mips_add_cfa_restore (rtx reg)
+{
+ mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
+ mips_epilogue.cfa_restores);
+}
\f
/* If a MIPS16e SAVE or RESTORE instruction saves or restores register
mips16e_s2_s8_regs[X], it must also save the registers in indexes
mips16e_collect_argument_saves (void)
{
rtx reg_values[FIRST_PSEUDO_REGISTER];
- rtx insn, next, set, dest, src;
+ rtx_insn *insn, *next;
+ rtx set, dest, src;
unsigned int nargs, regno;
push_topmost_sequence ();
}
/* Return a move between register REGNO and memory location SP + OFFSET.
- Make the move a load if RESTORE_P, otherwise make it a frame-related
- store. */
+ REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
+ Make the move a load if RESTORE_P, otherwise make it a store. */
static rtx
-mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
- unsigned int regno)
+mips16e_save_restore_reg (bool restore_p, bool reg_parm_p,
+ HOST_WIDE_INT offset, unsigned int regno)
{
rtx reg, mem;
- mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
+ mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx,
+ offset));
reg = gen_rtx_REG (SImode, regno);
- return (restore_p
- ? gen_rtx_SET (VOIDmode, reg, mem)
- : mips_frame_set (mem, reg));
+ if (restore_p)
+ {
+ mips_add_cfa_restore (reg);
+ return gen_rtx_SET (VOIDmode, reg, mem);
+ }
+ if (reg_parm_p)
+ return gen_rtx_SET (VOIDmode, mem, reg);
+ return mips_frame_set (mem, reg);
}
/* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
/* Add the stack pointer adjustment. */
set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
- plus_constant (stack_pointer_rtx,
+ plus_constant (Pmode, stack_pointer_rtx,
restore_p ? size : -size));
RTX_FRAME_RELATED_P (set) = 1;
XVECEXP (pattern, 0, n++) = set;
for (i = 0; i < nargs; i++)
{
offset = top_offset + i * UNITS_PER_WORD;
- set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
+ set = mips16e_save_restore_reg (restore_p, true, offset,
+ GP_ARG_FIRST + i);
XVECEXP (pattern, 0, n++) = set;
}
if (BITSET_P (*mask_ptr, regno))
{
offset -= UNITS_PER_WORD;
- set = mips16e_save_restore_reg (restore_p, offset, regno);
+ set = mips16e_save_restore_reg (restore_p, false, offset, regno);
XVECEXP (pattern, 0, n++) = set;
*mask_ptr &= ~(1 << regno);
}
if *CACHE is already true. */
static bool
-mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
+mips_find_gp_ref (bool *cache, bool (*pred) (rtx_insn *))
{
- rtx insn;
+ rtx_insn *insn;
if (!*cache)
{
See mips_cfun_has_inflexible_gp_ref_p for details. */
static bool
-mips_insn_has_inflexible_gp_ref_p (rtx insn)
+mips_insn_has_inflexible_gp_ref_p (rtx_insn *insn)
{
/* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
indicate that the target could be a traditional MIPS
See mips_cfun_has_flexible_gp_ref_p for details. */
static bool
-mips_insn_has_flexible_gp_ref_p (rtx insn)
+mips_insn_has_flexible_gp_ref_p (rtx_insn *insn)
{
return (get_attr_got (insn) != GOT_UNSET
|| mips_small_data_pattern_p (PATTERN (insn))
/* If the global pointer is call-saved, try to use a call-clobbered
alternative. */
- if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
+ if (TARGET_CALL_SAVED_GP && crtl->is_leaf)
for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
if (!df_regs_ever_live_p (regno)
&& call_really_used_regs[regno]
static bool
mips_cfun_call_saved_reg_p (unsigned int regno)
{
+ /* If the user makes an ordinarily-call-saved register global,
+ that register is no longer call-saved. */
+ if (global_regs[regno])
+ return false;
+
/* Interrupt handlers need to save extra registers. */
if (cfun->machine->interrupt_handler_p
&& mips_interrupt_extra_call_saved_reg_p (regno))
/* If REGNO is ordinarily call-clobbered, we must assume that any
called function could modify it. */
if (cfun->machine->interrupt_handler_p
- && !current_function_is_leaf
+ && !crtl->is_leaf
&& mips_interrupt_extra_call_saved_reg_p (regno))
return true;
/* Set this function's interrupt properties. */
if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
{
- if (!ISA_MIPS32R2)
- error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
+ if (mips_isa_rev < 2)
+ error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater");
else if (TARGET_HARD_FLOAT)
error ("the %<interrupt%> attribute requires %<-msoft-float%>");
else if (TARGET_MIPS16)
slot. This area isn't needed in leaf functions, but if the
target-independent frame size is nonzero, we have already committed to
allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
- if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf)
+ if ((size == 0 || FRAME_GROWS_DOWNWARD) && crtl->is_leaf)
{
/* The MIPS 3.0 linker does not like functions that dynamically
allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
if (TARGET_CPRESTORE_DIRECTIVE)
{
gcc_assert (gp == pic_offset_table_rtx);
- emit_insn (gen_cprestore (mem, offset));
+ emit_insn (PMODE_INSN (gen_cprestore, (mem, offset)));
}
else
mips_emit_move (mips_cprestore_slot (temp, false), gp);
{
rtx mem;
- mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
+ mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx,
+ offset));
fn (gen_rtx_REG (mode, regno), mem);
}
}
}
+/* Save register REG to MEM. Make the instruction frame-related. */
+
+static void
+mips_save_reg (rtx reg, rtx mem)
+{
+ if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
+ {
+ rtx x1, x2;
+
+ mips_emit_move_or_split (mem, reg, SPLIT_IF_NECESSARY);
+
+ x1 = mips_frame_set (mips_subword (mem, false),
+ mips_subword (reg, false));
+ x2 = mips_frame_set (mips_subword (mem, true),
+ mips_subword (reg, true));
+ mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
+ }
+ else
+ mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
+}
+
+/* Capture the register combinations that are allowed in a SWM or LWM
+ instruction. The entries are ordered by number of registers set in
+ the mask. We also ignore the single register encodings because a
+ normal SW/LW is preferred. */
+
+static const unsigned int umips_swm_mask[17] = {
+ 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
+ 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
+ 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
+ 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
+ 0x00030000
+};
+
+static const unsigned int umips_swm_encoding[17] = {
+ 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
+};
+
+/* Try to use a microMIPS LWM or SWM instruction to save or restore
+ as many GPRs in *MASK as possible. *OFFSET is the offset from the
+ stack pointer of the topmost save slot.
+
+ Remove from *MASK all registers that were handled using LWM and SWM.
+ Update *OFFSET so that it points to the first unused save slot. */
+
+static bool
+umips_build_save_restore (mips_save_restore_fn fn,
+ unsigned *mask, HOST_WIDE_INT *offset)
+{
+ int nregs;
+ unsigned int i, j;
+ rtx pattern, set, reg, mem;
+ HOST_WIDE_INT this_offset;
+ rtx this_base;
+
+ /* Try matching $16 to $31 (s0 to ra). */
+ for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
+ if ((*mask & 0xffff0000) == umips_swm_mask[i])
+ break;
+
+ if (i == ARRAY_SIZE (umips_swm_mask))
+ return false;
+
+ /* Get the offset of the lowest save slot. */
+ nregs = (umips_swm_encoding[i] & 0xf) + (umips_swm_encoding[i] >> 4);
+ this_offset = *offset - UNITS_PER_WORD * (nregs - 1);
+
+ /* LWM/SWM can only support offsets from -2048 to 2047. */
+ if (!UMIPS_12BIT_OFFSET_P (this_offset))
+ return false;
+
+ /* Create the final PARALLEL. */
+ pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs));
+ this_base = stack_pointer_rtx;
+
+ /* For registers $16-$23 and $30. */
+ for (j = 0; j < (umips_swm_encoding[i] & 0xf); j++)
+ {
+ HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
+ mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
+ unsigned int regno = (j != 8) ? 16 + j : 30;
+ *mask &= ~(1 << regno);
+ reg = gen_rtx_REG (SImode, regno);
+ if (fn == mips_save_reg)
+ set = mips_frame_set (mem, reg);
+ else
+ {
+ set = gen_rtx_SET (VOIDmode, reg, mem);
+ mips_add_cfa_restore (reg);
+ }
+ XVECEXP (pattern, 0, j) = set;
+ }
+
+ /* For register $31. */
+ if (umips_swm_encoding[i] >> 4)
+ {
+ HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
+ *mask &= ~(1 << 31);
+ mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
+ reg = gen_rtx_REG (SImode, 31);
+ if (fn == mips_save_reg)
+ set = mips_frame_set (mem, reg);
+ else
+ {
+ set = gen_rtx_SET (VOIDmode, reg, mem);
+ mips_add_cfa_restore (reg);
+ }
+ XVECEXP (pattern, 0, j) = set;
+ }
+
+ pattern = emit_insn (pattern);
+ if (fn == mips_save_reg)
+ RTX_FRAME_RELATED_P (pattern) = 1;
+
+ /* Adjust the last offset. */
+ *offset -= UNITS_PER_WORD * nregs;
+
+ return true;
+}
+
/* Call FN for each register that is saved by the current function.
SP_OFFSET is the offset of the current stack pointer from the start
of the frame. */
mips_save_restore_fn fn)
{
enum machine_mode fpr_mode;
- HOST_WIDE_INT offset;
int regno;
+ const struct mips_frame_info *frame = &cfun->machine->frame;
+ HOST_WIDE_INT offset;
+ unsigned int mask;
/* Save registers starting from high to low. The debuggers prefer at least
the return register be stored at func+4, and also it allows us not to
need a nop in the epilogue if at least one register is reloaded in
addition to return address. */
- offset = cfun->machine->frame.gp_sp_offset - sp_offset;
+ offset = frame->gp_sp_offset - sp_offset;
+ mask = frame->mask;
+
+ if (TARGET_MICROMIPS)
+ umips_build_save_restore (fn, &mask, &offset);
+
for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
- if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
+ if (BITSET_P (mask, regno - GP_REG_FIRST))
{
/* Record the ra offset for use by mips_function_profiler. */
if (regno == RETURN_ADDR_REGNUM)
{
const char *fnname;
-#ifdef SDB_DEBUGGING_INFO
- if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
- SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
-#endif
-
/* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
floating-point arguments. */
if (TARGET_MIPS16
mips_end_function_definition (fnname);
}
\f
-/* Save register REG to MEM. Make the instruction frame-related. */
+/* Emit an optimisation barrier for accesses to the current frame. */
static void
-mips_save_reg (rtx reg, rtx mem)
+mips_frame_barrier (void)
{
- if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
- {
- rtx x1, x2;
-
- if (mips_split_64bit_move_p (mem, reg))
- mips_split_doubleword_move (mem, reg);
- else
- mips_emit_move (mem, reg);
-
- x1 = mips_frame_set (mips_subword (mem, false),
- mips_subword (reg, false));
- x2 = mips_frame_set (mips_subword (mem, true),
- mips_subword (reg, true));
- mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
- }
- else
- mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
+ emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx));
}
+
/* The __gnu_local_gp symbol. */
static GTY(()) rtx mips_gnu_local_gp;
mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
}
- emit_insn (Pmode == SImode
- ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
- : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
+ emit_insn (PMODE_INSN (gen_loadgp_absolute,
+ (pic_reg, mips_gnu_local_gp)));
break;
case LOADGP_OLDABI:
addr = XEXP (DECL_RTL (current_function_decl), 0);
offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
- emit_insn (Pmode == SImode
- ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
- : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
+ emit_insn (PMODE_INSN (gen_loadgp_newabi,
+ (pic_reg, offset, incoming_address)));
break;
case LOADGP_RTP:
base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
- emit_insn (Pmode == SImode
- ? gen_loadgp_rtp_si (pic_reg, base, index)
- : gen_loadgp_rtp_di (pic_reg, base, index));
+ emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index)));
break;
default:
}
if (TARGET_MIPS16)
- emit_insn (gen_copygp_mips16 (pic_offset_table_rtx, pic_reg));
+ emit_insn (PMODE_INSN (gen_copygp_mips16,
+ (pic_offset_table_rtx, pic_reg)));
/* Emit a blockage if there are implicit uses of the GP register.
This includes profiled functions, because FUNCTION_PROFILE uses
emit_insn (gen_loadgp_blockage ());
}
+#define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
+
+#if PROBE_INTERVAL > 32768
+#error Cannot use indexed addressing mode for stack probing
+#endif
+
+/* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
+ inclusive. These are offsets from the current stack pointer. */
+
+static void
+mips_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
+{
+ if (TARGET_MIPS16)
+ sorry ("-fstack-check=specific not implemented for MIPS16");
+
+ /* See if we have a constant small number of probes to generate. If so,
+ that's the easy case. */
+ if (first + size <= 32768)
+ {
+ HOST_WIDE_INT i;
+
+ /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
+ it exceeds SIZE. If only one probe is needed, this will not
+ generate any code. Then probe at FIRST + SIZE. */
+ for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
+ emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
+ -(first + i)));
+
+ emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
+ -(first + size)));
+ }
+
+ /* Otherwise, do the same as above, but in a loop. Note that we must be
+ extra careful with variables wrapping around because we might be at
+ the very top (or the very bottom) of the address space and we have
+ to be able to handle this case properly; in particular, we use an
+ equality test for the loop condition. */
+ else
+ {
+ HOST_WIDE_INT rounded_size;
+ rtx r3 = MIPS_PROLOGUE_TEMP (Pmode);
+ rtx r12 = MIPS_PROLOGUE_TEMP2 (Pmode);
+
+ /* Sanity check for the addressing mode we're going to use. */
+ gcc_assert (first <= 32768);
+
+
+ /* Step 1: round SIZE to the previous multiple of the interval. */
+
+ rounded_size = size & -PROBE_INTERVAL;
+
+
+ /* Step 2: compute initial and final value of the loop counter. */
+
+ /* TEST_ADDR = SP + FIRST. */
+ emit_insn (gen_rtx_SET (VOIDmode, r3,
+ plus_constant (Pmode, stack_pointer_rtx,
+ -first)));
+
+ /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
+ if (rounded_size > 32768)
+ {
+ emit_move_insn (r12, GEN_INT (rounded_size));
+ emit_insn (gen_rtx_SET (VOIDmode, r12,
+ gen_rtx_MINUS (Pmode, r3, r12)));
+ }
+ else
+ emit_insn (gen_rtx_SET (VOIDmode, r12,
+ plus_constant (Pmode, r3, -rounded_size)));
+
+
+ /* Step 3: the loop
+
+ while (TEST_ADDR != LAST_ADDR)
+ {
+ TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
+ probe at TEST_ADDR
+ }
+
+ probes at FIRST + N * PROBE_INTERVAL for values of N from 1
+ until it is equal to ROUNDED_SIZE. */
+
+ emit_insn (PMODE_INSN (gen_probe_stack_range, (r3, r3, r12)));
+
+
+ /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
+ that SIZE is equal to ROUNDED_SIZE. */
+
+ if (size != rounded_size)
+ emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
+ }
+
+ /* Make sure nothing is scheduled before we are done. */
+ emit_insn (gen_blockage ());
+}
+
+/* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
+ absolute addresses. */
+
+const char *
+mips_output_probe_stack_range (rtx reg1, rtx reg2)
+{
+ static int labelno = 0;
+ char loop_lab[32], end_lab[32], tmp[64];
+ rtx xops[2];
+
+ ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
+ ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
+
+ ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
+
+ /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
+ xops[0] = reg1;
+ xops[1] = reg2;
+ strcpy (tmp, "%(%<beq\t%0,%1,");
+ output_asm_insn (strcat (tmp, &end_lab[1]), xops);
+
+ /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
+ xops[1] = GEN_INT (-PROBE_INTERVAL);
+ if (TARGET_64BIT && TARGET_LONG64)
+ output_asm_insn ("daddiu\t%0,%0,%1", xops);
+ else
+ output_asm_insn ("addiu\t%0,%0,%1", xops);
+
+ /* Probe at TEST_ADDR and branch. */
+ fprintf (asm_out_file, "\tb\t");
+ assemble_name_raw (asm_out_file, loop_lab);
+ fputc ('\n', asm_out_file);
+ if (TARGET_64BIT)
+ output_asm_insn ("sd\t$0,0(%0)%)", xops);
+ else
+ output_asm_insn ("sw\t$0,0(%0)%)", xops);
+
+ ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
+
+ return "";
+}
+
/* A for_each_rtx callback. Stop the search if *X is a kernel register. */
static int
const struct mips_frame_info *frame;
HOST_WIDE_INT size;
unsigned int nargs;
- rtx insn;
if (cfun->machine->global_pointer != INVALID_REGNUM)
{
frame = &cfun->machine->frame;
size = frame->total_size;
- if (flag_stack_usage)
+ if (flag_stack_usage_info)
current_function_static_stack_size = size;
+ if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
+ {
+ if (crtl->is_leaf && !cfun->calls_alloca)
+ {
+ if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT)
+ mips_emit_probe_stack_range (STACK_CHECK_PROTECT,
+ size - STACK_CHECK_PROTECT);
+ }
+ else if (size > 0)
+ mips_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
+ }
+
/* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
bytes beforehand; this is enough to cover the register save area
without going out of range. */
/* Build the save instruction. */
mask = frame->mask;
- insn = mips16e_build_save_restore (false, &mask, &offset,
- nargs, step1);
+ rtx insn = mips16e_build_save_restore (false, &mask, &offset,
+ nargs, step1);
RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
+ mips_frame_barrier ();
size -= step1;
/* Check if we need to save other registers. */
}
/* Allocate the first part of the frame. */
- insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
- GEN_INT (-step1));
+ rtx insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
+ GEN_INT (-step1));
RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
+ mips_frame_barrier ();
size -= step1;
/* Start at the uppermost location for saving. */
{
/* Push EPC into its stack slot. */
mem = gen_frame_mem (word_mode,
- plus_constant (stack_pointer_rtx,
+ plus_constant (Pmode, stack_pointer_rtx,
offset));
mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
offset -= UNITS_PER_WORD;
/* Push Status into its stack slot. */
mem = gen_frame_mem (word_mode,
- plus_constant (stack_pointer_rtx, offset));
+ plus_constant (Pmode, stack_pointer_rtx,
+ offset));
mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
offset -= UNITS_PER_WORD;
}
else
{
- insn = gen_add3_insn (stack_pointer_rtx,
- stack_pointer_rtx,
- GEN_INT (-step1));
+ rtx insn = gen_add3_insn (stack_pointer_rtx,
+ stack_pointer_rtx,
+ GEN_INT (-step1));
RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
+ mips_frame_barrier ();
size -= step1;
}
mips_for_each_saved_acc (size, mips_save_reg);
/* Describe the combined effect of the previous instructions. */
mips_set_frame_expr
(gen_rtx_SET (VOIDmode, stack_pointer_rtx,
- plus_constant (stack_pointer_rtx, -size)));
+ plus_constant (Pmode, stack_pointer_rtx, -size)));
}
+ mips_frame_barrier ();
}
/* Set up the frame pointer, if we're using one. */
offset = frame->hard_frame_pointer_offset;
if (offset == 0)
{
- insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
+ rtx insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
RTX_FRAME_RELATED_P (insn) = 1;
}
else if (SMALL_OPERAND (offset))
{
- insn = gen_add3_insn (hard_frame_pointer_rtx,
- stack_pointer_rtx, GEN_INT (offset));
+ rtx insn = gen_add3_insn (hard_frame_pointer_rtx,
+ stack_pointer_rtx, GEN_INT (offset));
RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
}
else
MIPS_PROLOGUE_TEMP (Pmode)));
mips_set_frame_expr
(gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
- plus_constant (stack_pointer_rtx, offset)));
+ plus_constant (Pmode, stack_pointer_rtx, offset)));
}
}
HOST_WIDE_INT offset;
mips_get_cprestore_base_and_offset (&base, &offset, false);
- mem = gen_frame_mem (Pmode, plus_constant (base, offset));
+ mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
temp = (SMALL_OPERAND (offset)
? gen_rtx_SCRATCH (Pmode)
: MIPS_PROLOGUE_TEMP (Pmode));
- emit_insn (gen_potential_cprestore (mem, GEN_INT (offset), gp, temp));
+ emit_insn (PMODE_INSN (gen_potential_cprestore,
+ (mem, GEN_INT (offset), gp, temp)));
mips_get_cprestore_base_and_offset (&base, &offset, true);
- mem = gen_frame_mem (Pmode, plus_constant (base, offset));
- emit_insn (gen_use_cprestore (mem));
+ mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
+ emit_insn (PMODE_INSN (gen_use_cprestore, (mem)));
}
/* We need to search back to the last use of K0 or K1. */
if (cfun->machine->interrupt_handler_p)
{
+ rtx_insn *insn;
for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
if (INSN_P (insn)
&& for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
emit_insn (gen_blockage ());
}
\f
-/* Emit instructions to restore register REG from slot MEM. */
+/* Attach all pending register saves to the previous instruction.
+ Return that instruction. */
+
+static rtx_insn *
+mips_epilogue_emit_cfa_restores (void)
+{
+ rtx_insn *insn;
+
+ insn = get_last_insn ();
+ gcc_assert (insn && !REG_NOTES (insn));
+ if (mips_epilogue.cfa_restores)
+ {
+ RTX_FRAME_RELATED_P (insn) = 1;
+ REG_NOTES (insn) = mips_epilogue.cfa_restores;
+ mips_epilogue.cfa_restores = 0;
+ }
+ return insn;
+}
+
+/* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
+ now at REG + OFFSET. */
+
+static void
+mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset)
+{
+ rtx_insn *insn;
+
+ insn = mips_epilogue_emit_cfa_restores ();
+ if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset)
+ {
+ RTX_FRAME_RELATED_P (insn) = 1;
+ REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA,
+ plus_constant (Pmode, reg, offset),
+ REG_NOTES (insn));
+ mips_epilogue.cfa_reg = reg;
+ mips_epilogue.cfa_offset = offset;
+ }
+}
+
+/* Emit instructions to restore register REG from slot MEM. Also update
+ the cfa_restores list. */
static void
mips_restore_reg (rtx reg, rtx mem)
$7 instead and adjust the return insn appropriately. */
if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
+ else if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
+ {
+ mips_add_cfa_restore (mips_subword (reg, true));
+ mips_add_cfa_restore (mips_subword (reg, false));
+ }
+ else
+ mips_add_cfa_restore (reg);
mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
+ if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg))
+ /* The CFA is currently defined in terms of the register whose
+ value we have just restored. Redefine the CFA in terms of
+ the stack pointer. */
+ mips_epilogue_set_cfa (stack_pointer_rtx,
+ mips_epilogue.cfa_restore_sp_offset);
+}
+
+/* Emit code to set the stack pointer to BASE + OFFSET, given that
+ BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
+ BASE, if not the stack pointer, is available as a temporary. */
+
+static void
+mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size)
+{
+ if (base == stack_pointer_rtx && offset == const0_rtx)
+ return;
+
+ mips_frame_barrier ();
+ if (offset == const0_rtx)
+ {
+ emit_move_insn (stack_pointer_rtx, base);
+ mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
+ }
+ else if (TARGET_MIPS16 && base != stack_pointer_rtx)
+ {
+ emit_insn (gen_add3_insn (base, base, offset));
+ mips_epilogue_set_cfa (base, new_frame_size);
+ emit_move_insn (stack_pointer_rtx, base);
+ }
+ else
+ {
+ emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset));
+ mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
+ }
}
/* Emit any instructions needed before a return. */
{
const struct mips_frame_info *frame;
HOST_WIDE_INT step1, step2;
- rtx base, target, insn;
+ rtx base, adjust;
+ rtx_insn *insn;
+ bool use_jraddiusp_p = false;
if (!sibcall_p && mips_can_use_return_insn ())
{
base = hard_frame_pointer_rtx;
step1 -= frame->hard_frame_pointer_offset;
}
+ mips_epilogue.cfa_reg = base;
+ mips_epilogue.cfa_offset = step1;
+ mips_epilogue.cfa_restores = NULL_RTX;
/* If we need to restore registers, deallocate as much stack as
possible in the second step without going out of range. */
step1 -= step2;
}
- /* Set TARGET to BASE + STEP1. */
- target = base;
- if (step1 > 0)
+ /* Get an rtx for STEP1 that we can add to BASE. */
+ adjust = GEN_INT (step1);
+ if (!SMALL_OPERAND (step1))
{
- rtx adjust;
-
- /* Get an rtx for STEP1 that we can add to BASE. */
- adjust = GEN_INT (step1);
- if (!SMALL_OPERAND (step1))
- {
- mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
- adjust = MIPS_EPILOGUE_TEMP (Pmode);
- }
-
- /* Normal mode code can copy the result straight into $sp. */
- if (!TARGET_MIPS16)
- target = stack_pointer_rtx;
-
- emit_insn (gen_add3_insn (target, base, adjust));
+ mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
+ adjust = MIPS_EPILOGUE_TEMP (Pmode);
}
-
- /* Copy TARGET into the stack pointer. */
- if (target != stack_pointer_rtx)
- mips_emit_move (stack_pointer_rtx, target);
+ mips_deallocate_stack (base, adjust, step2);
/* If we're using addressing macros, $gp is implicitly used by all
SYMBOL_REFs. We must emit a blockage insn before restoring $gp
if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
emit_insn (gen_blockage ());
+ mips_epilogue.cfa_restore_sp_offset = step2;
if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
{
unsigned int regno, mask;
/* Restore the remaining registers and deallocate the final bit
of the frame. */
+ mips_frame_barrier ();
emit_insn (restore);
+ mips_epilogue_set_cfa (stack_pointer_rtx, 0);
}
else
{
{
/* Restore the original EPC. */
mem = gen_frame_mem (word_mode,
- plus_constant (stack_pointer_rtx, offset));
+ plus_constant (Pmode, stack_pointer_rtx,
+ offset));
mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
offset -= UNITS_PER_WORD;
/* Restore the original Status. */
mem = gen_frame_mem (word_mode,
- plus_constant (stack_pointer_rtx, offset));
+ plus_constant (Pmode, stack_pointer_rtx,
+ offset));
mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
offset -= UNITS_PER_WORD;
- /* If we don't use shoadow register set, we need to update SP. */
- if (!cfun->machine->use_shadow_register_set_p && step2 > 0)
- emit_insn (gen_add3_insn (stack_pointer_rtx,
- stack_pointer_rtx,
- GEN_INT (step2)));
+ /* If we don't use shadow register set, we need to update SP. */
+ if (!cfun->machine->use_shadow_register_set_p)
+ mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
+ else
+ /* The choice of position is somewhat arbitrary in this case. */
+ mips_epilogue_emit_cfa_restores ();
/* Move to COP0 Status. */
emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
gen_rtx_REG (SImode, K0_REG_NUM)));
}
+ else if (TARGET_MICROMIPS
+ && !crtl->calls_eh_return
+ && !sibcall_p
+ && step2 > 0
+ && mips_unsigned_immediate_p (step2, 5, 2))
+ use_jraddiusp_p = true;
else
- {
- /* Deallocate the final bit of the frame. */
- if (step2 > 0)
- emit_insn (gen_add3_insn (stack_pointer_rtx,
- stack_pointer_rtx,
- GEN_INT (step2)));
- }
+ /* Deallocate the final bit of the frame. */
+ mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
}
+ if (!use_jraddiusp_p)
+ gcc_assert (!mips_epilogue.cfa_restores);
+
/* Add in the __builtin_eh_return stack adjustment. We need to
use a temporary in MIPS16 code. */
if (crtl->calls_eh_return)
}
else
{
- unsigned int regno;
+ rtx pat;
/* When generating MIPS16 code, the normal
mips_for_each_saved_gpr_and_fpr path will restore the return
if (TARGET_MIPS16
&& !GENERATE_MIPS16E_SAVE_RESTORE
&& BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
- regno = GP_REG_FIRST + 7;
+ {
+ /* simple_returns cannot rely on values that are only available
+ on paths through the epilogue (because return paths that do
+ not pass through the epilogue may nevertheless reuse a
+ simple_return that occurs at the end of the epilogue).
+ Use a normal return here instead. */
+ rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
+ pat = gen_return_internal (reg);
+ }
+ else if (use_jraddiusp_p)
+ pat = gen_jraddiusp (GEN_INT (step2));
else
- regno = RETURN_ADDR_REGNUM;
- emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
+ {
+ rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
+ pat = gen_simple_return_internal (reg);
+ }
+ emit_jump_insn (pat);
+ if (use_jraddiusp_p)
+ mips_epilogue_set_cfa (stack_pointer_rtx, step2);
}
}
&& (regno - ST_REG_FIRST) % 4 == 0);
if (mode == CCmode)
- {
- if (!ISA_HAS_8CC)
- return regno == FPSW_REGNUM;
-
- return (ST_REG_P (regno)
- || GP_REG_P (regno)
- || FP_REG_P (regno));
- }
+ return ISA_HAS_8CC ? ST_REG_P (regno) : regno == FPSW_REGNUM;
size = GET_MODE_SIZE (mode);
mclass = GET_MODE_CLASS (mode);
&& (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
|| (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
{
- /* Allow TFmode for CCmode reloads. */
- if (mode == TFmode && ISA_HAS_8CC)
- return true;
-
/* Allow 64-bit vector modes for Loongson-2E/2F. */
if (TARGET_LOONGSON_VECTORS
&& (mode == V2SImode
COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
{
- size = MIN (size, 4);
+ if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
+ size = MIN (size, 4);
AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
}
if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
{
- size = MIN (size, UNITS_PER_FPREG);
+ if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
+ size = MIN (size, UNITS_PER_FPREG);
AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
}
if (!hard_reg_set_empty_p (left))
/* Implement CANNOT_CHANGE_MODE_CLASS. */
bool
-mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
- enum machine_mode to ATTRIBUTE_UNUSED,
+mips_cannot_change_mode_class (enum machine_mode from,
+ enum machine_mode to,
enum reg_class rclass)
{
- /* There are several problems with changing the modes of values
- in floating-point registers:
+ /* Allow conversions between different Loongson integer vectors,
+ and between those vectors and DImode. */
+ if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8
+ && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to))
+ return false;
+
+ /* Otherwise, there are several problems with changing the modes of
+ values in floating-point registers:
- When a multi-word value is stored in paired floating-point
- registers, the first register always holds the low word.
- We therefore can't allow FPRs to change between single-word
- and multi-word modes on big-endian targets.
+ registers, the first register always holds the low word. We
+ therefore can't allow FPRs to change between single-word and
+ multi-word modes on big-endian targets.
- - GCC assumes that each word of a multiword register can be accessed
- individually using SUBREGs. This is not true for floating-point
- registers if they are bigger than a word.
+ - GCC assumes that each word of a multiword register can be
+ accessed individually using SUBREGs. This is not true for
+ floating-point registers if they are bigger than a word.
- Loading a 32-bit value into a 64-bit floating-point register
- will not sign-extend the value, despite what LOAD_EXTEND_OP says.
- We can't allow FPRs to change from SImode to to a wider mode on
- 64-bit targets.
+ will not sign-extend the value, despite what LOAD_EXTEND_OP
+ says. We can't allow FPRs to change from SImode to a wider
+ mode on 64-bit targets.
- - If the FPU has already interpreted a value in one format, we must
- not ask it to treat the value as having a different format.
+ - If the FPU has already interpreted a value in one format, we
+ must not ask it to treat the value as having a different
+ format.
We therefore disallow all mode changes involving FPRs. */
+
return reg_classes_intersect_p (FP_REGS, rclass);
}
&& !mips_mode_ok_for_mov_fmt_p (mode2)));
}
-/* Implement PREFERRED_RELOAD_CLASS. */
+/* Implement TARGET_PREFERRED_RELOAD_CLASS. */
-enum reg_class
-mips_preferred_reload_class (rtx x, enum reg_class rclass)
+static reg_class_t
+mips_preferred_reload_class (rtx x, reg_class_t rclass)
{
if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
return LEA_REGS;
return rclass;
}
-/* Return the cost of moving a value of mode MODE from a register of
- class FROM to a GPR. Return 0 for classes that are unions of other
- classes handled by this function. */
+/* Return the cost of moving a value from a register of class FROM to a GPR.
+ Return 0 for classes that are unions of other classes handled by this
+ function. */
static int
-mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
- reg_class_t from)
+mips_move_to_gpr_cost (reg_class_t from)
{
switch (from)
{
+ case M16_REGS:
case GENERAL_REGS:
/* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
return 2;
/* MFC1, etc. */
return 4;
- case ST_REGS:
- /* LUI followed by MOVF. */
- return 4;
-
case COP0_REGS:
case COP2_REGS:
case COP3_REGS:
}
}
-/* Return the cost of moving a value of mode MODE from a GPR to a
- register of class TO. Return 0 for classes that are unions of
- other classes handled by this function. */
+/* Return the cost of moving a value from a GPR to a register of class TO.
+ Return 0 for classes that are unions of other classes handled by this
+ function. */
static int
-mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to)
+mips_move_from_gpr_cost (reg_class_t to)
{
switch (to)
{
+ case M16_REGS:
case GENERAL_REGS:
/* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
return 2;
/* MTC1, etc. */
return 4;
- case ST_REGS:
- /* A secondary reload through an FPR scratch. */
- return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
- + mips_register_move_cost (mode, FP_REGS, ST_REGS));
-
case COP0_REGS:
case COP2_REGS:
case COP3_REGS:
if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
/* MOV.FMT. */
return 4;
- if (to == ST_REGS)
- /* The sequence generated by mips_expand_fcc_reload. */
- return 8;
}
/* Handle cases in which only one class deviates from the ideal. */
dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
if (from == dregs)
- return mips_move_from_gpr_cost (mode, to);
+ return mips_move_from_gpr_cost (to);
if (to == dregs)
- return mips_move_to_gpr_cost (mode, from);
+ return mips_move_to_gpr_cost (from);
/* Handles cases that require a GPR temporary. */
- cost1 = mips_move_to_gpr_cost (mode, from);
+ cost1 = mips_move_to_gpr_cost (from);
if (cost1 != 0)
{
- cost2 = mips_move_from_gpr_cost (mode, to);
+ cost2 = mips_move_from_gpr_cost (to);
if (cost2 != 0)
return cost1 + cost2;
}
return 0;
}
+/* Implement TARGET_REGISTER_PRIORITY. */
+
+static int
+mips_register_priority (int hard_regno)
+{
+ /* Treat MIPS16 registers with higher priority than other regs. */
+ if (TARGET_MIPS16
+ && TEST_HARD_REG_BIT (reg_class_contents[M16_REGS], hard_regno))
+ return 1;
+ return 0;
+}
+
/* Implement TARGET_MEMORY_MOVE_COST. */
static int
+ memory_move_secondary_cost (mode, rclass, in));
}
-/* Implement TARGET_IRA_COVER_CLASSES. */
-
-static const reg_class_t *
-mips_ira_cover_classes (void)
-{
- static const reg_class_t acc_classes[] = {
- GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
- ST_REGS, LIM_REG_CLASSES
- };
- static const reg_class_t no_acc_classes[] = {
- GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
- ST_REGS, LIM_REG_CLASSES
- };
-
- /* Don't allow the register allocators to use LO and HI in MIPS16 mode,
- which has no MTLO or MTHI instructions. Also, using GR_AND_ACC_REGS
- as a cover class only works well when we keep per-register costs.
- Using it when not optimizing can cause us to think accumulators
- have the same cost as GPRs in cases where GPRs are actually much
- cheaper. */
- return TARGET_MIPS16 || !optimize ? no_acc_classes : acc_classes;
-}
-
/* Return the register class required for a secondary register when
copying between one of the registers in RCLASS and value X, which
has mode MODE. X is the source of the move if IN_P, otherwise it
enum reg_class
mips_secondary_reload_class (enum reg_class rclass,
- enum machine_mode mode, rtx x, bool in_p)
+ enum machine_mode mode, rtx x, bool)
{
int regno;
if (ACC_REG_P (regno))
return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
- /* We can only copy a value to a condition code register from a
- floating-point register, and even then we require a scratch
- floating-point register. We can only copy a value out of a
- condition-code register into a general register. */
- if (reg_class_subset_p (rclass, ST_REGS))
- {
- if (in_p)
- return FP_REGS;
- return GP_REG_P (regno) ? NO_REGS : GR_REGS;
- }
- if (ST_REG_P (regno))
- {
- if (!in_p)
- return FP_REGS;
- return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
- }
-
if (reg_class_subset_p (rclass, FP_REGS))
{
- if (MEM_P (x)
- && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
+ if (regno < 0
+ || (MEM_P (x)
+ && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)))
/* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
return NO_REGS;
/* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
return NO_REGS;
- if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
+ if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
/* We can force the constant to memory and use lwc1
and ldc1. As above, we will use pairs of lwc1s if
ldc1 is not supported. */
}
/* The MIPS16 ISA does not have an encoding for "sync", so we rely
- on an external non-MIPS16 routine to implement __sync_synchronize. */
+ on an external non-MIPS16 routine to implement __sync_synchronize.
+ Similarly for the rest of the ll/sc libfuncs. */
if (TARGET_MIPS16)
- synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
+ {
+ synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
+ init_sync_libfuncs (UNITS_PER_WORD);
+ }
}
/* Build up a multi-insn sequence that loads label TARGET into $AT. */
attributes in the machine-description file. */
int
-mips_adjust_insn_length (rtx insn, int length)
+mips_adjust_insn_length (rtx_insn *insn, int length)
{
/* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
of a PIC long-branch sequence. Substitute the correct value. */
if (length == MAX_PIC_BRANCH_LENGTH
+ && JUMP_P (insn)
&& INSN_CODE (insn) >= 0
&& get_attr_type (insn) == TYPE_BRANCH)
{
is a conditional branch. */
length = simplejump_p (insn) ? 0 : 8;
- /* Load the label into $AT and jump to it. Ignore the delay
- slot of the jump. */
- length += 4 * mips_load_label_num_insns() + 4;
+ /* Add the size of a load into $AT. */
+ length += BASE_INSN_LENGTH * mips_load_label_num_insns ();
+
+ /* Add the length of an indirect jump, ignoring the delay slot. */
+ length += TARGET_COMPRESSION ? 2 : 4;
}
/* A unconditional jump has an unfilled delay slot if it is not part
of a sequence. A conditional jump normally has a delay slot, but
does not on MIPS16. */
if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
- length += 4;
+ length += TARGET_MIPS16 ? 2 : 4;
/* See how many nops might be needed to avoid hardware hazards. */
- if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
+ if (!cfun->machine->ignore_hazard_length_p
+ && INSN_P (insn)
+ && INSN_CODE (insn) >= 0)
switch (get_attr_hazard (insn))
{
case HAZARD_NONE:
break;
case HAZARD_DELAY:
- length += 4;
+ length += NOP_INSN_LENGTH;
break;
case HAZARD_HILO:
- length += 8;
+ length += NOP_INSN_LENGTH * 2;
break;
}
- /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
- the .md file length attributes are 4-based for both modes.
- Adjust the MIPS16 ones here. */
- if (TARGET_MIPS16)
- length /= 2;
-
return length;
}
version of BRANCH_IF_TRUE. */
const char *
-mips_output_conditional_branch (rtx insn, rtx *operands,
+mips_output_conditional_branch (rtx_insn *insn, rtx *operands,
const char *branch_if_true,
const char *branch_if_false)
{
unsigned int length;
- rtx taken, not_taken;
+ rtx taken;
gcc_assert (LABEL_P (operands[0]));
/* Generate a reversed branch around a direct jump. This fallback does
not use branch-likely instructions. */
mips_branch_likely = false;
- not_taken = gen_label_rtx ();
+ rtx_code_label *not_taken = gen_label_rtx ();
taken = operands[0];
/* Generate the reversed branch to NOT_TAKEN. */
delay slot if is not annulled. */
if (!INSN_ANNULLED_BRANCH_P (insn))
{
- final_scan_insn (XVECEXP (final_sequence, 0, 1),
+ final_scan_insn (final_sequence->insn (1),
asm_out_file, optimize, 1, NULL);
- INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
+ final_sequence->insn (1)->set_deleted ();
}
else
output_asm_insn ("nop", 0);
Use INSN's delay slot if is annulled. */
if (INSN_ANNULLED_BRANCH_P (insn))
{
- final_scan_insn (XVECEXP (final_sequence, 0, 1),
+ final_scan_insn (final_sequence->insn (1),
asm_out_file, optimize, 1, NULL);
- INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
+ final_sequence->insn (1)->set_deleted ();
}
else
output_asm_insn ("nop", 0);
its second is always zero. */
const char *
-mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
+mips_output_order_conditional_branch (rtx_insn *insn, rtx *operands, bool inverted_p)
{
const char *branch[2];
if (!ISA_HAS_LL_SC)
{
output_asm_insn (".set\tpush", 0);
- output_asm_insn (".set\tmips2", 0);
+ if (TARGET_64BIT)
+ output_asm_insn (".set\tmips3", 0);
+ else
+ output_asm_insn (".set\tmips2", 0);
}
}
sequence for it. */
static void
-mips_process_sync_loop (rtx insn, rtx *operands)
+mips_process_sync_loop (rtx_insn *insn, rtx *operands)
{
rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
- rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3;
+ rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3, cmp;
unsigned int tmp3_insn;
enum attr_sync_insn1 insn1;
enum attr_sync_insn2 insn2;
bool is_64bit_p;
+ int memmodel_attr;
+ enum memmodel model;
/* Read an operand from the sync_WHAT attribute and store it in
variable WHAT. DEFAULT is the default value if no attribute
/* Read the other attributes. */
at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
READ_OPERAND (oldval, at);
+ READ_OPERAND (cmp, 0);
READ_OPERAND (newval, at);
READ_OPERAND (inclusive_mask, 0);
READ_OPERAND (exclusive_mask, 0);
insn1 = get_attr_sync_insn1 (insn);
insn2 = get_attr_sync_insn2 (insn);
+ /* Don't bother setting CMP result that is never used. */
+ if (cmp && find_reg_note (insn, REG_UNUSED, cmp))
+ cmp = 0;
+
+ memmodel_attr = get_attr_sync_memmodel (insn);
+ switch (memmodel_attr)
+ {
+ case 10:
+ model = MEMMODEL_ACQ_REL;
+ break;
+ case 11:
+ model = MEMMODEL_ACQUIRE;
+ break;
+ default:
+ model = (enum memmodel) INTVAL (operands[memmodel_attr]);
+ }
+
mips_multi_start ();
/* Output the release side of the memory barrier. */
- if (get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES)
+ if (need_atomic_barrier_p (model, true))
{
if (required_oldval == 0 && TARGET_OCTEON)
{
tmp1 = at;
}
mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
+
+ /* CMP = 0 [delay slot]. */
+ if (cmp)
+ mips_multi_add_insn ("li\t%0,0", cmp, NULL);
}
/* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
mips_multi_copy_insn (tmp3_insn);
mips_multi_set_operand (mips_multi_last_index (), 0, newval);
}
- else
+ else if (!(required_oldval && cmp))
mips_multi_add_insn ("nop", NULL);
+ /* CMP = 1 -- either standalone or in a delay slot. */
+ if (required_oldval && cmp)
+ mips_multi_add_insn ("li\t%0,1", cmp, NULL);
+
/* Output the acquire side of the memory barrier. */
- if (TARGET_SYNC_AFTER_SC)
+ if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false))
mips_multi_add_insn ("sync", NULL);
/* Output the exit label, if needed. */
the operands given by OPERANDS. */
const char *
-mips_output_sync_loop (rtx insn, rtx *operands)
+mips_output_sync_loop (rtx_insn *insn, rtx *operands)
{
mips_process_sync_loop (insn, operands);
which has the operands given by OPERANDS. */
unsigned int
-mips_sync_loop_insns (rtx insn, rtx *operands)
+mips_sync_loop_insns (rtx_insn *insn, rtx *operands)
{
mips_process_sync_loop (insn, operands);
return mips_multi_num_insns;
return s;
}
\f
+/* Return true if destination of IN_INSN is used as add source in
+ OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example:
+ madd.s dst, x, y, z
+ madd.s a, dst, b, c */
+
+bool
+mips_fmadd_bypass (rtx_insn *out_insn, rtx_insn *in_insn)
+{
+ int dst_reg, src_reg;
+
+ gcc_assert (get_attr_type (in_insn) == TYPE_FMADD);
+ gcc_assert (get_attr_type (out_insn) == TYPE_FMADD);
+
+ extract_insn (in_insn);
+ dst_reg = REG_P (recog_data.operand[0]);
+
+ extract_insn (out_insn);
+ src_reg = REG_P (recog_data.operand[1]);
+
+ if (dst_reg == src_reg)
+ return true;
+
+ return false;
+}
+
/* Return true if IN_INSN is a multiply-add or multiply-subtract
instruction and if OUT_INSN assigns to the accumulator operand. */
bool
-mips_linked_madd_p (rtx out_insn, rtx in_insn)
+mips_linked_madd_p (rtx_insn *out_insn, rtx_insn *in_insn)
{
- rtx x;
+ enum attr_accum_in accum_in;
+ int accum_in_opnum;
+ rtx accum_in_op;
- x = single_set (in_insn);
- if (x == 0)
+ if (recog_memoized (in_insn) < 0)
return false;
- x = SET_SRC (x);
+ accum_in = get_attr_accum_in (in_insn);
+ if (accum_in == ACCUM_IN_NONE)
+ return false;
- if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 0)) == MULT
- && reg_set_p (XEXP (x, 1), out_insn))
- return true;
+ accum_in_opnum = accum_in - ACCUM_IN_0;
- if (GET_CODE (x) == MINUS
- && GET_CODE (XEXP (x, 1)) == MULT
- && reg_set_p (XEXP (x, 0), out_insn))
- return true;
+ extract_insn (in_insn);
+ gcc_assert (accum_in_opnum < recog_data.n_operands);
+ accum_in_op = recog_data.operand[accum_in_opnum];
- return false;
+ return reg_set_p (accum_in_op, out_insn);
}
/* True if the dependency between OUT_INSN and IN_INSN is on the store
for that case. */
bool
-mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
+mips_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
{
if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
return false;
DFA state.
E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
instruction to go ALU1. */
- rtx alu1_turn_enabled_insn;
- rtx alu2_turn_enabled_insn;
- rtx falu1_turn_enabled_insn;
- rtx falu2_turn_enabled_insn;
+ rtx_insn *alu1_turn_enabled_insn;
+ rtx_insn *alu2_turn_enabled_insn;
+ rtx_insn *falu1_turn_enabled_insn;
+ rtx_insn *falu2_turn_enabled_insn;
} mips_ls2;
/* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
is treated like input-dependence. */
static int
-mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
- rtx dep ATTRIBUTE_UNUSED, int cost)
+mips_adjust_cost (rtx_insn *insn ATTRIBUTE_UNUSED, rtx link,
+ rtx_insn *dep ATTRIBUTE_UNUSED, int cost)
{
if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
&& TUNE_20KC)
case PROCESSOR_R4130:
case PROCESSOR_R5400:
case PROCESSOR_R5500:
+ case PROCESSOR_R5900:
case PROCESSOR_R7000:
case PROCESSOR_R9000:
case PROCESSOR_OCTEON:
+ case PROCESSOR_OCTEON2:
return 2;
case PROCESSOR_SB1:
case PROCESSOR_LOONGSON_2E:
case PROCESSOR_LOONGSON_2F:
case PROCESSOR_LOONGSON_3A:
+ case PROCESSOR_P5600:
return 4;
+ case PROCESSOR_XLP:
+ return (reload_completed ? 4 : 3);
+
default:
return 1;
}
if (TUNE_OCTEON)
return 2;
+ if (TUNE_P5600)
+ return 4;
+
return 0;
}
\f
be <= HIGHER. */
static void
-mips_promote_ready (rtx *ready, int lower, int higher)
+mips_promote_ready (rtx_insn **ready, int lower, int higher)
{
- rtx new_head;
+ rtx_insn *new_head;
int i;
new_head = ready[lower];
instructions if POS2 is not already less than POS1. */
static void
-mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
+mips_maybe_swap_ready (rtx_insn **ready, int pos1, int pos2, int limit)
{
if (pos1 < pos2
&& INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
{
- rtx temp;
+ rtx_insn *temp;
temp = ready[pos1];
ready[pos1] = ready[pos2];
\f
/* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
that may clobber hi or lo. */
-static rtx mips_macc_chains_last_hilo;
+static rtx_insn *mips_macc_chains_last_hilo;
/* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
been scheduled, updating mips_macc_chains_last_hilo appropriately. */
static void
-mips_macc_chains_record (rtx insn)
+mips_macc_chains_record (rtx_insn *insn)
{
if (get_attr_may_clobber_hilo (insn))
mips_macc_chains_last_hilo = insn;
clobber hi or lo. */
static void
-mips_macc_chains_reorder (rtx *ready, int nready)
+mips_macc_chains_reorder (rtx_insn **ready, int nready)
{
int i, j;
}
\f
/* The last instruction to be scheduled. */
-static rtx vr4130_last_insn;
+static rtx_insn *vr4130_last_insn;
/* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
points to an rtx that is initially an instruction. Nullify the rtx
alignment than (INSN1, INSN2). See 4130.md for more details. */
static bool
-vr4130_swap_insns_p (rtx insn1, rtx insn2)
+vr4130_swap_insns_p (rtx_insn *insn1, rtx_insn *insn2)
{
sd_iterator_def sd_it;
dep_t dep;
vr4130_swap_insns_p says that it could be worthwhile. */
static void
-vr4130_reorder (rtx *ready, int nready)
+vr4130_reorder (rtx_insn **ready, int nready)
{
if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
mips_promote_ready (ready, nready - 2, nready - 1);
resets to TYPE_UNKNOWN state. */
static void
-mips_74k_agen_init (rtx insn)
+mips_74k_agen_init (rtx_insn *insn)
{
if (!insn || CALL_P (insn) || JUMP_P (insn))
mips_last_74k_agen_insn = TYPE_UNKNOWN;
together. Swap things around in the ready queue to make this happen. */
static void
-mips_74k_agen_reorder (rtx *ready, int nready)
+mips_74k_agen_reorder (rtx_insn **ready, int nready)
{
int i;
int store_pos, load_pos;
for (i = nready - 1; i >= 0; i--)
{
- rtx insn = ready[i];
+ rtx_insn *insn = ready[i];
if (USEFUL_INSN_P (insn))
switch (get_attr_type (insn))
{
{
mips_macc_chains_last_hilo = 0;
vr4130_last_insn = 0;
- mips_74k_agen_init (NULL_RTX);
+ mips_74k_agen_init (NULL);
/* When scheduling for Loongson2, branch instructions go to ALU1,
therefore basic block is most likely to start with round-robin counter
static void
mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
- rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
+ rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
{
if (!reload_completed
&& TUNE_MACC_CHAINS
static int
mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
- rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
+ rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
{
mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
return mips_issue_rate ();
static int
mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
- rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
+ rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
{
mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
return cached_can_issue_more;
/* Update round-robin counters for ALU1/2 and FALU1/2. */
static void
-mips_ls2_variable_issue (rtx insn)
+mips_ls2_variable_issue (rtx_insn *insn)
{
if (mips_ls2.alu1_turn_p)
{
static int
mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
- rtx insn, int more)
+ rtx_insn *insn, int more)
{
/* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
if (USEFUL_INSN_P (insn))
/* Flags that indicate when a built-in function is available.
BUILTIN_AVAIL_NON_MIPS16
- The function is available on the current target, but only
- in non-MIPS16 mode. */
+ The function is available on the current target if !TARGET_MIPS16.
+
+ BUILTIN_AVAIL_MIPS16
+ The function is available on the current target if TARGET_MIPS16. */
#define BUILTIN_AVAIL_NON_MIPS16 1
+#define BUILTIN_AVAIL_MIPS16 2
/* Declare an availability predicate for built-in functions that
require non-MIPS16 mode and also require COND to be true.
return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
}
+/* Declare an availability predicate for built-in functions that
+ support both MIPS16 and non-MIPS16 code and also require COND
+ to be true. NAME is the main part of the predicate's name. */
+#define AVAIL_ALL(NAME, COND) \
+ static unsigned int \
+ mips_builtin_avail_##NAME (void) \
+ { \
+ return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \
+ }
+
/* This structure describes a single built-in function. */
struct mips_builtin_description {
/* The code of the main .md file instruction. See mips_builtin_type
unsigned int (*avail) (void);
};
+AVAIL_ALL (hard_float, TARGET_HARD_FLOAT_ABI)
AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
+AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
#define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
#define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
#define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
-#define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
-#define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
-#define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
-#define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
-#define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
-#define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
static const struct mips_builtin_description mips_builtins[] = {
+#define MIPS_GET_FCSR 0
+ DIRECT_BUILTIN (get_fcsr, MIPS_USI_FTYPE_VOID, hard_float),
+#define MIPS_SET_FCSR 1
+ DIRECT_NO_TARGET_BUILTIN (set_fcsr, MIPS_VOID_FTYPE_USI, hard_float),
+
DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
+ /* Built-in functions for the DSP ASE (64-bit only). */
+ DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64),
+
/* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
- LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI),
- LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI),
+ LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
+ LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
return mips_builtin_decls[code];
}
-/* Take argument ARGNO from EXP's argument list and convert it into a
- form suitable for input operand OPNO of instruction ICODE. Return the
- value. */
+/* Take argument ARGNO from EXP's argument list and convert it into
+ an expand operand. Store the operand in *OP. */
-static rtx
-mips_prepare_builtin_arg (enum insn_code icode,
- unsigned int opno, tree exp, unsigned int argno)
+static void
+mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
+ unsigned int argno)
{
tree arg;
rtx value;
- enum machine_mode mode;
arg = CALL_EXPR_ARG (exp, argno);
value = expand_normal (arg);
- mode = insn_data[icode].operand[opno].mode;
- if (!insn_data[icode].operand[opno].predicate (value, mode))
- {
- /* We need to get the mode from ARG for two reasons:
+ create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
+}
- - to cope with address operands, where MODE is the mode of the
- memory, rather than of VALUE itself.
+/* Expand instruction ICODE as part of a built-in function sequence.
+ Use the first NOPS elements of OPS as the instruction's operands.
+ HAS_TARGET_P is true if operand 0 is a target; it is false if the
+ instruction has no target.
- - to cope with special predicates like pmode_register_operand,
- where MODE is VOIDmode. */
- value = copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg)), value);
+ Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
- /* Check the predicate again. */
- if (!insn_data[icode].operand[opno].predicate (value, mode))
- {
- error ("invalid argument to built-in function");
- return const0_rtx;
- }
+static rtx
+mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
+ struct expand_operand *ops, bool has_target_p)
+{
+ if (!maybe_expand_insn (icode, nops, ops))
+ {
+ error ("invalid argument to built-in function");
+ return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
}
-
- return value;
+ return has_target_p ? ops[0].value : const0_rtx;
}
-/* Return an rtx suitable for output operand OP of instruction ICODE.
- If TARGET is non-null, try to use it where possible. */
+/* Expand a floating-point comparison for built-in function call EXP.
+ The first NARGS arguments are the values to be compared. ICODE is
+ the .md pattern that does the comparison and COND is the condition
+ that is being tested. Return an rtx for the result. */
static rtx
-mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
+mips_expand_builtin_compare_1 (enum insn_code icode,
+ enum mips_fp_condition cond,
+ tree exp, int nargs)
{
- enum machine_mode mode;
+ struct expand_operand ops[MAX_RECOG_OPERANDS];
+ rtx output;
+ int opno, argno;
- mode = insn_data[icode].operand[op].mode;
- if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
- target = gen_reg_rtx (mode);
+ /* The instruction should have a target operand, an operand for each
+ argument, and an operand for COND. */
+ gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
- return target;
+ output = mips_allocate_fcc (insn_data[(int) icode].operand[0].mode);
+ opno = 0;
+ create_fixed_operand (&ops[opno++], output);
+ for (argno = 0; argno < nargs; argno++)
+ mips_prepare_builtin_arg (&ops[opno++], exp, argno);
+ create_integer_operand (&ops[opno++], (int) cond);
+ return mips_expand_builtin_insn (icode, opno, ops, true);
}
/* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
bool has_target_p)
{
- rtx ops[MAX_RECOG_OPERANDS];
+ struct expand_operand ops[MAX_RECOG_OPERANDS];
int opno, argno;
/* Map any target to operand 0. */
opno = 0;
if (has_target_p)
- {
- target = mips_prepare_builtin_target (icode, opno, target);
- ops[opno] = target;
- opno++;
- }
-
- /* Map the arguments to the other operands. The n_operands value
- for an expander includes match_dups and match_scratches as well as
- match_operands, so n_operands is only an upper bound on the number
- of arguments to the expander function. */
- gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
- for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
- ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
-
- switch (opno)
- {
- case 2:
- emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
- break;
+ create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
- case 3:
- emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
- break;
-
- case 4:
- emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
- break;
+ /* Map the arguments to the other operands. */
+ gcc_assert (opno + call_expr_nargs (exp)
+ == insn_data[icode].n_generator_args);
+ for (argno = 0; argno < call_expr_nargs (exp); argno++)
+ mips_prepare_builtin_arg (&ops[opno++], exp, argno);
- default:
- gcc_unreachable ();
- }
- return target;
+ return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
}
/* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
enum insn_code icode, enum mips_fp_condition cond,
rtx target, tree exp)
{
- rtx cmp_result, op0, op1;
-
- cmp_result = mips_prepare_builtin_target (icode, 0, 0);
- op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
- op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
- emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
+ struct expand_operand ops[4];
+ rtx cmp_result;
- icode = CODE_FOR_mips_cond_move_tf_ps;
- target = mips_prepare_builtin_target (icode, 0, target);
+ cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
+ create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
if (type == MIPS_BUILTIN_MOVT)
{
- op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
- op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
+ mips_prepare_builtin_arg (&ops[2], exp, 2);
+ mips_prepare_builtin_arg (&ops[1], exp, 3);
}
else
{
- op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
- op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
+ mips_prepare_builtin_arg (&ops[1], exp, 2);
+ mips_prepare_builtin_arg (&ops[2], exp, 3);
}
- emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
- return target;
+ create_fixed_operand (&ops[3], cmp_result);
+ return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
+ 4, ops, true);
}
/* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
mips_builtin_branch_and_move (rtx condition, rtx target,
rtx value_if_true, rtx value_if_false)
{
- rtx true_label, done_label;
+ rtx_code_label *true_label, *done_label;
true_label = gen_label_rtx ();
done_label = gen_label_rtx ();
enum insn_code icode, enum mips_fp_condition cond,
rtx target, tree exp)
{
- rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS];
- int argno;
+ rtx offset, condition, cmp_result;
if (target == 0 || GET_MODE (target) != SImode)
target = gen_reg_rtx (SImode);
-
- /* The instruction should have a target operand, an operand for each
- argument, and an operand for COND. */
- gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands);
-
- /* Prepare the operands to the comparison. */
- cmp_result = mips_prepare_builtin_target (icode, 0, 0);
- for (argno = 0; argno < call_expr_nargs (exp); argno++)
- args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno);
-
- switch (insn_data[icode].n_operands)
- {
- case 4:
- emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
- GEN_INT (cond)));
- break;
-
- case 6:
- emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
- args[2], args[3], GEN_INT (cond)));
- break;
-
- default:
- gcc_unreachable ();
- }
+ cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
+ call_expr_nargs (exp));
/* If the comparison sets more than one register, we define the result
to be 0 if all registers are false and -1 if all registers are true.
d = &mips_builtins[fcode];
avail = d->avail ();
gcc_assert (avail != 0);
- if (TARGET_MIPS16)
+ if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16))
{
error ("built-in function %qE not supported for MIPS16",
DECL_NAME (fndecl));
struct mips16_constant {
struct mips16_constant *next;
rtx value;
- rtx label;
+ rtx_code_label *label;
enum machine_mode mode;
};
/* Add constant VALUE to POOL and return its label. MODE is the
value's mode (used for CONST_INTs, etc.). */
-static rtx
+static rtx_code_label *
mips16_add_constant (struct mips16_constant_pool *pool,
rtx value, enum machine_mode mode)
{
/* Output constant VALUE after instruction INSN and return the last
instruction emitted. MODE is the mode of the constant. */
-static rtx
-mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
+static rtx_insn *
+mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx_insn *insn)
{
if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
{
/* Dump out the constants in CONSTANTS after INSN. */
static void
-mips16_emit_constants (struct mips16_constant *constants, rtx insn)
+mips16_emit_constants (struct mips16_constant *constants, rtx_insn *insn)
{
struct mips16_constant *c, *next;
int align;
/* Return the length of instruction INSN. */
static int
-mips16_insn_length (rtx insn)
+mips16_insn_length (rtx_insn *insn)
{
- if (JUMP_P (insn))
+ if (JUMP_TABLE_DATA_P (insn))
{
rtx body = PATTERN (insn);
if (GET_CODE (body) == ADDR_VEC)
return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
- if (GET_CODE (body) == ADDR_DIFF_VEC)
+ else if (GET_CODE (body) == ADDR_DIFF_VEC)
return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
+ else
+ gcc_unreachable ();
}
return get_attr_length (insn);
}
static void
mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
{
- rtx base, offset, label;
+ rtx base, offset;
+ rtx_code_label *label;
split_const (*x, &base, &offset);
if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
{
- label = mips16_add_constant (pool, get_pool_constant (base),
+ label = mips16_add_constant (pool, copy_rtx (get_pool_constant (base)),
get_pool_mode (base));
base = gen_rtx_LABEL_REF (Pmode, label);
*x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
INSN is the instruction we're rewriting and POOL points to the current
constant pool. */
struct mips16_rewrite_pool_refs_info {
- rtx insn;
+ rtx_insn *insn;
struct mips16_constant_pool *pool;
};
return -1;
}
+ /* Don't rewrite the __mips16_rdwr symbol. */
+ if (GET_CODE (*x) == UNSPEC && XINT (*x, 1) == UNSPEC_TLS_GET_TP)
+ return -1;
+
if (TARGET_MIPS16_TEXT_LOADS)
mips16_rewrite_pool_constant (info->pool, x);
|| TARGET_RELAX_PIC_CALLS);
}
-/* Build MIPS16 constant pools. */
+/* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
+ otherwise assume that they are already split. */
static void
-mips16_lay_out_constants (void)
+mips16_lay_out_constants (bool split_p)
{
struct mips16_constant_pool pool;
struct mips16_rewrite_pool_refs_info info;
- rtx insn, barrier;
+ rtx_insn *insn, *barrier;
if (!TARGET_MIPS16_PCREL_LOADS)
return;
- if (mips_cfg_in_reorg ())
- split_all_insns ();
- else
- split_all_insns_noflow ();
+ if (split_p)
+ {
+ if (mips_cfg_in_reorg ())
+ split_all_insns ();
+ else
+ split_all_insns_noflow ();
+ }
barrier = 0;
memset (&pool, 0, sizeof (pool));
for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
do it immediately before INSN. */
if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
{
- rtx label, jump;
+ rtx_code_label *label;
+ rtx_insn *jump;
label = gen_label_rtx ();
virtual_incoming_args_rtx (which should never occur in X otherwise). */
static rtx
-r10k_simplify_address (rtx x, rtx insn)
+r10k_simplify_address (rtx x, rtx_insn *insn)
{
- rtx newx, op0, op1, set, def_insn, note;
+ rtx newx, op0, op1, set, note;
+ rtx_insn *def_insn;
df_ref use, def;
struct df_link *defs;
/* Replace the incoming value of $sp with
virtual_incoming_args_rtx. */
if (x == stack_pointer_rtx
- && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
+ && DF_REF_BB (def) == ENTRY_BLOCK_PTR_FOR_FN (cfun))
newx = virtual_incoming_args_rtx;
}
else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
expression; it might not be a legitimate address. */
static bool
-r10k_safe_address_p (rtx x, rtx insn)
+r10k_safe_address_p (rtx x, rtx_insn *insn)
{
rtx base, offset;
HOST_WIDE_INT offset_val;
a link-time-constant address. */
static bool
-r10k_safe_mem_expr_p (tree expr, rtx offset)
+r10k_safe_mem_expr_p (tree expr, unsigned HOST_WIDE_INT offset)
{
- if (expr == NULL_TREE
- || offset == NULL_RTX
- || !CONST_INT_P (offset)
- || INTVAL (offset) < 0
- || INTVAL (offset) >= int_size_in_bytes (TREE_TYPE (expr)))
- return false;
+ HOST_WIDE_INT bitoffset, bitsize;
+ tree inner, var_offset;
+ enum machine_mode mode;
+ int unsigned_p, volatile_p;
- while (TREE_CODE (expr) == COMPONENT_REF)
- {
- expr = TREE_OPERAND (expr, 0);
- if (expr == NULL_TREE)
- return false;
- }
+ inner = get_inner_reference (expr, &bitsize, &bitoffset, &var_offset, &mode,
+ &unsigned_p, &volatile_p, false);
+ if (!DECL_P (inner) || !DECL_SIZE_UNIT (inner) || var_offset)
+ return false;
- return DECL_P (expr);
+ offset += bitoffset / BITS_PER_UNIT;
+ return offset < tree_to_uhwi (DECL_SIZE_UNIT (inner));
}
/* A for_each_rtx callback for which DATA points to the instruction
if (!MEM_P (mem))
return 0;
- if (r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
+ if (MEM_EXPR (mem)
+ && MEM_OFFSET_KNOWN_P (mem)
+ && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
return -1;
- if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
+ if (r10k_safe_address_p (XEXP (mem, 0), (rtx_insn *) data))
return -1;
return 1;
r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
void *data)
{
- rtx *insn_ptr;
+ rtx_insn **insn_ptr;
- insn_ptr = (rtx *) data;
+ insn_ptr = (rtx_insn **) data;
if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
- *insn_ptr = NULL_RTX;
+ *insn_ptr = NULL;
}
/* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
cache barrier. */
static bool
-r10k_needs_protection_p (rtx insn)
+r10k_needs_protection_p (rtx_insn *insn)
{
if (CALL_P (insn))
return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
FOR_EACH_EDGE (e, ei, bb->preds)
if (!single_succ_p (e->src)
- || !TEST_BIT (protected_bbs, e->src->index)
+ || !bitmap_bit_p (protected_bbs, e->src->index)
|| (e->flags & EDGE_COMPLEX) != 0)
return false;
return true;
unsigned int i, n;
basic_block bb;
sbitmap protected_bbs;
- rtx insn, end, unprotected_region;
+ rtx_insn *insn, *end;
+ rtx unprotected_region;
if (TARGET_MIPS16)
{
/* Bit X of PROTECTED_BBS is set if the last operation in basic block
X is protected by a cache barrier. */
- protected_bbs = sbitmap_alloc (last_basic_block);
- sbitmap_zero (protected_bbs);
+ protected_bbs = sbitmap_alloc (last_basic_block_for_fn (cfun));
+ bitmap_clear (protected_bbs);
/* Iterate over the basic blocks in reverse post-order. */
- rev_post_order = XNEWVEC (int, last_basic_block);
+ rev_post_order = XNEWVEC (int, last_basic_block_for_fn (cfun));
n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
for (i = 0; i < n; i++)
{
- bb = BASIC_BLOCK (rev_post_order[i]);
+ bb = BASIC_BLOCK_FOR_FN (cfun, rev_post_order[i]);
/* If this block is only reached by unconditional edges, and if the
source of every edge is protected, the beginning of the block is
/* Record whether the end of this block is protected. */
if (unprotected_region == NULL_RTX)
- SET_BIT (protected_bbs, bb->index);
+ bitmap_set_bit (protected_bbs, bb->index);
}
XDELETEVEC (rev_post_order);
SECOND_CALL. */
static rtx
-mips_call_expr_from_insn (rtx insn, rtx *second_call)
+mips_call_expr_from_insn (rtx_insn *insn, rtx *second_call)
{
rtx x;
rtx x2;
}
/* REG is set in DEF. See if the definition is one of the ways we load a
- register with a symbol address for a mips_use_pic_fn_addr_reg_p call. If
- it is return the symbol reference of the function, otherwise return
- NULL_RTX. */
+ register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
+ If it is, return the symbol reference of the function, otherwise return
+ NULL_RTX.
+
+ If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
+ the values of source registers, otherwise treat such registers as
+ having an unknown value. */
static rtx
-mips_pic_call_symbol_from_set (df_ref def, rtx reg)
+mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
{
- rtx def_insn, set;
+ rtx_insn *def_insn;
+ rtx set;
if (DF_REF_IS_ARTIFICIAL (def))
return NULL_RTX;
{
rtx note, src, symbol;
- /* First, look at REG_EQUAL/EQUIV notes. */
- note = find_reg_equal_equiv_note (def_insn);
- if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
- return XEXP (note, 0);
-
- /* For %call16 references we don't have REG_EQUAL. */
+ /* First see whether the source is a plain symbol. This is used
+ when calling symbols that are not lazily bound. */
src = SET_SRC (set);
+ if (GET_CODE (src) == SYMBOL_REF)
+ return src;
+
+ /* Handle %call16 references. */
symbol = mips_strip_unspec_call (src);
if (symbol)
{
return symbol;
}
- /* Follow simple register copies. */
- if (REG_P (src))
- return mips_find_pic_call_symbol (def_insn, src);
+ /* If we have something more complicated, look for a
+ REG_EQUAL or REG_EQUIV note. */
+ note = find_reg_equal_equiv_note (def_insn);
+ if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
+ return XEXP (note, 0);
+
+ /* Follow at most one simple register copy. Such copies are
+ interesting in cases like:
+
+ for (...)
+ {
+ locally_binding_fn (...);
+ }
+
+ and:
+
+ locally_binding_fn (...);
+ ...
+ locally_binding_fn (...);
+
+ where the load of locally_binding_fn can legitimately be
+ hoisted or shared. However, we do not expect to see complex
+ chains of copies, so a full worklist solution to the problem
+ would probably be overkill. */
+ if (recurse_p && REG_P (src))
+ return mips_find_pic_call_symbol (def_insn, src, false);
}
return NULL_RTX;
}
-/* Find the definition of the use of REG in INSN. See if the definition is
- one of the ways we load a register with a symbol address for a
- mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference of
- the function, otherwise return NULL_RTX. */
+/* Find the definition of the use of REG in INSN. See if the definition
+ is one of the ways we load a register with a symbol address for a
+ mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
+ of the function, otherwise return NULL_RTX. RECURSE_P is as for
+ mips_pic_call_symbol_from_set. */
static rtx
-mips_find_pic_call_symbol (rtx insn, rtx reg)
+mips_find_pic_call_symbol (rtx_insn *insn, rtx reg, bool recurse_p)
{
df_ref use;
struct df_link *defs;
defs = DF_REF_CHAIN (use);
if (!defs)
return NULL_RTX;
- symbol = mips_pic_call_symbol_from_set (defs->ref, reg);
+ symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
if (!symbol)
return NULL_RTX;
{
rtx other;
- other = mips_pic_call_symbol_from_set (defs->ref, reg);
+ other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
if (!rtx_equal_p (symbol, other))
return NULL_RTX;
}
mips_annotate_pic_calls (void)
{
basic_block bb;
- rtx insn;
+ rtx_insn *insn;
- FOR_EACH_BB (bb)
+ FOR_EACH_BB_FN (bb, cfun)
FOR_BB_INSNS (bb, insn)
{
rtx call, reg, symbol, second_call;
if (!REG_P (reg))
continue;
- symbol = mips_find_pic_call_symbol (insn, reg);
+ symbol = mips_find_pic_call_symbol (insn, reg, true);
if (symbol)
{
mips_annotate_pic_call_expr (call, symbol);
}
\f
/* A temporary variable used by for_each_rtx callbacks, etc. */
-static rtx mips_sim_insn;
+static rtx_insn *mips_sim_insn;
/* A structure representing the state of the processor pipeline.
Used by the mips_sim_* family of functions. */
LAST_SET[X].TIME is the time at which that instruction was issued.
INSN is null if no instruction has yet set register X. */
struct {
- rtx insn;
+ rtx_insn *insn;
unsigned int time;
} last_set[FIRST_PSEUDO_REGISTER];
static void
mips_sim_reset (struct mips_sim *state)
{
+ curr_state = state->dfa_state;
+
state->time = 0;
state->insns_left = state->issue_rate;
memset (&state->last_set, 0, sizeof (state->last_set));
- state_reset (state->dfa_state);
+ state_reset (curr_state);
+
+ targetm.sched.init (0, false, 0);
+ advance_state (curr_state);
}
/* Initialize STATE before its first use. DFA_STATE points to an
static void
mips_sim_init (struct mips_sim *state, state_t dfa_state)
{
+ if (targetm.sched.init_dfa_pre_cycle_insn)
+ targetm.sched.init_dfa_pre_cycle_insn ();
+
+ if (targetm.sched.init_dfa_post_cycle_insn)
+ targetm.sched.init_dfa_post_cycle_insn ();
+
state->issue_rate = mips_issue_rate ();
state->dfa_state = dfa_state;
mips_sim_reset (state);
static void
mips_sim_next_cycle (struct mips_sim *state)
{
+ curr_state = state->dfa_state;
+
state->time++;
state->insns_left = state->issue_rate;
- state_transition (state->dfa_state, 0);
+ advance_state (curr_state);
}
/* Advance simulation state STATE until instruction INSN can read
register REG. */
static void
-mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
+mips_sim_wait_reg (struct mips_sim *state, rtx_insn *insn, rtx reg)
{
unsigned int regno, end_regno;
dependencies are satisfied. */
static void
-mips_sim_wait_regs (struct mips_sim *state, rtx insn)
+mips_sim_wait_regs (struct mips_sim *state, rtx_insn *insn)
{
mips_sim_insn = insn;
note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
instruction INSN are available. */
static void
-mips_sim_wait_units (struct mips_sim *state, rtx insn)
+mips_sim_wait_units (struct mips_sim *state, rtx_insn *insn)
{
state_t tmp_state;
/* Advance simulation state STATE until INSN is ready to issue. */
static void
-mips_sim_wait_insn (struct mips_sim *state, rtx insn)
+mips_sim_wait_insn (struct mips_sim *state, rtx_insn *insn)
{
mips_sim_wait_regs (state, insn);
mips_sim_wait_units (state, insn);
been called). */
static void
-mips_sim_issue_insn (struct mips_sim *state, rtx insn)
+mips_sim_issue_insn (struct mips_sim *state, rtx_insn *insn)
{
- state_transition (state->dfa_state, insn);
- state->insns_left--;
+ curr_state = state->dfa_state;
+
+ state_transition (curr_state, insn);
+ state->insns_left = targetm.sched.variable_issue (0, false, insn,
+ state->insns_left);
mips_sim_insn = insn;
note_stores (PATTERN (insn), mips_sim_record_set, state);
SEQUENCE. */
static void
-mips_sim_finish_insn (struct mips_sim *state, rtx insn)
+mips_sim_finish_insn (struct mips_sim *state, rtx_insn *insn)
{
/* If INSN is a jump with an implicit delay slot, simulate a nop. */
if (JUMP_P (insn))
break;
}
}
+
+/* Use simulator state STATE to calculate the execution time of
+ instruction sequence SEQ. */
+
+static unsigned int
+mips_seq_time (struct mips_sim *state, rtx_insn *seq)
+{
+ mips_sim_reset (state);
+ for (rtx_insn *insn = seq; insn; insn = NEXT_INSN (insn))
+ {
+ mips_sim_wait_insn (state, insn);
+ mips_sim_issue_insn (state, insn);
+ }
+ return state->time;
+}
+\f
+/* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
+ setting SETTING, using STATE to simulate instruction sequences. */
+
+static unsigned int
+mips_mult_zero_zero_cost (struct mips_sim *state, bool setting)
+{
+ mips_tuning_info.fast_mult_zero_zero_p = setting;
+ start_sequence ();
+
+ enum machine_mode dword_mode = TARGET_64BIT ? TImode : DImode;
+ rtx hilo = gen_rtx_REG (dword_mode, MD_REG_FIRST);
+ mips_emit_move_or_split (hilo, const0_rtx, SPLIT_FOR_SPEED);
+
+ /* If the target provides mulsidi3_32bit then that's the most likely
+ consumer of the result. Test for bypasses. */
+ if (dword_mode == DImode && HAVE_maddsidi4)
+ {
+ rtx gpr = gen_rtx_REG (SImode, GP_REG_FIRST + 4);
+ emit_insn (gen_maddsidi4 (hilo, gpr, gpr, hilo));
+ }
+
+ unsigned int time = mips_seq_time (state, get_insns ());
+ end_sequence ();
+ return time;
+}
+
+/* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
+ and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
+ Prefer MULT -- which is shorter -- in the event of a tie. */
+
+static void
+mips_set_fast_mult_zero_zero_p (struct mips_sim *state)
+{
+ if (TARGET_MIPS16)
+ /* No MTLO or MTHI available. */
+ mips_tuning_info.fast_mult_zero_zero_p = true;
+ else
+ {
+ unsigned int true_time = mips_mult_zero_zero_cost (state, true);
+ unsigned int false_time = mips_mult_zero_zero_cost (state, false);
+ mips_tuning_info.fast_mult_zero_zero_p = (true_time <= false_time);
+ }
+}
+
+/* Set up costs based on the current architecture and tuning settings. */
+
+static void
+mips_set_tuning_info (void)
+{
+ if (mips_tuning_info.initialized_p
+ && mips_tuning_info.arch == mips_arch
+ && mips_tuning_info.tune == mips_tune
+ && mips_tuning_info.mips16_p == TARGET_MIPS16)
+ return;
+
+ mips_tuning_info.arch = mips_arch;
+ mips_tuning_info.tune = mips_tune;
+ mips_tuning_info.mips16_p = TARGET_MIPS16;
+ mips_tuning_info.initialized_p = true;
+
+ dfa_start ();
+
+ struct mips_sim state;
+ mips_sim_init (&state, alloca (state_size ()));
+
+ mips_set_fast_mult_zero_zero_p (&state);
+
+ dfa_finish ();
+}
+
+/* Implement TARGET_EXPAND_TO_RTL_HOOK. */
+
+static void
+mips_expand_to_rtl_hook (void)
+{
+ /* We need to call this at a point where we can safely create sequences
+ of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
+ need to call it at a point where the DFA infrastructure is not
+ already in use, so we can't just call it lazily on demand.
+
+ At present, mips_tuning_info is only needed during post-expand
+ RTL passes such as split_insns, so this hook should be early enough.
+ We may need to move the call elsewhere if mips_tuning_info starts
+ to be used for other things (such as rtx_costs, or expanders that
+ could be called during gimple optimization). */
+ mips_set_tuning_info ();
+}
\f
/* The VR4130 pipeline issues aligned pairs of instructions together,
but it stalls the second instruction if it depends on the first.
try to avoid it by swapping rs and rt. */
static void
-vr4130_avoid_branch_rt_conflict (rtx insn)
+vr4130_avoid_branch_rt_conflict (rtx_insn *insn)
{
- rtx first, second;
+ rtx_insn *first, *second;
first = SEQ_BEGIN (insn);
second = SEQ_END (insn);
vr4130_align_insns (void)
{
struct mips_sim state;
- rtx insn, subinsn, last, last2, next;
+ rtx_insn *insn, *subinsn, *last, *last2, *next;
bool aligned_p;
dfa_start ();
the fly to avoid a separate instruction walk. */
vr4130_avoid_branch_rt_conflict (insn);
- if (USEFUL_INSN_P (insn))
+ length = get_attr_length (insn);
+ if (length > 0 && USEFUL_INSN_P (insn))
FOR_EACH_SUBINSN (subinsn, insn)
{
mips_sim_wait_insn (&state, subinsn);
issuing at the same time as the branch. We therefore
insert a nop before the branch in order to align its
delay slot. */
+ gcc_assert (last2);
emit_insn_after (gen_nop (), last2);
aligned_p = false;
}
/* SUBINSN is the delay slot of INSN, but INSN is
currently unaligned. Insert a nop between
LAST and INSN to align it. */
+ gcc_assert (last);
emit_insn_after (gen_nop (), last);
aligned_p = true;
}
return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
}
+/* Hashtable helpers. */
+
+struct mips_lo_sum_offset_hasher : typed_free_remove <mips_lo_sum_offset>
+{
+ typedef mips_lo_sum_offset value_type;
+ typedef rtx_def compare_type;
+ static inline hashval_t hash (const value_type *);
+ static inline bool equal (const value_type *, const compare_type *);
+};
+
/* Hash-table callbacks for mips_lo_sum_offsets. */
-static hashval_t
-mips_lo_sum_offset_hash (const void *entry)
+inline hashval_t
+mips_lo_sum_offset_hasher::hash (const value_type *entry)
{
- return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
+ return mips_hash_base (entry->base);
}
-static int
-mips_lo_sum_offset_eq (const void *entry, const void *value)
+inline bool
+mips_lo_sum_offset_hasher::equal (const value_type *entry,
+ const compare_type *value)
{
- return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
- (const_rtx) value);
+ return rtx_equal_p (entry->base, value);
}
+typedef hash_table<mips_lo_sum_offset_hasher> mips_offset_table;
+
/* Look up symbolic constant X in HTAB, which is a hash table of
mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
paired with a recorded LO_SUM, otherwise record X in the table. */
static bool
-mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
+mips_lo_sum_offset_lookup (mips_offset_table *htab, rtx x,
+ enum insert_option option)
{
rtx base, offset;
- void **slot;
+ mips_lo_sum_offset **slot;
struct mips_lo_sum_offset *entry;
/* Split X into a base and offset. */
base = UNSPEC_ADDRESS (base);
/* Look up the base in the hash table. */
- slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
+ slot = htab->find_slot_with_hash (base, mips_hash_base (base), option);
if (slot == NULL)
return false;
mips_record_lo_sum (rtx *loc, void *data)
{
if (GET_CODE (*loc) == LO_SUM)
- mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
+ mips_lo_sum_offset_lookup ((mips_offset_table*) data,
+ XEXP (*loc, 1), INSERT);
return 0;
}
LO_SUMs in the current function. */
static bool
-mips_orphaned_high_part_p (htab_t htab, rtx insn)
+mips_orphaned_high_part_p (mips_offset_table *htab, rtx_insn *insn)
{
enum mips_symbol_type type;
rtx x, set;
LO_REG is an rtx for the LO register, used in dependence checking. */
static void
-mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
+mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, int *hilo_delay,
rtx *delayed_reg, rtx lo_reg)
{
rtx pattern, set;
static void
mips_reorg_process_insns (void)
{
- rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
+ rtx_insn *insn, *last_insn, *subinsn, *next_insn;
+ rtx lo_reg, delayed_reg;
int hilo_delay;
- htab_t htab;
/* Force all instructions to be split into their final form. */
split_all_insns_noflow ();
if (crtl->profile)
cfun->machine->all_noreorder_p = false;
- /* Code compiled with -mfix-vr4120 can't be all noreorder because
- we rely on the assembler to work around some errata. */
- if (TARGET_FIX_VR4120)
+ /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be
+ all noreorder because we rely on the assembler to work around some
+ errata. The R5900 too has several bugs. */
+ if (TARGET_FIX_VR4120
+ || TARGET_FIX_RM7000
+ || TARGET_FIX_24K
+ || TARGET_MIPS5900)
cfun->machine->all_noreorder_p = false;
/* The same is true for -mfix-vr4130 if we might generate MFLO or
if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
cfun->machine->all_noreorder_p = false;
- htab = htab_create (37, mips_lo_sum_offset_hash,
- mips_lo_sum_offset_eq, free);
+ mips_offset_table htab (37);
/* Make a first pass over the instructions, recording all the LO_SUMs. */
for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
FOR_EACH_SUBINSN (subinsn, insn)
if (USEFUL_INSN_P (subinsn))
- for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
+ {
+ rtx body = PATTERN (insn);
+ int noperands = asm_noperands (body);
+ if (noperands >= 0)
+ {
+ rtx *ops = XALLOCAVEC (rtx, noperands);
+ bool *used = XALLOCAVEC (bool, noperands);
+ const char *string = decode_asm_operands (body, ops, NULL, NULL,
+ NULL, NULL);
+ get_referenced_operands (string, used, noperands);
+ for (int i = 0; i < noperands; ++i)
+ if (used[i])
+ for_each_rtx (&ops[i], mips_record_lo_sum, &htab);
+ }
+ else
+ for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, &htab);
+ }
last_insn = 0;
hilo_delay = 2;
FOR_EACH_SUBINSN (subinsn, insn)
if (INSN_P (subinsn))
{
- if (mips_orphaned_high_part_p (htab, subinsn))
+ if (mips_orphaned_high_part_p (&htab, subinsn))
{
PATTERN (subinsn) = gen_nop ();
INSN_CODE (subinsn) = CODE_FOR_nop;
{
/* INSN is a single instruction. Delete it if it's an
orphaned high-part relocation. */
- if (mips_orphaned_high_part_p (htab, insn))
+ if (mips_orphaned_high_part_p (&htab, insn))
delete_insn (insn);
/* Also delete cache barriers if the last instruction
was an annulled branch. INSN will not be speculatively
executed. */
else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
&& last_insn
+ && JUMP_P (SEQ_BEGIN (last_insn))
&& INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
delete_insn (insn);
else
}
}
}
+}
+
+/* Return true if the function has a long branch instruction. */
+
+static bool
+mips_has_long_branch_p (void)
+{
+ rtx_insn *insn, *subinsn;
+ int normal_length;
+
+ /* We need up-to-date instruction lengths. */
+ shorten_branches (get_insns ());
+
+ /* Look for a branch that is longer than normal. The normal length for
+ non-MIPS16 branches is 8, because the length includes the delay slot.
+ It is 4 for MIPS16, because MIPS16 branches are extended instructions,
+ but they have no delay slot. */
+ normal_length = (TARGET_MIPS16 ? 4 : 8);
+ for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+ FOR_EACH_SUBINSN (subinsn, insn)
+ if (JUMP_P (subinsn)
+ && get_attr_length (subinsn) > normal_length
+ && (any_condjump_p (subinsn) || any_uncondjump_p (subinsn)))
+ return true;
- htab_delete (htab);
+ return false;
}
/* If we are using a GOT, but have not decided to use a global pointer yet,
static bool
mips_expand_ghost_gp_insns (void)
{
- rtx insn;
- int normal_length;
-
/* Quick exit if we already know that we will or won't need a
global pointer. */
if (!TARGET_USE_GOT
|| mips_must_initialize_gp_p ())
return false;
- shorten_branches (get_insns ());
-
- /* Look for a branch that is longer than normal. The normal length for
- non-MIPS16 branches is 8, because the length includes the delay slot.
- It is 4 for MIPS16, because MIPS16 branches are extended instructions,
- but they have no delay slot. */
- normal_length = (TARGET_MIPS16 ? 4 : 8);
- for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
- if (JUMP_P (insn)
- && USEFUL_INSN_P (insn)
- && get_attr_length (insn) > normal_length)
- break;
-
- if (insn == NULL_RTX)
+ /* Run a full check for long branches. */
+ if (!mips_has_long_branch_p ())
return false;
/* We've now established that we need $gp. */
df_finish_pass (false);
}
-/* Implement TARGET_MACHINE_DEPENDENT_REORG. */
+/* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
+ called very late in mips_reorg, but the caller is required to run
+ mips16_lay_out_constants on the result. */
static void
-mips_reorg (void)
+mips16_load_branch_target (rtx dest, rtx src)
{
- /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
- insn splitting in mips16_lay_out_constants, DF insn info is only kept up
- to date if the CFG is available. */
- if (mips_cfg_in_reorg ())
- compute_bb_for_insn ();
- mips16_lay_out_constants ();
- if (mips_cfg_in_reorg ())
+ if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
{
- mips_df_reorg ();
+ rtx page, low;
+
+ if (mips_cfun_has_cprestore_slot_p ())
+ mips_emit_move (dest, mips_cprestore_slot (dest, true));
+ else
+ mips_emit_move (dest, pic_offset_table_rtx);
+ page = mips_unspec_address (src, SYMBOL_GOTOFF_PAGE);
+ low = mips_unspec_address (src, SYMBOL_GOT_PAGE_OFST);
+ emit_insn (gen_rtx_SET (VOIDmode, dest,
+ PMODE_INSN (gen_unspec_got, (dest, page))));
+ emit_insn (gen_rtx_SET (VOIDmode, dest,
+ gen_rtx_LO_SUM (Pmode, dest, low)));
+ }
+ else
+ {
+ src = mips_unspec_address (src, SYMBOL_ABSOLUTE);
+ mips_emit_move (dest, src);
+ }
+}
+
+/* If we're compiling a MIPS16 function, look for and split any long branches.
+ This must be called after all other instruction modifications in
+ mips_reorg. */
+
+static void
+mips16_split_long_branches (void)
+{
+ bool something_changed;
+
+ if (!TARGET_MIPS16)
+ return;
+
+ /* Loop until the alignments for all targets are sufficient. */
+ do
+ {
+ rtx_insn *insn;
+
+ shorten_branches (get_insns ());
+ something_changed = false;
+ for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+ if (JUMP_P (insn)
+ && get_attr_length (insn) > 4
+ && (any_condjump_p (insn) || any_uncondjump_p (insn)))
+ {
+ rtx old_label, temp, saved_temp;
+ rtx_code_label *new_label;
+ rtx target;
+ rtx_insn *jump, *jump_sequence;
+
+ start_sequence ();
+
+ /* Free up a MIPS16 register by saving it in $1. */
+ saved_temp = gen_rtx_REG (Pmode, AT_REGNUM);
+ temp = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
+ emit_move_insn (saved_temp, temp);
+
+ /* Load the branch target into TEMP. */
+ old_label = JUMP_LABEL (insn);
+ target = gen_rtx_LABEL_REF (Pmode, old_label);
+ mips16_load_branch_target (temp, target);
+
+ /* Jump to the target and restore the register's
+ original value. */
+ jump = emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore,
+ (temp, temp, saved_temp)));
+ JUMP_LABEL (jump) = old_label;
+ LABEL_NUSES (old_label)++;
+
+ /* Rewrite any symbolic references that are supposed to use
+ a PC-relative constant pool. */
+ mips16_lay_out_constants (false);
+
+ if (simplejump_p (insn))
+ /* We're going to replace INSN with a longer form. */
+ new_label = NULL;
+ else
+ {
+ /* Create a branch-around label for the original
+ instruction. */
+ new_label = gen_label_rtx ();
+ emit_label (new_label);
+ }
+
+ jump_sequence = get_insns ();
+ end_sequence ();
+
+ emit_insn_after (jump_sequence, insn);
+ if (new_label)
+ invert_jump (insn, new_label, false);
+ else
+ delete_insn (insn);
+ something_changed = true;
+ }
+ }
+ while (something_changed);
+}
+
+/* Implement TARGET_MACHINE_DEPENDENT_REORG. */
+
+static void
+mips_reorg (void)
+{
+ /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
+ insn splitting in mips16_lay_out_constants, DF insn info is only kept up
+ to date if the CFG is available. */
+ if (mips_cfg_in_reorg ())
+ compute_bb_for_insn ();
+ mips16_lay_out_constants (true);
+ if (mips_cfg_in_reorg ())
+ {
+ mips_df_reorg ();
free_bb_for_insn ();
}
+}
+
+/* We use a machine specific pass to do a second machine dependent reorg
+ pass after delay branch scheduling. */
- if (optimize > 0 && flag_delayed_branch)
- dbr_schedule (get_insns ());
+static unsigned int
+mips_machine_reorg2 (void)
+{
mips_reorg_process_insns ();
if (!TARGET_MIPS16
&& TARGET_EXPLICIT_RELOCS
/* The expansion could invalidate some of the VR4130 alignment
optimizations, but this should be an extremely rare case anyhow. */
mips_reorg_process_insns ();
+ mips16_split_long_branches ();
+ return 0;
+}
+
+namespace {
+
+const pass_data pass_data_mips_machine_reorg2 =
+{
+ RTL_PASS, /* type */
+ "mach2", /* name */
+ OPTGROUP_NONE, /* optinfo_flags */
+ TV_MACH_DEP, /* tv_id */
+ 0, /* properties_required */
+ 0, /* properties_provided */
+ 0, /* properties_destroyed */
+ 0, /* todo_flags_start */
+ 0, /* todo_flags_finish */
+};
+
+class pass_mips_machine_reorg2 : public rtl_opt_pass
+{
+public:
+ pass_mips_machine_reorg2(gcc::context *ctxt)
+ : rtl_opt_pass(pass_data_mips_machine_reorg2, ctxt)
+ {}
+
+ /* opt_pass methods: */
+ virtual unsigned int execute (function *) { return mips_machine_reorg2 (); }
+
+}; // class pass_mips_machine_reorg2
+
+} // anon namespace
+
+rtl_opt_pass *
+make_pass_mips_machine_reorg2 (gcc::context *ctxt)
+{
+ return new pass_mips_machine_reorg2 (ctxt);
}
+
\f
/* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
in order to avoid duplicating too much logic from elsewhere. */
HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
tree function)
{
- rtx this_rtx, temp1, temp2, insn, fnaddr;
+ rtx this_rtx, temp1, temp2, fnaddr;
+ rtx_insn *insn;
bool use_sibcall_p;
/* Pretend to be a post-reload pass while generating rtl. */
/* Run just enough of rest_of_compilation. This sequence was
"borrowed" from alpha.c. */
insn = get_insns ();
- insn_locators_alloc ();
split_all_insns_noflow ();
- mips16_lay_out_constants ();
+ mips16_lay_out_constants (true);
shorten_branches (insn);
final_start_function (insn, file, 1);
final (insn, file, 1);
reload_completed = 0;
}
\f
-/* The last argument passed to mips_set_mips16_mode, or negative if the
- function hasn't been called yet.
- There are two copies of this information. One is saved and restored
- by the PCH process while the other is specific to this compiler
- invocation. The information calculated by mips_set_mips16_mode
- is invalid unless the two variables are the same. */
-static int was_mips16_p = -1;
-static GTY(()) int was_mips16_pch_p = -1;
+/* The last argument passed to mips_set_compression_mode,
+ or negative if the function hasn't been called yet. */
+static unsigned int old_compression_mode = -1;
-/* Set up the target-dependent global state so that it matches the
- current function's ISA mode. */
+/* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
+ which is either MASK_MIPS16 or MASK_MICROMIPS. */
static void
-mips_set_mips16_mode (int mips16_p)
+mips_set_compression_mode (unsigned int compression_mode)
{
- if (mips16_p == was_mips16_p
- && mips16_p == was_mips16_pch_p)
+
+ if (compression_mode == old_compression_mode)
return;
/* Restore base settings of various flags. */
align_loops = mips_base_align_loops;
align_jumps = mips_base_align_jumps;
align_functions = mips_base_align_functions;
+ target_flags &= ~(MASK_MIPS16 | MASK_MICROMIPS);
+ target_flags |= compression_mode;
- if (mips16_p)
+ if (compression_mode & MASK_MIPS16)
{
/* Switch to MIPS16 mode. */
target_flags |= MASK_MIPS16;
+ /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
+ target_flags &= ~MASK_SYNCI;
+
/* Don't run the scheduler before reload, since it tends to
increase register pressure. */
flag_schedule_insns = 0;
/* MIPS16 has no BAL instruction. */
target_flags &= ~MASK_RELAX_PIC_CALLS;
+ /* The R4000 errata don't apply to any known MIPS16 cores.
+ It's simpler to make the R4000 fixes and MIPS16 mode
+ mutually exclusive. */
+ target_flags &= ~MASK_FIX_R4000;
+
if (flag_pic && !TARGET_OLDABI)
sorry ("MIPS16 PIC for ABIs other than o32 and o64");
}
else
{
- /* Switch to normal (non-MIPS16) mode. */
- target_flags &= ~MASK_MIPS16;
+ /* Switch to microMIPS or the standard encoding. */
+
+ if (TARGET_MICROMIPS)
+ /* Avoid branch likely. */
+ target_flags &= ~MASK_BRANCHLIKELY;
/* Provide default values for align_* for 64-bit targets. */
if (TARGET_64BIT)
/* (Re)initialize MIPS target internals for new ISA. */
mips_init_relocs ();
- if (mips16_p)
+ if (compression_mode & MASK_MIPS16)
{
if (!mips16_globals)
- mips16_globals = save_target_globals ();
+ mips16_globals = save_target_globals_default_opts ();
else
restore_target_globals (mips16_globals);
}
else
restore_target_globals (&default_target_globals);
- was_mips16_p = mips16_p;
- was_mips16_pch_p = mips16_p;
+ old_compression_mode = compression_mode;
}
/* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
- function should use the MIPS16 ISA and switch modes accordingly. */
+ function should use the MIPS16 or microMIPS ISA and switch modes
+ accordingly. */
static void
mips_set_current_function (tree fndecl)
{
- mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
+ mips_set_compression_mode (mips_get_compress_mode (fndecl));
}
\f
/* Allocate a chunk of memory for per-function machine-dependent data. */
static struct machine_function *
mips_init_machine_status (void)
{
- return ggc_alloc_cleared_machine_function ();
+ return ggc_cleared_alloc<machine_function> ();
}
/* Return the processor associated with the given ISA level, or null
return NULL;
}
-/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
- with a final "000" replaced by "k". Ignore case.
-
- Note: this function is shared between GCC and GAS. */
-
-static bool
-mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
-{
- while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
- given++, canonical++;
-
- return ((*given == 0 && *canonical == 0)
- || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
-}
-
-/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
- CPU name. We've traditionally allowed a lot of variation here.
-
- Note: this function is shared between GCC and GAS. */
+/* Return a mips_cpu_info entry determined by an option valued
+ OPT. */
-static bool
-mips_matching_cpu_name_p (const char *canonical, const char *given)
+static const struct mips_cpu_info *
+mips_cpu_info_from_opt (int opt)
{
- /* First see if the name matches exactly, or with a final "000"
- turned into "k". */
- if (mips_strict_matching_cpu_name_p (canonical, given))
- return true;
-
- /* If not, try comparing based on numerical designation alone.
- See if GIVEN is an unadorned number, or 'r' followed by a number. */
- if (TOLOWER (*given) == 'r')
- given++;
- if (!ISDIGIT (*given))
- return false;
+ switch (opt)
+ {
+ case MIPS_ARCH_OPTION_FROM_ABI:
+ /* 'from-abi' selects the most compatible architecture for the
+ given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
+ ABIs. For the EABIs, we have to decide whether we're using
+ the 32-bit or 64-bit version. */
+ return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
+ : ABI_NEEDS_64BIT_REGS ? 3
+ : (TARGET_64BIT ? 3 : 1));
- /* Skip over some well-known prefixes in the canonical name,
- hoping to find a number there too. */
- if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
- canonical += 2;
- else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
- canonical += 2;
- else if (TOLOWER (canonical[0]) == 'r')
- canonical += 1;
+ case MIPS_ARCH_OPTION_NATIVE:
+ gcc_unreachable ();
- return mips_strict_matching_cpu_name_p (canonical, given);
+ default:
+ return &mips_cpu_info_table[opt];
+ }
}
-/* Return the mips_cpu_info entry for the processor or ISA given
- by CPU_STRING. Return null if the string isn't recognized.
-
- A similar function exists in GAS. */
+/* Return a default mips_cpu_info entry, given that no -march= option
+ was explicitly specified. */
static const struct mips_cpu_info *
-mips_parse_cpu (const char *cpu_string)
+mips_default_arch (void)
{
+#if defined (MIPS_CPU_STRING_DEFAULT)
unsigned int i;
- const char *s;
-
- /* In the past, we allowed upper-case CPU names, but it doesn't
- work well with the multilib machinery. */
- for (s = cpu_string; *s != 0; s++)
- if (ISUPPER (*s))
- {
- warning (0, "CPU names must be lower case");
- break;
- }
-
- /* 'from-abi' selects the most compatible architecture for the given
- ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
- EABIs, we have to decide whether we're using the 32-bit or 64-bit
- version. */
- if (strcasecmp (cpu_string, "from-abi") == 0)
- return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
- : ABI_NEEDS_64BIT_REGS ? 3
- : (TARGET_64BIT ? 3 : 1));
-
- /* 'default' has traditionally been a no-op. Probably not very useful. */
- if (strcasecmp (cpu_string, "default") == 0)
- return NULL;
-
for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
- if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
+ if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
return mips_cpu_info_table + i;
-
- return NULL;
+ gcc_unreachable ();
+#elif defined (MIPS_ISA_DEFAULT)
+ return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
+#else
+ /* 'from-abi' makes a good default: you get whatever the ABI
+ requires. */
+ return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
+#endif
}
/* Set up globals to generate code for the ISA or processor
mips_arch_info = info;
mips_arch = info->cpu;
mips_isa = info->isa;
+ if (mips_isa < 32)
+ mips_isa_rev = 0;
+ else
+ mips_isa_rev = (mips_isa & 31) + 1;
}
}
}
}
-/* Implement TARGET_HANDLE_OPTION. */
-
-static bool
-mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
-{
- switch (code)
- {
- case OPT_mabi_:
- if (strcmp (arg, "32") == 0)
- mips_abi = ABI_32;
- else if (strcmp (arg, "o64") == 0)
- mips_abi = ABI_O64;
- else if (strcmp (arg, "n32") == 0)
- mips_abi = ABI_N32;
- else if (strcmp (arg, "64") == 0)
- mips_abi = ABI_64;
- else if (strcmp (arg, "eabi") == 0)
- mips_abi = ABI_EABI;
- else
- return false;
- return true;
-
- case OPT_march_:
- case OPT_mtune_:
- return mips_parse_cpu (arg) != 0;
-
- case OPT_mips:
- mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
- return mips_isa_option_info != 0;
-
- case OPT_mno_flush_func:
- mips_cache_flush_func = NULL;
- return true;
-
- case OPT_mcode_readable_:
- if (strcmp (arg, "yes") == 0)
- mips_code_readable = CODE_READABLE_YES;
- else if (strcmp (arg, "pcrel") == 0)
- mips_code_readable = CODE_READABLE_PCREL;
- else if (strcmp (arg, "no") == 0)
- mips_code_readable = CODE_READABLE_NO;
- else
- return false;
- return true;
-
- case OPT_mr10k_cache_barrier_:
- if (strcmp (arg, "load-store") == 0)
- mips_r10k_cache_barrier = R10K_CACHE_BARRIER_LOAD_STORE;
- else if (strcmp (arg, "store") == 0)
- mips_r10k_cache_barrier = R10K_CACHE_BARRIER_STORE;
- else if (strcmp (arg, "none") == 0)
- mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
- else
- return false;
- return true;
-
- default:
- return true;
- }
-}
-
/* Implement TARGET_OPTION_OVERRIDE. */
static void
{
int i, start, regno, mode;
- /* Process flags as though we were generating non-MIPS16 code. */
- mips_base_mips16 = TARGET_MIPS16;
- target_flags &= ~MASK_MIPS16;
+ if (global_options_set.x_mips_isa_option)
+ mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
#ifdef SUBTARGET_OVERRIDE_OPTIONS
SUBTARGET_OVERRIDE_OPTIONS;
#endif
+ /* MIPS16 and microMIPS cannot coexist. */
+ if (TARGET_MICROMIPS && TARGET_MIPS16)
+ error ("unsupported combination: %s", "-mips16 -mmicromips");
+
+ /* Save the base compression state and process flags as though we
+ were generating uncompressed code. */
+ mips_base_compression_flags = TARGET_COMPRESSION;
+ target_flags &= ~TARGET_COMPRESSION;
+
/* -mno-float overrides -mhard-float and -msoft-float. */
if (TARGET_NO_FLOAT)
{
}
if (TARGET_FLIP_MIPS16)
- TARGET_INTERLINK_MIPS16 = 1;
+ TARGET_INTERLINK_COMPRESSED = 1;
/* Set the small data limit. */
mips_small_data_threshold = (global_options_set.x_g_switch_value
Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
The GAS and GCC code should be kept in sync as much as possible. */
- if (mips_arch_string != 0)
- mips_set_architecture (mips_parse_cpu (mips_arch_string));
+ if (global_options_set.x_mips_arch_option)
+ mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
if (mips_isa_option_info != 0)
{
}
if (mips_arch_info == 0)
- {
-#ifdef MIPS_CPU_STRING_DEFAULT
- mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
-#else
- mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
-#endif
- }
+ mips_set_architecture (mips_default_arch ());
if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
error ("%<-march=%s%> is not compatible with the selected ABI",
mips_arch_info->name);
/* Optimize for mips_arch, unless -mtune selects a different processor. */
- if (mips_tune_string != 0)
- mips_set_tune (mips_parse_cpu (mips_tune_string));
+ if (global_options_set.x_mips_tune_option)
+ mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
if (mips_tune_info == 0)
mips_set_tune (mips_arch_info);
/* End of code shared with GAS. */
- /* If no -mlong* option was given, infer it from the other options. */
- if ((target_flags_explicit & MASK_LONG64) == 0)
+ /* The R5900 FPU only supports single precision. */
+ if (TARGET_MIPS5900 && TARGET_HARD_FLOAT_ABI && TARGET_DOUBLE_FLOAT)
+ error ("unsupported combination: %s",
+ "-march=r5900 -mhard-float -mdouble-float");
+
+ /* If a -mlong* option was given, check that it matches the ABI,
+ otherwise infer the -mlong* setting from the other options. */
+ if ((target_flags_explicit & MASK_LONG64) != 0)
+ {
+ if (TARGET_LONG64)
+ {
+ if (mips_abi == ABI_N32)
+ error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
+ else if (mips_abi == ABI_32)
+ error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
+ else if (mips_abi == ABI_O64 && TARGET_ABICALLS)
+ /* We have traditionally allowed non-abicalls code to use
+ an LP64 form of o64. However, it would take a bit more
+ effort to support the combination of 32-bit GOT entries
+ and 64-bit pointers, so we treat the abicalls case as
+ an error. */
+ error ("the combination of %qs and %qs is incompatible with %qs",
+ "-mabi=o64", "-mabicalls", "-mlong64");
+ }
+ else
+ {
+ if (mips_abi == ABI_64)
+ error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
+ }
+ }
+ else
{
if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
target_flags |= MASK_LONG64;
warning (0, "the %qs architecture does not support branch-likely"
" instructions", mips_arch_info->name);
+ /* If the user hasn't specified -mimadd or -mno-imadd set
+ MASK_IMADD based on the target architecture and tuning
+ flags. */
+ if ((target_flags_explicit & MASK_IMADD) == 0)
+ {
+ if (ISA_HAS_MADD_MSUB &&
+ (mips_tune_info->tune_flags & PTF_AVOID_IMADD) == 0)
+ target_flags |= MASK_IMADD;
+ else
+ target_flags &= ~MASK_IMADD;
+ }
+ else if (TARGET_IMADD && !ISA_HAS_MADD_MSUB)
+ warning (0, "the %qs architecture does not support madd or msub"
+ " instructions", mips_arch_info->name);
+
/* The effect of -mabicalls isn't defined for the EABI. */
if (mips_abi == ABI_EABI && TARGET_ABICALLS)
{
target_flags &= ~MASK_ABICALLS;
}
+ /* PIC requires -mabicalls. */
+ if (flag_pic)
+ {
+ if (mips_abi == ABI_EABI)
+ error ("cannot generate position-independent code for %qs",
+ "-mabi=eabi");
+ else if (!TARGET_ABICALLS)
+ error ("position-independent code requires %qs", "-mabicalls");
+ }
+
if (TARGET_ABICALLS_PIC2)
/* We need to set flag_pic for executables as well as DSOs
because we may reference symbols that are not defined in
}
}
-#ifdef MIPS_TFMODE_FORMAT
- REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
-#endif
+ /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
+ for all its floating point. */
+ if (mips_nan != MIPS_IEEE_754_2008)
+ {
+ REAL_MODE_FORMAT (SFmode) = &mips_single_format;
+ REAL_MODE_FORMAT (DFmode) = &mips_double_format;
+ REAL_MODE_FORMAT (TFmode) = &mips_quad_format;
+ }
/* Make sure that the user didn't turn off paired single support when
MIPS-3D support is requested. */
/* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
and TARGET_HARD_FLOAT_ABI are both true. */
if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
- error ("%qs must be used with %qs",
- TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
- TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
+ {
+ error ("%qs must be used with %qs",
+ TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
+ TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
+ target_flags &= ~MASK_PAIRED_SINGLE_FLOAT;
+ TARGET_MIPS3D = 0;
+ }
- /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
- enabled. */
+ /* Make sure that -mpaired-single is only used on ISAs that support it.
+ We must disable it otherwise since it relies on other ISA properties
+ like ISA_HAS_8CC having their normal values. */
if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
- warning (0, "the %qs architecture does not support paired-single"
+ {
+ error ("the %qs architecture does not support paired-single"
" instructions", mips_arch_info->name);
+ target_flags &= ~MASK_PAIRED_SINGLE_FLOAT;
+ TARGET_MIPS3D = 0;
+ }
if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
&& !TARGET_CACHE_BUILTIN)
mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
}
- /* If TARGET_DSPR2, enable MASK_DSP. */
+ /* If TARGET_DSPR2, enable TARGET_DSP. */
if (TARGET_DSPR2)
- target_flags |= MASK_DSP;
+ TARGET_DSP = true;
/* .eh_frame addresses should be the same width as a C pointer.
Most MIPS ABIs support only one pointer size, so the assembler
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
- mips_dbx_regno[i] = INVALID_REGNUM;
+ mips_dbx_regno[i] = IGNORED_DWARF_REGNUM;
if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
mips_dwarf_regno[i] = i;
else
/* Default to working around R4000 errata only if the processor
was selected explicitly. */
if ((target_flags_explicit & MASK_FIX_R4000) == 0
- && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
+ && strcmp (mips_arch_info->name, "r4000") == 0)
target_flags |= MASK_FIX_R4000;
/* Default to working around R4400 errata only if the processor
was selected explicitly. */
if ((target_flags_explicit & MASK_FIX_R4400) == 0
- && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
+ && strcmp (mips_arch_info->name, "r4400") == 0)
target_flags |= MASK_FIX_R4400;
/* Default to working around R10000 errata only if the processor
was selected explicitly. */
if ((target_flags_explicit & MASK_FIX_R10000) == 0
- && mips_matching_cpu_name_p (mips_arch_info->name, "r10000"))
+ && strcmp (mips_arch_info->name, "r10000") == 0)
target_flags |= MASK_FIX_R10000;
/* Make sure that branch-likely instructions available when using
/* Now select the ISA mode.
- Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
- MIPS16 mode afterwards if need be. */
- mips_set_mips16_mode (false);
-}
+ Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
+ later if required. */
+ mips_set_compression_mode (0);
-/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
-static const struct default_options mips_option_optimization_table[] =
- {
- { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
- { OPT_LEVELS_NONE, 0, NULL, 0 }
- };
+ /* We register a second machine specific reorg pass after delay slot
+ filling. Registering the pass must be done at start up. It's
+ convenient to do it here. */
+ opt_pass *new_pass = make_pass_mips_machine_reorg2 (g);
+ struct register_pass_info insert_pass_mips_machine_reorg2 =
+ {
+ new_pass, /* pass */
+ "dbr", /* reference_pass_name */
+ 1, /* ref_pass_instance_number */
+ PASS_POS_INSERT_AFTER /* po_op */
+ };
+ register_pass (&insert_pass_mips_machine_reorg2);
+
+ if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
+ REAL_MODE_FORMAT (SFmode) = &spu_single_format;
+}
/* Swap the register information for registers I and I + 1, which
currently have the wrong endianness. Note that the registers'
global_regs[CCDSP_PO_REGNUM] = 1;
global_regs[CCDSP_SC_REGNUM] = 1;
}
- else
- {
- int regno;
+ else
+ AND_COMPL_HARD_REG_SET (accessible_reg_set,
+ reg_class_contents[(int) DSP_ACC_REGS]);
- for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
- fixed_regs[regno] = call_used_regs[regno] = 1;
- }
if (!TARGET_HARD_FLOAT)
{
- int regno;
-
- for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
- fixed_regs[regno] = call_used_regs[regno] = 1;
- for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
- fixed_regs[regno] = call_used_regs[regno] = 1;
+ AND_COMPL_HARD_REG_SET (accessible_reg_set,
+ reg_class_contents[(int) FP_REGS]);
+ AND_COMPL_HARD_REG_SET (accessible_reg_set,
+ reg_class_contents[(int) ST_REGS]);
}
- else if (! ISA_HAS_8CC)
+ else if (!ISA_HAS_8CC)
{
- int regno;
-
/* We only have a single condition-code register. We implement
this by fixing all the condition-code registers and generating
RTL that refers directly to ST_REG_FIRST. */
- for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
- fixed_regs[regno] = call_used_regs[regno] = 1;
+ AND_COMPL_HARD_REG_SET (accessible_reg_set,
+ reg_class_contents[(int) ST_REGS]);
+ SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
+ fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
}
- /* In MIPS16 mode, we permit the $t temporary registers to be used
- for reload. We prohibit the unused $s registers, since they
- are call-saved, and saving them via a MIPS16 register would
- probably waste more time than just reloading the value. */
if (TARGET_MIPS16)
{
+ /* In MIPS16 mode, we prohibit the unused $s registers, since they
+ are call-saved, and saving them via a MIPS16 register would
+ probably waste more time than just reloading the value.
+
+ We permit the $t temporary registers when optimizing for speed
+ but not when optimizing for space because using them results in
+ code that is larger (but faster) then not using them. We do
+ allow $24 (t8) because it is used in CMP and CMPI instructions
+ and $25 (t9) because it is used as the function call address in
+ SVR4 PIC code. */
+
fixed_regs[18] = call_used_regs[18] = 1;
fixed_regs[19] = call_used_regs[19] = 1;
fixed_regs[20] = call_used_regs[20] = 1;
fixed_regs[26] = call_used_regs[26] = 1;
fixed_regs[27] = call_used_regs[27] = 1;
fixed_regs[30] = call_used_regs[30] = 1;
+ if (optimize_size)
+ {
+ fixed_regs[8] = call_used_regs[8] = 1;
+ fixed_regs[9] = call_used_regs[9] = 1;
+ fixed_regs[10] = call_used_regs[10] = 1;
+ fixed_regs[11] = call_used_regs[11] = 1;
+ fixed_regs[12] = call_used_regs[12] = 1;
+ fixed_regs[13] = call_used_regs[13] = 1;
+ fixed_regs[14] = call_used_regs[14] = 1;
+ fixed_regs[15] = call_used_regs[15] = 1;
+ }
+
+ /* Do not allow HI and LO to be treated as register operands.
+ There are no MTHI or MTLO instructions (or any real need
+ for them) and one-way registers cannot easily be reloaded. */
+ AND_COMPL_HARD_REG_SET (operand_reg_set,
+ reg_class_contents[(int) MD_REGS]);
}
/* $f20-$f23 are call-clobbered for n64. */
if (mips_abi == ABI_64)
}
}
-/* Initialize vector TARGET to VALS. */
-
-void
-mips_expand_vector_init (rtx target, rtx vals)
-{
- enum machine_mode mode;
- enum machine_mode inner;
- unsigned int i, n_elts;
- rtx mem;
-
- mode = GET_MODE (target);
- inner = GET_MODE_INNER (mode);
- n_elts = GET_MODE_NUNITS (mode);
-
- gcc_assert (VECTOR_MODE_P (mode));
-
- mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
- for (i = 0; i < n_elts; i++)
- emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
- XVECEXP (vals, 0, i));
-
- emit_move_insn (target, mem);
-}
-
-/* When generating MIPS16 code, we want to allocate $24 (T_REG) before
- other registers for instructions for which it is possible. This
- encourages the compiler to use CMP in cases where an XOR would
- require some register shuffling. */
-
-void
-mips_order_regs_for_local_alloc (void)
-{
- int i;
-
- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- reg_alloc_order[i] = i;
-
- if (TARGET_MIPS16)
- {
- /* It really doesn't matter where we put register 0, since it is
- a fixed register anyhow. */
- reg_alloc_order[0] = 24;
- reg_alloc_order[24] = 0;
- }
-}
-
/* Implement EH_USES. */
bool
INSN has NOPERANDS operands, stored in OPVEC. */
static bool
-mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
+mips_need_noat_wrapper_p (rtx_insn *insn, rtx *opvec, int noperands)
{
int i;
/* Implement FINAL_PRESCAN_INSN. */
void
-mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
+mips_final_prescan_insn (rtx_insn *insn, rtx *opvec, int noperands)
{
if (mips_need_noat_wrapper_p (insn, opvec, noperands))
mips_push_asm_switch (&mips_noat);
/* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
static void
-mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
+mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx_insn *insn,
rtx *opvec, int noperands)
{
if (mips_need_noat_wrapper_p (insn, opvec, noperands))
case we still expand mulsidi3 for DMUL. */
if (ISA_HAS_DMUL3)
return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
+ if (TARGET_MIPS16)
+ return (signed_p
+ ? gen_mulsidi3_64bit_mips16
+ : gen_umulsidi3_64bit_mips16);
if (TARGET_FIX_R4000)
return NULL;
return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
}
else
{
+ if (TARGET_MIPS16)
+ return (signed_p
+ ? gen_mulsidi3_32bit_mips16
+ : gen_umulsidi3_32bit_mips16);
if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
}
}
-\f
-/* Return the size in bytes of the trampoline code, padded to
- TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
- function address immediately follow. */
-
-int
-mips_trampoline_code_size (void)
-{
- if (TARGET_USE_PIC_FN_ADDR_REG)
- return 4 * 4;
- else if (ptr_mode == DImode)
- return 8 * 4;
- else if (ISA_HAS_LOAD_DELAY)
- return 6 * 4;
- else
- return 4 * 4;
-}
-/* Implement TARGET_TRAMPOLINE_INIT. */
+/* Return true if PATTERN matches the kind of instruction generated by
+ umips_build_save_restore. SAVE_P is true for store. */
-static void
-mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
+bool
+umips_save_restore_pattern_p (bool save_p, rtx pattern)
{
- rtx addr, end_addr, high, low, opcode, mem;
- rtx trampoline[8];
- unsigned int i, j;
- HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
+ int n;
+ unsigned int i;
+ HOST_WIDE_INT first_offset = 0;
+ rtx first_base = 0;
+ unsigned int regmask = 0;
- /* Work out the offsets of the pointers from the start of the
- trampoline code. */
- end_addr_offset = mips_trampoline_code_size ();
- static_chain_offset = end_addr_offset;
- target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
+ for (n = 0; n < XVECLEN (pattern, 0); n++)
+ {
+ rtx set, reg, mem, this_base;
+ HOST_WIDE_INT this_offset;
- /* Get pointers to the beginning and end of the code block. */
- addr = force_reg (Pmode, XEXP (m_tramp, 0));
- end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
+ /* Check that we have a SET. */
+ set = XVECEXP (pattern, 0, n);
+ if (GET_CODE (set) != SET)
+ return false;
-#define OP(X) gen_int_mode (X, SImode)
+ /* Check that the SET is a load (if restoring) or a store
+ (if saving). */
+ mem = save_p ? SET_DEST (set) : SET_SRC (set);
+ if (!MEM_P (mem) || MEM_VOLATILE_P (mem))
+ return false;
- /* Build up the code in TRAMPOLINE. */
- i = 0;
- if (TARGET_USE_PIC_FN_ADDR_REG)
- {
- /* $25 contains the address of the trampoline. Emit code of the form:
+ /* Check that the address is the sum of base and a possibly-zero
+ constant offset. Determine if the offset is in range. */
+ mips_split_plus (XEXP (mem, 0), &this_base, &this_offset);
+ if (!REG_P (this_base))
+ return false;
- l[wd] $1, target_function_offset($25)
- l[wd] $static_chain, static_chain_offset($25)
+ if (n == 0)
+ {
+ if (!UMIPS_12BIT_OFFSET_P (this_offset))
+ return false;
+ first_base = this_base;
+ first_offset = this_offset;
+ }
+ else
+ {
+ /* Check that the save slots are consecutive. */
+ if (REGNO (this_base) != REGNO (first_base)
+ || this_offset != first_offset + UNITS_PER_WORD * n)
+ return false;
+ }
+
+ /* Check that SET's other operand is a register. */
+ reg = save_p ? SET_SRC (set) : SET_DEST (set);
+ if (!REG_P (reg))
+ return false;
+
+ regmask |= 1 << REGNO (reg);
+ }
+
+ for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
+ if (regmask == umips_swm_mask[i])
+ return true;
+
+ return false;
+}
+
+/* Return the assembly instruction for microMIPS LWM or SWM.
+ SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
+
+const char *
+umips_output_save_restore (bool save_p, rtx pattern)
+{
+ static char buffer[300];
+ char *s;
+ int n;
+ HOST_WIDE_INT offset;
+ rtx base, mem, set, last_set, last_reg;
+
+ /* Parse the pattern. */
+ gcc_assert (umips_save_restore_pattern_p (save_p, pattern));
+
+ s = strcpy (buffer, save_p ? "swm\t" : "lwm\t");
+ s += strlen (s);
+ n = XVECLEN (pattern, 0);
+
+ set = XVECEXP (pattern, 0, 0);
+ mem = save_p ? SET_DEST (set) : SET_SRC (set);
+ mips_split_plus (XEXP (mem, 0), &base, &offset);
+
+ last_set = XVECEXP (pattern, 0, n - 1);
+ last_reg = save_p ? SET_SRC (last_set) : SET_DEST (last_set);
+
+ if (REGNO (last_reg) == 31)
+ n--;
+
+ gcc_assert (n <= 9);
+ if (n == 0)
+ ;
+ else if (n == 1)
+ s += sprintf (s, "%s,", reg_names[16]);
+ else if (n < 9)
+ s += sprintf (s, "%s-%s,", reg_names[16], reg_names[15 + n]);
+ else if (n == 9)
+ s += sprintf (s, "%s-%s,%s,", reg_names[16], reg_names[23],
+ reg_names[30]);
+
+ if (REGNO (last_reg) == 31)
+ s += sprintf (s, "%s,", reg_names[31]);
+
+ s += sprintf (s, "%d(%s)", (int)offset, reg_names[REGNO (base)]);
+ return buffer;
+}
+
+/* Return true if MEM1 and MEM2 use the same base register, and the
+ offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
+ register into (from) which the contents of MEM1 will be loaded
+ (stored), depending on the value of LOAD_P.
+ SWAP_P is true when the 1st and 2nd instructions are swapped. */
+
+static bool
+umips_load_store_pair_p_1 (bool load_p, bool swap_p,
+ rtx first_reg, rtx mem1, rtx mem2)
+{
+ rtx base1, base2;
+ HOST_WIDE_INT offset1, offset2;
+
+ if (!MEM_P (mem1) || !MEM_P (mem2))
+ return false;
+
+ mips_split_plus (XEXP (mem1, 0), &base1, &offset1);
+ mips_split_plus (XEXP (mem2, 0), &base2, &offset2);
+
+ if (!REG_P (base1) || !rtx_equal_p (base1, base2))
+ return false;
+
+ /* Avoid invalid load pair instructions. */
+ if (load_p && REGNO (first_reg) == REGNO (base1))
+ return false;
+
+ /* We must avoid this case for anti-dependence.
+ Ex: lw $3, 4($3)
+ lw $2, 0($3)
+ first_reg is $2, but the base is $3. */
+ if (load_p
+ && swap_p
+ && REGNO (first_reg) + 1 == REGNO (base1))
+ return false;
+
+ if (offset2 != offset1 + 4)
+ return false;
+
+ if (!UMIPS_12BIT_OFFSET_P (offset1))
+ return false;
+
+ return true;
+}
+
+/* OPERANDS describes the operands to a pair of SETs, in the order
+ dest1, src1, dest2, src2. Return true if the operands can be used
+ in an LWP or SWP instruction; LOAD_P says which. */
+
+bool
+umips_load_store_pair_p (bool load_p, rtx *operands)
+{
+ rtx reg1, reg2, mem1, mem2;
+
+ if (load_p)
+ {
+ reg1 = operands[0];
+ reg2 = operands[2];
+ mem1 = operands[1];
+ mem2 = operands[3];
+ }
+ else
+ {
+ reg1 = operands[1];
+ reg2 = operands[3];
+ mem1 = operands[0];
+ mem2 = operands[2];
+ }
+
+ if (REGNO (reg2) == REGNO (reg1) + 1)
+ return umips_load_store_pair_p_1 (load_p, false, reg1, mem1, mem2);
+
+ if (REGNO (reg1) == REGNO (reg2) + 1)
+ return umips_load_store_pair_p_1 (load_p, true, reg2, mem2, mem1);
+
+ return false;
+}
+
+/* Return the assembly instruction for a microMIPS LWP or SWP in which
+ the first register is REG and the first memory slot is MEM.
+ LOAD_P is true for LWP. */
+
+static void
+umips_output_load_store_pair_1 (bool load_p, rtx reg, rtx mem)
+{
+ rtx ops[] = {reg, mem};
+
+ if (load_p)
+ output_asm_insn ("lwp\t%0,%1", ops);
+ else
+ output_asm_insn ("swp\t%0,%1", ops);
+}
+
+/* Output the assembly instruction for a microMIPS LWP or SWP instruction.
+ LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
+
+void
+umips_output_load_store_pair (bool load_p, rtx *operands)
+{
+ rtx reg1, reg2, mem1, mem2;
+ if (load_p)
+ {
+ reg1 = operands[0];
+ reg2 = operands[2];
+ mem1 = operands[1];
+ mem2 = operands[3];
+ }
+ else
+ {
+ reg1 = operands[1];
+ reg2 = operands[3];
+ mem1 = operands[0];
+ mem2 = operands[2];
+ }
+
+ if (REGNO (reg2) == REGNO (reg1) + 1)
+ {
+ umips_output_load_store_pair_1 (load_p, reg1, mem1);
+ return;
+ }
+
+ gcc_assert (REGNO (reg1) == REGNO (reg2) + 1);
+ umips_output_load_store_pair_1 (load_p, reg2, mem2);
+}
+
+/* Return true if REG1 and REG2 match the criteria for a movep insn. */
+
+bool
+umips_movep_target_p (rtx reg1, rtx reg2)
+{
+ int regno1, regno2, pair;
+ unsigned int i;
+ static const int match[8] = {
+ 0x00000060, /* 5, 6 */
+ 0x000000a0, /* 5, 7 */
+ 0x000000c0, /* 6, 7 */
+ 0x00200010, /* 4, 21 */
+ 0x00400010, /* 4, 22 */
+ 0x00000030, /* 4, 5 */
+ 0x00000050, /* 4, 6 */
+ 0x00000090 /* 4, 7 */
+ };
+
+ if (!REG_P (reg1) || !REG_P (reg2))
+ return false;
+
+ regno1 = REGNO (reg1);
+ regno2 = REGNO (reg2);
+
+ if (!GP_REG_P (regno1) || !GP_REG_P (regno2))
+ return false;
+
+ pair = (1 << regno1) | (1 << regno2);
+
+ for (i = 0; i < ARRAY_SIZE (match); i++)
+ if (pair == match[i])
+ return true;
+
+ return false;
+}
+\f
+/* Return the size in bytes of the trampoline code, padded to
+ TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
+ function address immediately follow. */
+
+int
+mips_trampoline_code_size (void)
+{
+ if (TARGET_USE_PIC_FN_ADDR_REG)
+ return 4 * 4;
+ else if (ptr_mode == DImode)
+ return 8 * 4;
+ else if (ISA_HAS_LOAD_DELAY)
+ return 6 * 4;
+ else
+ return 4 * 4;
+}
+
+/* Implement TARGET_TRAMPOLINE_INIT. */
+
+static void
+mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
+{
+ rtx addr, end_addr, high, low, opcode, mem;
+ rtx trampoline[8];
+ unsigned int i, j;
+ HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
+
+ /* Work out the offsets of the pointers from the start of the
+ trampoline code. */
+ end_addr_offset = mips_trampoline_code_size ();
+ static_chain_offset = end_addr_offset;
+ target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
+
+ /* Get pointers to the beginning and end of the code block. */
+ addr = force_reg (Pmode, XEXP (m_tramp, 0));
+ end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
+
+#define OP(X) gen_int_mode (X, SImode)
+
+ /* Build up the code in TRAMPOLINE. */
+ i = 0;
+ if (TARGET_USE_PIC_FN_ADDR_REG)
+ {
+ /* $25 contains the address of the trampoline. Emit code of the form:
+
+ l[wd] $1, target_function_offset($25)
+ l[wd] $static_chain, static_chain_offset($25)
jr $1
move $25,$1. */
trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
return GET_MODE_BITSIZE (mode) - 1;
}
+/* Implement TARGET_PREPARE_PCH_SAVE. */
+
+static void
+mips_prepare_pch_save (void)
+{
+ /* We are called in a context where the current MIPS16 vs. non-MIPS16
+ setting should be irrelevant. The question then is: which setting
+ makes most sense at load time?
+
+ The PCH is loaded before the first token is read. We should never
+ have switched into MIPS16 mode by that point, and thus should not
+ have populated mips16_globals. Nor can we load the entire contents
+ of mips16_globals from the PCH file, because mips16_globals contains
+ a combination of GGC and non-GGC data.
+
+ There is therefore no point in trying save the GGC part of
+ mips16_globals to the PCH file, or to preserve MIPS16ness across
+ the PCH save and load. The loading compiler would not have access
+ to the non-GGC parts of mips16_globals (either from the PCH file,
+ or from a copy that the loading compiler generated itself) and would
+ have to call target_reinit anyway.
+
+ It therefore seems best to switch back to non-MIPS16 mode at
+ save time, and to ensure that mips16_globals remains null after
+ a PCH load. */
+ mips_set_compression_mode (0);
+ mips16_globals = 0;
+}
+\f
+/* Generate or test for an insn that supports a constant permutation. */
+
+#define MAX_VECT_LEN 8
+
+struct expand_vec_perm_d
+{
+ rtx target, op0, op1;
+ unsigned char perm[MAX_VECT_LEN];
+ enum machine_mode vmode;
+ unsigned char nelt;
+ bool one_vector_p;
+ bool testing_p;
+};
+
+/* Construct (set target (vec_select op0 (parallel perm))) and
+ return true if that's a valid instruction in the active ISA. */
+
+static bool
+mips_expand_vselect (rtx target, rtx op0,
+ const unsigned char *perm, unsigned nelt)
+{
+ rtx rperm[MAX_VECT_LEN], x;
+ rtx_insn *insn;
+ unsigned i;
+
+ for (i = 0; i < nelt; ++i)
+ rperm[i] = GEN_INT (perm[i]);
+
+ x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
+ x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
+ x = gen_rtx_SET (VOIDmode, target, x);
+
+ insn = emit_insn (x);
+ if (recog_memoized (insn) < 0)
+ {
+ remove_insn (insn);
+ return false;
+ }
+ return true;
+}
+
+/* Similar, but generate a vec_concat from op0 and op1 as well. */
+
+static bool
+mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
+ const unsigned char *perm, unsigned nelt)
+{
+ enum machine_mode v2mode;
+ rtx x;
+
+ v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
+ x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
+ return mips_expand_vselect (target, x, perm, nelt);
+}
+
+/* Recognize patterns for even-odd extraction. */
+
+static bool
+mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
+{
+ unsigned i, odd, nelt = d->nelt;
+ rtx t0, t1, t2, t3;
+
+ if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
+ return false;
+ /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
+ if (nelt < 4)
+ return false;
+
+ odd = d->perm[0];
+ if (odd > 1)
+ return false;
+ for (i = 1; i < nelt; ++i)
+ if (d->perm[i] != i * 2 + odd)
+ return false;
+
+ if (d->testing_p)
+ return true;
+
+ /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
+ t0 = gen_reg_rtx (d->vmode);
+ t1 = gen_reg_rtx (d->vmode);
+ switch (d->vmode)
+ {
+ case V4HImode:
+ emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1));
+ emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1));
+ if (odd)
+ emit_insn (gen_loongson_punpckhhw (d->target, t1, t0));
+ else
+ emit_insn (gen_loongson_punpcklhw (d->target, t1, t0));
+ break;
+
+ case V8QImode:
+ t2 = gen_reg_rtx (d->vmode);
+ t3 = gen_reg_rtx (d->vmode);
+ emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1));
+ emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1));
+ emit_insn (gen_loongson_punpckhbh (t2, t1, t0));
+ emit_insn (gen_loongson_punpcklbh (t3, t1, t0));
+ if (odd)
+ emit_insn (gen_loongson_punpckhbh (d->target, t3, t2));
+ else
+ emit_insn (gen_loongson_punpcklbh (d->target, t3, t2));
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
+ return true;
+}
+
+/* Recognize patterns for the Loongson PSHUFH instruction. */
+
+static bool
+mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d)
+{
+ unsigned i, mask;
+ rtx rmask;
+
+ if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
+ return false;
+ if (d->vmode != V4HImode)
+ return false;
+ if (d->testing_p)
+ return true;
+
+ /* Convert the selector into the packed 8-bit form for pshufh. */
+ /* Recall that loongson is little-endian only. No big-endian
+ adjustment required. */
+ for (i = mask = 0; i < 4; i++)
+ mask |= (d->perm[i] & 3) << (i * 2);
+ rmask = force_reg (SImode, GEN_INT (mask));
+
+ if (d->one_vector_p)
+ emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask));
+ else
+ {
+ rtx t0, t1, x, merge, rmerge[4];
+
+ t0 = gen_reg_rtx (V4HImode);
+ t1 = gen_reg_rtx (V4HImode);
+ emit_insn (gen_loongson_pshufh (t1, d->op1, rmask));
+ emit_insn (gen_loongson_pshufh (t0, d->op0, rmask));
+
+ for (i = 0; i < 4; ++i)
+ rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx);
+ merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge));
+ merge = force_reg (V4HImode, merge);
+
+ x = gen_rtx_AND (V4HImode, merge, t1);
+ emit_insn (gen_rtx_SET (VOIDmode, t1, x));
+
+ x = gen_rtx_NOT (V4HImode, merge);
+ x = gen_rtx_AND (V4HImode, x, t0);
+ emit_insn (gen_rtx_SET (VOIDmode, t0, x));
+
+ x = gen_rtx_IOR (V4HImode, t0, t1);
+ emit_insn (gen_rtx_SET (VOIDmode, d->target, x));
+ }
+
+ return true;
+}
+
+/* Recognize broadcast patterns for the Loongson. */
+
+static bool
+mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
+{
+ unsigned i, elt;
+ rtx t0, t1;
+
+ if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
+ return false;
+ /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
+ if (d->vmode != V8QImode)
+ return false;
+ if (!d->one_vector_p)
+ return false;
+
+ elt = d->perm[0];
+ for (i = 1; i < 8; ++i)
+ if (d->perm[i] != elt)
+ return false;
+
+ if (d->testing_p)
+ return true;
+
+ /* With one interleave we put two of the desired element adjacent. */
+ t0 = gen_reg_rtx (V8QImode);
+ if (elt < 4)
+ emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0));
+ else
+ emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0));
+
+ /* Shuffle that one HImode element into all locations. */
+ elt &= 3;
+ elt *= 0x55;
+ t1 = gen_reg_rtx (V4HImode);
+ emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0),
+ force_reg (SImode, GEN_INT (elt))));
+
+ emit_move_insn (d->target, gen_lowpart (V8QImode, t1));
+ return true;
+}
+
+static bool
+mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
+{
+ unsigned int i, nelt = d->nelt;
+ unsigned char perm2[MAX_VECT_LEN];
+
+ if (d->one_vector_p)
+ {
+ /* Try interleave with alternating operands. */
+ memcpy (perm2, d->perm, sizeof(perm2));
+ for (i = 1; i < nelt; i += 2)
+ perm2[i] += nelt;
+ if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt))
+ return true;
+ }
+ else
+ {
+ if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1,
+ d->perm, nelt))
+ return true;
+
+ /* Try again with swapped operands. */
+ for (i = 0; i < nelt; ++i)
+ perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
+ if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
+ return true;
+ }
+
+ if (mips_expand_vpc_loongson_even_odd (d))
+ return true;
+ if (mips_expand_vpc_loongson_pshufh (d))
+ return true;
+ if (mips_expand_vpc_loongson_bcast (d))
+ return true;
+ return false;
+}
+
+/* Expand a vec_perm_const pattern. */
+
+bool
+mips_expand_vec_perm_const (rtx operands[4])
+{
+ struct expand_vec_perm_d d;
+ int i, nelt, which;
+ unsigned char orig_perm[MAX_VECT_LEN];
+ rtx sel;
+ bool ok;
+
+ d.target = operands[0];
+ d.op0 = operands[1];
+ d.op1 = operands[2];
+ sel = operands[3];
+
+ d.vmode = GET_MODE (d.target);
+ gcc_assert (VECTOR_MODE_P (d.vmode));
+ d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
+ d.testing_p = false;
+
+ for (i = which = 0; i < nelt; ++i)
+ {
+ rtx e = XVECEXP (sel, 0, i);
+ int ei = INTVAL (e) & (2 * nelt - 1);
+ which |= (ei < nelt ? 1 : 2);
+ orig_perm[i] = ei;
+ }
+ memcpy (d.perm, orig_perm, MAX_VECT_LEN);
+
+ switch (which)
+ {
+ default:
+ gcc_unreachable();
+
+ case 3:
+ d.one_vector_p = false;
+ if (!rtx_equal_p (d.op0, d.op1))
+ break;
+ /* FALLTHRU */
+
+ case 2:
+ for (i = 0; i < nelt; ++i)
+ d.perm[i] &= nelt - 1;
+ d.op0 = d.op1;
+ d.one_vector_p = true;
+ break;
+
+ case 1:
+ d.op1 = d.op0;
+ d.one_vector_p = true;
+ break;
+ }
+
+ ok = mips_expand_vec_perm_const_1 (&d);
+
+ /* If we were given a two-vector permutation which just happened to
+ have both input vectors equal, we folded this into a one-vector
+ permutation. There are several loongson patterns that are matched
+ via direct vec_select+vec_concat expansion, but we do not have
+ support in mips_expand_vec_perm_const_1 to guess the adjustment
+ that should be made for a single operand. Just try again with
+ the original permutation. */
+ if (!ok && which == 3)
+ {
+ d.op0 = operands[1];
+ d.op1 = operands[2];
+ d.one_vector_p = false;
+ memcpy (d.perm, orig_perm, MAX_VECT_LEN);
+ ok = mips_expand_vec_perm_const_1 (&d);
+ }
+
+ return ok;
+}
+
+/* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
+
+static bool
+mips_vectorize_vec_perm_const_ok (enum machine_mode vmode,
+ const unsigned char *sel)
+{
+ struct expand_vec_perm_d d;
+ unsigned int i, nelt, which;
+ bool ret;
+
+ d.vmode = vmode;
+ d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
+ d.testing_p = true;
+ memcpy (d.perm, sel, nelt);
+
+ /* Categorize the set of elements in the selector. */
+ for (i = which = 0; i < nelt; ++i)
+ {
+ unsigned char e = d.perm[i];
+ gcc_assert (e < 2 * nelt);
+ which |= (e < nelt ? 1 : 2);
+ }
+
+ /* For all elements from second vector, fold the elements to first. */
+ if (which == 2)
+ for (i = 0; i < nelt; ++i)
+ d.perm[i] -= nelt;
+
+ /* Check whether the mask can be applied to the vector type. */
+ d.one_vector_p = (which != 3);
+
+ d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
+ d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
+ if (!d.one_vector_p)
+ d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
+
+ start_sequence ();
+ ret = mips_expand_vec_perm_const_1 (&d);
+ end_sequence ();
+
+ return ret;
+}
+
+/* Expand an integral vector unpack operation. */
+
+void
+mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
+{
+ enum machine_mode imode = GET_MODE (operands[1]);
+ rtx (*unpack) (rtx, rtx, rtx);
+ rtx (*cmpgt) (rtx, rtx, rtx);
+ rtx tmp, dest, zero;
+
+ switch (imode)
+ {
+ case V8QImode:
+ if (high_p)
+ unpack = gen_loongson_punpckhbh;
+ else
+ unpack = gen_loongson_punpcklbh;
+ cmpgt = gen_loongson_pcmpgtb;
+ break;
+ case V4HImode:
+ if (high_p)
+ unpack = gen_loongson_punpckhhw;
+ else
+ unpack = gen_loongson_punpcklhw;
+ cmpgt = gen_loongson_pcmpgth;
+ break;
+ default:
+ gcc_unreachable ();
+ }
+
+ zero = force_reg (imode, CONST0_RTX (imode));
+ if (unsigned_p)
+ tmp = zero;
+ else
+ {
+ tmp = gen_reg_rtx (imode);
+ emit_insn (cmpgt (tmp, zero, operands[1]));
+ }
+
+ dest = gen_reg_rtx (imode);
+ emit_insn (unpack (dest, operands[1], tmp));
+
+ emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest));
+}
+
+/* A subroutine of mips_expand_vec_init, match constant vector elements. */
+
+static inline bool
+mips_constant_elt_p (rtx x)
+{
+ return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE;
+}
+
+/* A subroutine of mips_expand_vec_init, expand via broadcast. */
+
+static void
+mips_expand_vi_broadcast (enum machine_mode vmode, rtx target, rtx elt)
+{
+ struct expand_vec_perm_d d;
+ rtx t1;
+ bool ok;
+
+ if (elt != const0_rtx)
+ elt = force_reg (GET_MODE_INNER (vmode), elt);
+ if (REG_P (elt))
+ elt = gen_lowpart (DImode, elt);
+
+ t1 = gen_reg_rtx (vmode);
+ switch (vmode)
+ {
+ case V8QImode:
+ emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
+ break;
+ case V4HImode:
+ emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
+ break;
+ default:
+ gcc_unreachable ();
+ }
+
+ memset (&d, 0, sizeof (d));
+ d.target = target;
+ d.op0 = t1;
+ d.op1 = t1;
+ d.vmode = vmode;
+ d.nelt = GET_MODE_NUNITS (vmode);
+ d.one_vector_p = true;
+
+ ok = mips_expand_vec_perm_const_1 (&d);
+ gcc_assert (ok);
+}
+
+/* A subroutine of mips_expand_vec_init, replacing all of the non-constant
+ elements of VALS with zeros, copy the constant vector to TARGET. */
+
+static void
+mips_expand_vi_constant (enum machine_mode vmode, unsigned nelt,
+ rtx target, rtx vals)
+{
+ rtvec vec = shallow_copy_rtvec (XVEC (vals, 0));
+ unsigned i;
+
+ for (i = 0; i < nelt; ++i)
+ {
+ if (!mips_constant_elt_p (RTVEC_ELT (vec, i)))
+ RTVEC_ELT (vec, i) = const0_rtx;
+ }
+
+ emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec));
+}
+
+
+/* A subroutine of mips_expand_vec_init, expand via pinsrh. */
+
+static void
+mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var)
+{
+ mips_expand_vi_constant (V4HImode, 4, target, vals);
+
+ emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var),
+ GEN_INT (one_var)));
+}
+
+/* A subroutine of mips_expand_vec_init, expand anything via memory. */
+
+static void
+mips_expand_vi_general (enum machine_mode vmode, enum machine_mode imode,
+ unsigned nelt, unsigned nvar, rtx target, rtx vals)
+{
+ rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode));
+ unsigned int i, isize = GET_MODE_SIZE (imode);
+
+ if (nvar < nelt)
+ mips_expand_vi_constant (vmode, nelt, mem, vals);
+
+ for (i = 0; i < nelt; ++i)
+ {
+ rtx x = XVECEXP (vals, 0, i);
+ if (!mips_constant_elt_p (x))
+ emit_move_insn (adjust_address (mem, imode, i * isize), x);
+ }
+
+ emit_move_insn (target, mem);
+}
+
+/* Expand a vector initialization. */
+
+void
+mips_expand_vector_init (rtx target, rtx vals)
+{
+ enum machine_mode vmode = GET_MODE (target);
+ enum machine_mode imode = GET_MODE_INNER (vmode);
+ unsigned i, nelt = GET_MODE_NUNITS (vmode);
+ unsigned nvar = 0, one_var = -1u;
+ bool all_same = true;
+ rtx x;
+
+ for (i = 0; i < nelt; ++i)
+ {
+ x = XVECEXP (vals, 0, i);
+ if (!mips_constant_elt_p (x))
+ nvar++, one_var = i;
+ if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
+ all_same = false;
+ }
+
+ /* Load constants from the pool, or whatever's handy. */
+ if (nvar == 0)
+ {
+ emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)));
+ return;
+ }
+
+ /* For two-part initialization, always use CONCAT. */
+ if (nelt == 2)
+ {
+ rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0));
+ rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1));
+ x = gen_rtx_VEC_CONCAT (vmode, op0, op1);
+ emit_insn (gen_rtx_SET (VOIDmode, target, x));
+ return;
+ }
+
+ /* Loongson is the only cpu with vectors with more elements. */
+ gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS);
+
+ /* If all values are identical, broadcast the value. */
+ if (all_same)
+ {
+ mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0));
+ return;
+ }
+
+ /* If we've only got one non-variable V4HImode, use PINSRH. */
+ if (nvar == 1 && vmode == V4HImode)
+ {
+ mips_expand_vi_loongson_one_pinsrh (target, vals, one_var);
+ return;
+ }
+
+ mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals);
+}
+
+/* Expand a vector reduction. */
+
+void
+mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
+{
+ enum machine_mode vmode = GET_MODE (in);
+ unsigned char perm2[2];
+ rtx last, next, fold, x;
+ bool ok;
+
+ last = in;
+ fold = gen_reg_rtx (vmode);
+ switch (vmode)
+ {
+ case V2SFmode:
+ /* Use PUL/PLU to produce { L, H } op { H, L }.
+ By reversing the pair order, rather than a pure interleave high,
+ we avoid erroneous exceptional conditions that we might otherwise
+ produce from the computation of H op H. */
+ perm2[0] = 1;
+ perm2[1] = 2;
+ ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2);
+ gcc_assert (ok);
+ break;
+
+ case V2SImode:
+ /* Use interleave to produce { H, L } op { H, H }. */
+ emit_insn (gen_loongson_punpckhwd (fold, last, last));
+ break;
+
+ case V4HImode:
+ /* Perform the first reduction with interleave,
+ and subsequent reductions with shifts. */
+ emit_insn (gen_loongson_punpckhwd_hi (fold, last, last));
+
+ next = gen_reg_rtx (vmode);
+ emit_insn (gen (next, last, fold));
+ last = next;
+
+ fold = gen_reg_rtx (vmode);
+ x = force_reg (SImode, GEN_INT (16));
+ emit_insn (gen_vec_shr_v4hi (fold, last, x));
+ break;
+
+ case V8QImode:
+ emit_insn (gen_loongson_punpckhwd_qi (fold, last, last));
+
+ next = gen_reg_rtx (vmode);
+ emit_insn (gen (next, last, fold));
+ last = next;
+
+ fold = gen_reg_rtx (vmode);
+ x = force_reg (SImode, GEN_INT (16));
+ emit_insn (gen_vec_shr_v8qi (fold, last, x));
+
+ next = gen_reg_rtx (vmode);
+ emit_insn (gen (next, last, fold));
+ last = next;
+
+ fold = gen_reg_rtx (vmode);
+ x = force_reg (SImode, GEN_INT (8));
+ emit_insn (gen_vec_shr_v8qi (fold, last, x));
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
+
+ emit_insn (gen (target, last, fold));
+}
+
+/* Expand a vector minimum/maximum. */
+
+void
+mips_expand_vec_minmax (rtx target, rtx op0, rtx op1,
+ rtx (*cmp) (rtx, rtx, rtx), bool min_p)
+{
+ enum machine_mode vmode = GET_MODE (target);
+ rtx tc, t0, t1, x;
+
+ tc = gen_reg_rtx (vmode);
+ t0 = gen_reg_rtx (vmode);
+ t1 = gen_reg_rtx (vmode);
+
+ /* op0 > op1 */
+ emit_insn (cmp (tc, op0, op1));
+
+ x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0));
+ emit_insn (gen_rtx_SET (VOIDmode, t0, x));
+
+ x = gen_rtx_NOT (vmode, tc);
+ x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1));
+ emit_insn (gen_rtx_SET (VOIDmode, t1, x));
+
+ x = gen_rtx_IOR (vmode, t0, t1);
+ emit_insn (gen_rtx_SET (VOIDmode, target, x));
+}
+
+/* Implement TARGET_CASE_VALUES_THRESHOLD. */
+
+unsigned int
+mips_case_values_threshold (void)
+{
+ /* In MIPS16 mode using a larger case threshold generates smaller code. */
+ if (TARGET_MIPS16 && optimize_size)
+ return 10;
+ else
+ return default_case_values_threshold ();
+}
+
+/* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
+
+static void
+mips_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
+{
+ if (!TARGET_HARD_FLOAT_ABI)
+ return;
+ tree exceptions_var = create_tmp_var (MIPS_ATYPE_USI, NULL);
+ tree fcsr_orig_var = create_tmp_var (MIPS_ATYPE_USI, NULL);
+ tree fcsr_mod_var = create_tmp_var (MIPS_ATYPE_USI, NULL);
+ tree get_fcsr = mips_builtin_decls[MIPS_GET_FCSR];
+ tree set_fcsr = mips_builtin_decls[MIPS_SET_FCSR];
+ tree get_fcsr_hold_call = build_call_expr (get_fcsr, 0);
+ tree hold_assign_orig = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
+ fcsr_orig_var, get_fcsr_hold_call);
+ tree hold_mod_val = build2 (BIT_AND_EXPR, MIPS_ATYPE_USI, fcsr_orig_var,
+ build_int_cst (MIPS_ATYPE_USI, 0xfffff003));
+ tree hold_assign_mod = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
+ fcsr_mod_var, hold_mod_val);
+ tree set_fcsr_hold_call = build_call_expr (set_fcsr, 1, fcsr_mod_var);
+ tree hold_all = build2 (COMPOUND_EXPR, MIPS_ATYPE_USI,
+ hold_assign_orig, hold_assign_mod);
+ *hold = build2 (COMPOUND_EXPR, void_type_node, hold_all,
+ set_fcsr_hold_call);
+
+ *clear = build_call_expr (set_fcsr, 1, fcsr_mod_var);
+
+ tree get_fcsr_update_call = build_call_expr (get_fcsr, 0);
+ *update = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
+ exceptions_var, get_fcsr_update_call);
+ tree set_fcsr_update_call = build_call_expr (set_fcsr, 1, fcsr_orig_var);
+ *update = build2 (COMPOUND_EXPR, void_type_node, *update,
+ set_fcsr_update_call);
+ tree atomic_feraiseexcept
+ = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
+ tree int_exceptions_var = fold_convert (integer_type_node,
+ exceptions_var);
+ tree atomic_feraiseexcept_call = build_call_expr (atomic_feraiseexcept,
+ 1, int_exceptions_var);
+ *update = build2 (COMPOUND_EXPR, void_type_node, *update,
+ atomic_feraiseexcept_call);
+}
+
+/* Implement TARGET_SPILL_CLASS. */
+
+static reg_class_t
+mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED,
+ enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+ if (TARGET_MIPS16)
+ return SPILL_REGS;
+ return NO_REGS;
+}
+
+/* Implement TARGET_LRA_P. */
+
+static bool
+mips_lra_p (void)
+{
+ return mips_lra_flag;
+}
\f
/* Initialize the GCC target structure. */
#undef TARGET_ASM_ALIGNED_HI_OP
#undef TARGET_OPTION_OVERRIDE
#define TARGET_OPTION_OVERRIDE mips_option_override
-#undef TARGET_OPTION_OPTIMIZATION_TABLE
-#define TARGET_OPTION_OPTIMIZATION_TABLE mips_option_optimization_table
#undef TARGET_LEGITIMIZE_ADDRESS
#define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
mips_small_register_classes_for_mode_p
-#undef TARGET_DEFAULT_TARGET_FLAGS
-#define TARGET_DEFAULT_TARGET_FLAGS \
- (TARGET_DEFAULT \
- | TARGET_CPU_DEFAULT \
- | TARGET_ENDIAN_DEFAULT \
- | TARGET_FP_EXCEPTIONS_DEFAULT \
- | MASK_CHECK_ZERO_DIV \
- | MASK_FUSED_MADD)
-#undef TARGET_HANDLE_OPTION
-#define TARGET_HANDLE_OPTION mips_handle_option
-
#undef TARGET_FUNCTION_OK_FOR_SIBCALL
#define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
#define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
#undef TARGET_MERGE_DECL_ATTRIBUTES
#define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
+#undef TARGET_CAN_INLINE_P
+#define TARGET_CAN_INLINE_P mips_can_inline_p
#undef TARGET_SET_CURRENT_FUNCTION
#define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
#define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
#undef TARGET_REGISTER_MOVE_COST
#define TARGET_REGISTER_MOVE_COST mips_register_move_cost
+#undef TARGET_REGISTER_PRIORITY
+#define TARGET_REGISTER_PRIORITY mips_register_priority
#undef TARGET_MEMORY_MOVE_COST
#define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
#undef TARGET_RTX_COSTS
#undef TARGET_MACHINE_DEPENDENT_REORG
#define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
+#undef TARGET_PREFERRED_RELOAD_CLASS
+#define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
+
+#undef TARGET_EXPAND_TO_RTL_HOOK
+#define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
#undef TARGET_ASM_FILE_START
#define TARGET_ASM_FILE_START mips_file_start
#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
+#undef TARGET_ASM_CODE_END
+#define TARGET_ASM_CODE_END mips_code_end
#undef TARGET_INIT_LIBFUNCS
#define TARGET_INIT_LIBFUNCS mips_init_libfuncs
#undef TARGET_PROMOTE_PROTOTYPES
#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
+#undef TARGET_FUNCTION_VALUE
+#define TARGET_FUNCTION_VALUE mips_function_value
+#undef TARGET_LIBCALL_VALUE
+#define TARGET_LIBCALL_VALUE mips_libcall_value
+#undef TARGET_FUNCTION_VALUE_REGNO_P
+#define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
#undef TARGET_RETURN_IN_MEMORY
#define TARGET_RETURN_IN_MEMORY mips_return_in_memory
#undef TARGET_RETURN_IN_MSB
#undef TARGET_CANNOT_FORCE_CONST_MEM
#define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
+#undef TARGET_LEGITIMATE_CONSTANT_P
+#define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
+
#undef TARGET_ENCODE_SECTION_INFO
#define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
#undef TARGET_DWARF_REGISTER_SPAN
#define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
-#undef TARGET_IRA_COVER_CLASSES
-#define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes
-
#undef TARGET_ASM_FINAL_POSTSCAN_INSN
#define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
#undef TARGET_SHIFT_TRUNCATION_MASK
#define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
+#undef TARGET_PREPARE_PCH_SAVE
+#define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
+
+#undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
+#define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
+
+#undef TARGET_CASE_VALUES_THRESHOLD
+#define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
+
+#undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
+#define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv
+
+#undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
+#define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
+
+#undef TARGET_SPILL_CLASS
+#define TARGET_SPILL_CLASS mips_spill_class
+#undef TARGET_LRA_P
+#define TARGET_LRA_P mips_lra_p
+
struct gcc_target targetm = TARGET_INITIALIZER;
\f
#include "gt-mips.h"
projects / platform / upstream / gcc.git / blobdiff