Imported Upstream version 4.8.1

[platform/upstream/gcc48.git] / gcc / config / mips / 4600.md

diff --git a/gcc/config/mips/4600.md b/gcc/config/mips/4600.md
index c645cbc..675da69 100644 (file)
--- a/gcc/config/mips/4600.md
+++ b/gcc/config/mips/4600.md
@@ -1,5 +1,5 @@
-;; R4600 and R4650 pipeline description.
-;;   Copyright (C) 2004, 2005, 2007 Free Software Foundation, Inc.
+;; R4600, R4650, and R4700 pipeline description.
+;;   Copyright (C) 2004-2013 Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
 
@@ -21,19 +21,35 @@
 ;; This file overrides parts of generic.md.  It is derived from the
 ;; old define_function_unit description.
 ;;
-;; We handle the R4600 and R4650 in much the same way.  The only difference
-;; is in the integer multiplication and division costs.
+;; We handle the R4600, R4650, and R4700 in much the same way.  The only
+;; differences between R4600 and R4650 are the integer multiplication and
+;; division costs. The only differences between R4600 and R4700 are the
+;; integer and floating-point multiplication costs.
 
-(define_insn_reservation "r4600_imul" 10
+(define_insn_reservation "r4600_imul_si" 10
   (and (eq_attr "cpu" "r4600")
-       (eq_attr "type" "imul,imul3,imadd"))
+       (eq_attr "type" "imul,imul3,imadd")
+       (eq_attr "mode" "SI"))
   "imuldiv*10")
 
-(define_insn_reservation "r4600_idiv" 42
+(define_insn_reservation "r4600_imul_di" 12
   (and (eq_attr "cpu" "r4600")
-       (eq_attr "type" "idiv"))
+       (eq_attr "type" "imul,imul3,imadd")
+       (eq_attr "mode" "DI"))
+  "imuldiv*12")
+
+(define_insn_reservation "r4600_idiv_si" 42
+  (and (eq_attr "cpu" "r4600,r4700")
+       (eq_attr "type" "idiv")
+       (eq_attr "mode" "SI"))
   "imuldiv*42")
 
+(define_insn_reservation "r4600_idiv_di" 74
+  (and (eq_attr "cpu" "r4600,r4700")
+       (eq_attr "type" "idiv")
+       (eq_attr "mode" "DI"))
+  "imuldiv*74")
+
 
 (define_insn_reservation "r4650_imul" 4
   (and (eq_attr "cpu" "r4650")
@@ -46,13 +62,26 @@
   "imuldiv*36")
 
 
+(define_insn_reservation "r4700_imul_si" 8
+  (and (eq_attr "cpu" "r4700")
+       (eq_attr "type" "imul,imul3,imadd")
+       (eq_attr "mode" "SI"))
+  "imuldiv*8")
+
+(define_insn_reservation "r4700_imul_di" 10
+  (and (eq_attr "cpu" "r4700")
+       (eq_attr "type" "imul,imul3,imadd")
+       (eq_attr "mode" "DI"))
+  "imuldiv*10")
+
+
 (define_insn_reservation "r4600_load" 2
-  (and (eq_attr "cpu" "r4600,r4650")
+  (and (eq_attr "cpu" "r4600,r4650,r4700")
        (eq_attr "type" "load,fpload,fpidxload"))
   "alu")
 
 (define_insn_reservation "r4600_fmove" 1
-  (and (eq_attr "cpu" "r4600,r4650")
+  (and (eq_attr "cpu" "r4600,r4650,r4700")
        (eq_attr "type" "fabs,fneg,fmove"))
   "alu")
 
@@ -62,26 +91,40 @@
            (eq_attr "mode" "SF")))
   "alu")
 
+
+(define_insn_reservation "r4700_fmul_single" 4
+  (and (eq_attr "cpu" "r4700")
+       (and (eq_attr "type" "fmul,fmadd")
+           (eq_attr "mode" "SF")))
+  "alu")
+
+(define_insn_reservation "r4700_fmul_double" 5
+  (and (eq_attr "cpu" "r4700")
+       (and (eq_attr "type" "fmul,fmadd")
+           (eq_attr "mode" "DF")))
+  "alu")
+
+
 (define_insn_reservation "r4600_fdiv_single" 32
-  (and (eq_attr "cpu" "r4600,r4650")
+  (and (eq_attr "cpu" "r4600,r4650,r4700")
        (and (eq_attr "type" "fdiv,frdiv")
            (eq_attr "mode" "SF")))
   "alu")
 
 (define_insn_reservation "r4600_fdiv_double" 61
-  (and (eq_attr "cpu" "r4600,r4650")
+  (and (eq_attr "cpu" "r4600,r4650,r4700")
        (and (eq_attr "type" "fdiv,frdiv")
            (eq_attr "mode" "DF")))
   "alu")
 
 (define_insn_reservation "r4600_fsqrt_single" 31
-  (and (eq_attr "cpu" "r4600,r4650")
+  (and (eq_attr "cpu" "r4600,r4650,r4700")
        (and (eq_attr "type" "fsqrt,frsqrt")
            (eq_attr "mode" "SF")))
   "alu")
 
 (define_insn_reservation "r4600_fsqrt_double" 60
-  (and (eq_attr "cpu" "r4600,r4650")
+  (and (eq_attr "cpu" "r4600,r4650,r4700")
        (and (eq_attr "type" "fsqrt,frsqrt")
            (eq_attr "mode" "DF")))
   "alu")