;; GCC machine description for SSE instructions
-;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
-;; Free Software Foundation, Inc.
+;; Copyright (C) 2005-2013 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
UNSPEC_VCVTPS2PH
;; For AVX2 support
- UNSPEC_VPERMSI
- UNSPEC_VPERMDF
- UNSPEC_VPERMSF
+ UNSPEC_VPERMVAR
UNSPEC_VPERMTI
UNSPEC_GATHER
UNSPEC_VSIBADDR
(define_mode_attr ssse3_avx2
[(V16QI "ssse3") (V32QI "avx2")
- (V8HI "ssse3") (V16HI "avx2")
+ (V4HI "ssse3") (V8HI "ssse3") (V16HI "avx2")
(V4SI "ssse3") (V8SI "avx2")
(V2DI "ssse3") (V4DI "avx2")
(TI "ssse3") (V2TI "avx2")])
(V2DI "vec") (V4DI "avx2")])
(define_mode_attr ssedoublemode
- [(V16HI "V16SI") (V8HI "V8SI")])
+ [(V16HI "V16SI") (V8HI "V8SI") (V4HI "V4SI")
+ (V32QI "V32HI") (V16QI "V16HI")])
(define_mode_attr ssebytemode
[(V4DI "V32QI") (V2DI "V16QI")])
(V8SF "V4SF") (V4DF "V2DF")
(V4SF "V2SF")])
+;; Mapping of vector modes ti packed single mode of the same size
+(define_mode_attr ssePSmode
+ [(V32QI "V8SF") (V16QI "V4SF")
+ (V16HI "V8SF") (V8HI "V4SF")
+ (V8SI "V8SF") (V4SI "V4SF")
+ (V4DI "V8SF") (V2DI "V4SF")
+ (V2TI "V8SF") (V1TI "V4SF")
+ (V8SF "V8SF") (V4SF "V4SF")
+ (V4DF "V8SF") (V2DF "V4SF")])
+
;; Mapping of vector modes back to the scalar modes
(define_mode_attr ssescalarmode
[(V32QI "QI") (V16HI "HI") (V8SI "SI") (V4DI "DI")
;; This is essential for maintaining stable calling conventions.
(define_expand "mov<mode>"
- [(set (match_operand:V16 0 "nonimmediate_operand" "")
- (match_operand:V16 1 "nonimmediate_operand" ""))]
+ [(set (match_operand:V16 0 "nonimmediate_operand")
+ (match_operand:V16 1 "nonimmediate_operand"))]
"TARGET_SSE"
{
ix86_expand_vector_move (<MODE>mode, operands);
})
(define_insn "*mov<mode>_internal"
- [(set (match_operand:V16 0 "nonimmediate_operand" "=x,x ,m")
+ [(set (match_operand:V16 0 "nonimmediate_operand" "=x,x ,m")
(match_operand:V16 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))]
"TARGET_SSE
&& (register_operand (operands[0], <MODE>mode)
&& (misaligned_operand (operands[0], <MODE>mode)
|| misaligned_operand (operands[1], <MODE>mode)))
return "vmovupd\t{%1, %0|%0, %1}";
- else if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "%vmovaps\t{%1, %0|%0, %1}";
else
return "%vmovapd\t{%1, %0|%0, %1}";
&& (misaligned_operand (operands[0], <MODE>mode)
|| misaligned_operand (operands[1], <MODE>mode)))
return "vmovdqu\t{%1, %0|%0, %1}";
- else if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "%vmovaps\t{%1, %0|%0, %1}";
else
return "%vmovdqa\t{%1, %0|%0, %1}";
[(set_attr "type" "sselog1,ssemov,ssemov")
(set_attr "prefix" "maybe_vex")
(set (attr "mode")
- (cond [(match_test "TARGET_AVX")
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "<ssePSmode>")
+ (and (eq_attr "alternative" "2")
+ (match_test "TARGET_SSE_TYPELESS_STORES"))
+ (const_string "<ssePSmode>")
+ (match_test "TARGET_AVX")
(const_string "<sseinsnmode>")
- (ior (ior (match_test "optimize_function_for_size_p (cfun)")
- (not (match_test "TARGET_SSE2")))
- (and (eq_attr "alternative" "2")
- (match_test "TARGET_SSE_TYPELESS_STORES")))
- (const_string "V4SF")
- (eq (const_string "<MODE>mode") (const_string "V4SFmode"))
+ (ior (not (match_test "TARGET_SSE2"))
+ (match_test "optimize_function_for_size_p (cfun)"))
(const_string "V4SF")
- (eq (const_string "<MODE>mode") (const_string "V2DFmode"))
- (const_string "V2DF")
+ (and (eq_attr "alternative" "0")
+ (match_test "TARGET_SSE_LOAD0_BY_PXOR"))
+ (const_string "TI")
]
- (const_string "TI")))])
+ (const_string "<sseinsnmode>")))])
(define_insn "sse2_movq128"
[(set (match_operand:V2DI 0 "register_operand" "=x")
})
(define_split
- [(set (match_operand:V4SF 0 "register_operand" "")
- (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
+ [(set (match_operand:V4SF 0 "register_operand")
+ (match_operand:V4SF 1 "zero_extended_scalar_load_operand"))]
"TARGET_SSE && reload_completed"
[(set (match_dup 0)
(vec_merge:V4SF
})
(define_split
- [(set (match_operand:V2DF 0 "register_operand" "")
- (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
+ [(set (match_operand:V2DF 0 "register_operand")
+ (match_operand:V2DF 1 "zero_extended_scalar_load_operand"))]
"TARGET_SSE2 && reload_completed"
[(set (match_dup 0) (vec_concat:V2DF (match_dup 1) (match_dup 2)))]
{
})
(define_expand "push<mode>1"
- [(match_operand:V16 0 "register_operand" "")]
+ [(match_operand:V16 0 "register_operand")]
"TARGET_SSE"
{
ix86_expand_push (<MODE>mode, operands[0]);
})
(define_expand "movmisalign<mode>"
- [(set (match_operand:V16 0 "nonimmediate_operand" "")
- (match_operand:V16 1 "nonimmediate_operand" ""))]
+ [(set (match_operand:V16 0 "nonimmediate_operand")
+ (match_operand:V16 1 "nonimmediate_operand"))]
"TARGET_SSE"
{
ix86_expand_vector_move_misalign (<MODE>mode, operands);
[(match_operand:VF 1 "memory_operand" "m")]
UNSPEC_LOADU))]
"TARGET_SSE"
- "%vmovu<ssemodesuffix>\t{%1, %0|%0, %1}"
+{
+ switch (get_attr_mode (insn))
+ {
+ case MODE_V8SF:
+ case MODE_V4SF:
+ return "%vmovups\t{%1, %0|%0, %1}";
+ default:
+ return "%vmovu<ssemodesuffix>\t{%1, %0|%0, %1}";
+ }
+}
[(set_attr "type" "ssemov")
(set_attr "movu" "1")
(set_attr "prefix" "maybe_vex")
- (set_attr "mode" "<MODE>")])
+ (set (attr "mode")
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "<ssePSmode>")
+ (match_test "TARGET_AVX")
+ (const_string "<MODE>")
+ (match_test "optimize_function_for_size_p (cfun)")
+ (const_string "V4SF")
+ ]
+ (const_string "<MODE>")))])
(define_insn "<sse>_storeu<ssemodesuffix><avxsizesuffix>"
[(set (match_operand:VF 0 "memory_operand" "=m")
[(match_operand:VF 1 "register_operand" "x")]
UNSPEC_STOREU))]
"TARGET_SSE"
- "%vmovu<ssemodesuffix>\t{%1, %0|%0, %1}"
+{
+ switch (get_attr_mode (insn))
+ {
+ case MODE_V8SF:
+ case MODE_V4SF:
+ return "%vmovups\t{%1, %0|%0, %1}";
+ default:
+ return "%vmovu<ssemodesuffix>\t{%1, %0|%0, %1}";
+ }
+}
[(set_attr "type" "ssemov")
(set_attr "movu" "1")
(set_attr "prefix" "maybe_vex")
- (set_attr "mode" "<MODE>")])
+ (set (attr "mode")
+ (cond [(ior (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (match_test "TARGET_SSE_TYPELESS_STORES"))
+ (const_string "<ssePSmode>")
+ (match_test "TARGET_AVX")
+ (const_string "<MODE>")
+ (match_test "optimize_function_for_size_p (cfun)")
+ (const_string "V4SF")
+ ]
+ (const_string "<MODE>")))])
(define_insn "<sse2>_loaddqu<avxsizesuffix>"
[(set (match_operand:VI1 0 "register_operand" "=x")
(unspec:VI1 [(match_operand:VI1 1 "memory_operand" "m")]
UNSPEC_LOADU))]
"TARGET_SSE2"
- "%vmovdqu\t{%1, %0|%0, %1}"
+{
+ switch (get_attr_mode (insn))
+ {
+ case MODE_V8SF:
+ case MODE_V4SF:
+ return "%vmovups\t{%1, %0|%0, %1}";
+ default:
+ return "%vmovdqu\t{%1, %0|%0, %1}";
+ }
+}
[(set_attr "type" "ssemov")
(set_attr "movu" "1")
(set (attr "prefix_data16")
(const_string "*")
(const_string "1")))
(set_attr "prefix" "maybe_vex")
- (set_attr "mode" "<sseinsnmode>")])
+ (set (attr "mode")
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "<ssePSmode>")
+ (match_test "TARGET_AVX")
+ (const_string "<sseinsnmode>")
+ (match_test "optimize_function_for_size_p (cfun)")
+ (const_string "V4SF")
+ ]
+ (const_string "<sseinsnmode>")))])
(define_insn "<sse2>_storedqu<avxsizesuffix>"
[(set (match_operand:VI1 0 "memory_operand" "=m")
(unspec:VI1 [(match_operand:VI1 1 "register_operand" "x")]
UNSPEC_STOREU))]
"TARGET_SSE2"
- "%vmovdqu\t{%1, %0|%0, %1}"
+{
+ switch (get_attr_mode (insn))
+ {
+ case MODE_V8SF:
+ case MODE_V4SF:
+ return "%vmovups\t{%1, %0|%0, %1}";
+ default:
+ return "%vmovdqu\t{%1, %0|%0, %1}";
+ }
+}
[(set_attr "type" "ssemov")
(set_attr "movu" "1")
(set (attr "prefix_data16")
(const_string "*")
(const_string "1")))
(set_attr "prefix" "maybe_vex")
- (set_attr "mode" "<sseinsnmode>")])
+ (set (attr "mode")
+ (cond [(ior (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (match_test "TARGET_SSE_TYPELESS_STORES"))
+ (const_string "<ssePSmode>")
+ (match_test "TARGET_AVX")
+ (const_string "<sseinsnmode>")
+ (match_test "optimize_function_for_size_p (cfun)")
+ (const_string "V4SF")
+ ]
+ (const_string "<sseinsnmode>")))])
(define_insn "<sse3>_lddqu<avxsizesuffix>"
[(set (match_operand:VI1 0 "register_operand" "=x")
(V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")])
(define_expand "storent<mode>"
- [(set (match_operand:STORENT_MODE 0 "memory_operand" "")
+ [(set (match_operand:STORENT_MODE 0 "memory_operand")
(unspec:STORENT_MODE
- [(match_operand:STORENT_MODE 1 "register_operand" "")]
+ [(match_operand:STORENT_MODE 1 "register_operand")]
UNSPEC_MOVNT))]
"TARGET_SSE")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "<code><mode>2"
- [(set (match_operand:VF 0 "register_operand" "")
+ [(set (match_operand:VF 0 "register_operand")
(absneg:VF
- (match_operand:VF 1 "register_operand" "")))]
+ (match_operand:VF 1 "register_operand")))]
"TARGET_SSE"
"ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
[(set_attr "isa" "noavx,noavx,avx,avx")])
(define_expand "<plusminus_insn><mode>3"
- [(set (match_operand:VF 0 "register_operand" "")
+ [(set (match_operand:VF 0 "register_operand")
(plusminus:VF
- (match_operand:VF 1 "nonimmediate_operand" "")
- (match_operand:VF 2 "nonimmediate_operand" "")))]
+ (match_operand:VF 1 "nonimmediate_operand")
+ (match_operand:VF 2 "nonimmediate_operand")))]
"TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(set_attr "mode" "<ssescalarmode>")])
(define_expand "mul<mode>3"
- [(set (match_operand:VF 0 "register_operand" "")
+ [(set (match_operand:VF 0 "register_operand")
(mult:VF
- (match_operand:VF 1 "nonimmediate_operand" "")
- (match_operand:VF 2 "nonimmediate_operand" "")))]
+ (match_operand:VF 1 "nonimmediate_operand")
+ (match_operand:VF 2 "nonimmediate_operand")))]
"TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
[(set_attr "isa" "noavx,avx")
(set_attr "type" "ssemul")
(set_attr "prefix" "orig,vex")
+ (set_attr "btver2_decode" "direct,double")
(set_attr "mode" "<MODE>")])
(define_insn "<sse>_vmmul<mode>3"
(set_attr "mode" "<ssescalarmode>")])
(define_expand "div<mode>3"
- [(set (match_operand:VF2 0 "register_operand" "")
- (div:VF2 (match_operand:VF2 1 "register_operand" "")
- (match_operand:VF2 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:VF2 0 "register_operand")
+ (div:VF2 (match_operand:VF2 1 "register_operand")
+ (match_operand:VF2 2 "nonimmediate_operand")))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (DIV, <MODE>mode, operands);")
(define_expand "div<mode>3"
- [(set (match_operand:VF1 0 "register_operand" "")
- (div:VF1 (match_operand:VF1 1 "register_operand" "")
- (match_operand:VF1 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:VF1 0 "register_operand")
+ (div:VF1 (match_operand:VF1 1 "register_operand")
+ (match_operand:VF1 2 "nonimmediate_operand")))]
"TARGET_SSE"
{
ix86_fixup_binary_operands_no_copy (DIV, <MODE>mode, operands);
[(set_attr "isa" "noavx,avx")
(set_attr "type" "ssediv")
(set_attr "prefix" "orig,vex")
+ (set_attr "btver2_decode" "direct,double")
(set_attr "mode" "<ssescalarmode>")])
(define_insn "<sse>_rcp<mode>2"
"%vrcpps\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "atom_sse_attr" "rcp")
+ (set_attr "btver2_sse_attr" "rcp")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "<MODE>")])
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sse")
(set_attr "atom_sse_attr" "rcp")
+ (set_attr "btver2_sse_attr" "rcp")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "SF")])
(define_expand "sqrt<mode>2"
- [(set (match_operand:VF2 0 "register_operand" "")
- (sqrt:VF2 (match_operand:VF2 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:VF2 0 "register_operand")
+ (sqrt:VF2 (match_operand:VF2 1 "nonimmediate_operand")))]
"TARGET_SSE2")
(define_expand "sqrt<mode>2"
- [(set (match_operand:VF1 0 "register_operand" "")
- (sqrt:VF1 (match_operand:VF1 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:VF1 0 "register_operand")
+ (sqrt:VF1 (match_operand:VF1 1 "nonimmediate_operand")))]
"TARGET_SSE"
{
if (TARGET_SSE_MATH
"%vsqrt<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "atom_sse_attr" "sqrt")
+ (set_attr "btver2_sse_attr" "sqrt")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "<MODE>")])
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sse")
(set_attr "atom_sse_attr" "sqrt")
+ (set_attr "btver2_sse_attr" "sqrt")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "<ssescalarmode>")])
(define_expand "rsqrt<mode>2"
- [(set (match_operand:VF1 0 "register_operand" "")
+ [(set (match_operand:VF1 0 "register_operand")
(unspec:VF1
- [(match_operand:VF1 1 "nonimmediate_operand" "")] UNSPEC_RSQRT))]
+ [(match_operand:VF1 1 "nonimmediate_operand")] UNSPEC_RSQRT))]
"TARGET_SSE_MATH"
{
ix86_emit_swsqrtsf (operands[0], operands[1], <MODE>mode, true);
;; applied to NaNs. Hopefully the optimizers won't get too smart on us.
(define_expand "<code><mode>3"
- [(set (match_operand:VF 0 "register_operand" "")
+ [(set (match_operand:VF 0 "register_operand")
(smaxmin:VF
- (match_operand:VF 1 "nonimmediate_operand" "")
- (match_operand:VF 2 "nonimmediate_operand" "")))]
+ (match_operand:VF 1 "nonimmediate_operand")
+ (match_operand:VF 2 "nonimmediate_operand")))]
"TARGET_SSE"
{
if (!flag_finite_math_only)
v<maxmin_float><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseadd")
+ (set_attr "btver2_sse_attr" "maxmin")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "<MODE>")])
v<maxmin_float><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseadd")
+ (set_attr "btver2_sse_attr" "maxmin")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "<MODE>")])
v<maxmin_float><ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sse")
+ (set_attr "btver2_sse_attr" "maxmin")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "<ssescalarmode>")])
(set_attr "prefix" "vex")
(set_attr "mode" "V4DF")])
-(define_insn "sse3_h<plusminus_insn>v2df3"
+(define_expand "sse3_haddv2df3"
+ [(set (match_operand:V2DF 0 "register_operand")
+ (vec_concat:V2DF
+ (plus:DF
+ (vec_select:DF
+ (match_operand:V2DF 1 "register_operand")
+ (parallel [(const_int 0)]))
+ (vec_select:DF (match_dup 1) (parallel [(const_int 1)])))
+ (plus:DF
+ (vec_select:DF
+ (match_operand:V2DF 2 "nonimmediate_operand")
+ (parallel [(const_int 0)]))
+ (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))]
+ "TARGET_SSE3")
+
+(define_insn "*sse3_haddv2df3"
+ [(set (match_operand:V2DF 0 "register_operand" "=x,x")
+ (vec_concat:V2DF
+ (plus:DF
+ (vec_select:DF
+ (match_operand:V2DF 1 "register_operand" "0,x")
+ (parallel [(match_operand:SI 3 "const_0_to_1_operand")]))
+ (vec_select:DF
+ (match_dup 1)
+ (parallel [(match_operand:SI 4 "const_0_to_1_operand")])))
+ (plus:DF
+ (vec_select:DF
+ (match_operand:V2DF 2 "nonimmediate_operand" "xm,xm")
+ (parallel [(match_operand:SI 5 "const_0_to_1_operand")]))
+ (vec_select:DF
+ (match_dup 2)
+ (parallel [(match_operand:SI 6 "const_0_to_1_operand")])))))]
+ "TARGET_SSE3
+ && INTVAL (operands[3]) != INTVAL (operands[4])
+ && INTVAL (operands[5]) != INTVAL (operands[6])"
+ "@
+ haddpd\t{%2, %0|%0, %2}
+ vhaddpd\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseadd")
+ (set_attr "prefix" "orig,vex")
+ (set_attr "mode" "V2DF")])
+
+(define_insn "sse3_hsubv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x,x")
(vec_concat:V2DF
- (plusminus:DF
+ (minus:DF
(vec_select:DF
(match_operand:V2DF 1 "register_operand" "0,x")
(parallel [(const_int 0)]))
(vec_select:DF (match_dup 1) (parallel [(const_int 1)])))
- (plusminus:DF
+ (minus:DF
(vec_select:DF
(match_operand:V2DF 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0)]))
(vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))]
"TARGET_SSE3"
"@
- h<plusminus_mnemonic>pd\t{%2, %0|%0, %2}
- vh<plusminus_mnemonic>pd\t{%2, %1, %0|%0, %1, %2}"
+ hsubpd\t{%2, %0|%0, %2}
+ vhsubpd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseadd")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "V2DF")])
+(define_insn "*sse3_haddv2df3_low"
+ [(set (match_operand:DF 0 "register_operand" "=x,x")
+ (plus:DF
+ (vec_select:DF
+ (match_operand:V2DF 1 "register_operand" "0,x")
+ (parallel [(match_operand:SI 2 "const_0_to_1_operand")]))
+ (vec_select:DF
+ (match_dup 1)
+ (parallel [(match_operand:SI 3 "const_0_to_1_operand")]))))]
+ "TARGET_SSE3
+ && INTVAL (operands[2]) != INTVAL (operands[3])"
+ "@
+ haddpd\t{%0, %0|%0, %0}
+ vhaddpd\t{%1, %1, %0|%0, %1, %1}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseadd1")
+ (set_attr "prefix" "orig,vex")
+ (set_attr "mode" "V2DF")])
+
+(define_insn "*sse3_hsubv2df3_low"
+ [(set (match_operand:DF 0 "register_operand" "=x,x")
+ (minus:DF
+ (vec_select:DF
+ (match_operand:V2DF 1 "register_operand" "0,x")
+ (parallel [(const_int 0)]))
+ (vec_select:DF
+ (match_dup 1)
+ (parallel [(const_int 1)]))))]
+ "TARGET_SSE3"
+ "@
+ hsubpd\t{%0, %0|%0, %0}
+ vhsubpd\t{%1, %1, %0|%0, %1, %1}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseadd1")
+ (set_attr "prefix" "orig,vex")
+ (set_attr "mode" "V2DF")])
+
(define_insn "avx_h<plusminus_insn>v8sf3"
[(set (match_operand:V8SF 0 "register_operand" "=x")
(vec_concat:V8SF
(set_attr "mode" "V4SF")])
(define_expand "reduc_splus_v4df"
- [(match_operand:V4DF 0 "register_operand" "")
- (match_operand:V4DF 1 "register_operand" "")]
+ [(match_operand:V4DF 0 "register_operand")
+ (match_operand:V4DF 1 "register_operand")]
"TARGET_AVX"
{
rtx tmp = gen_reg_rtx (V4DFmode);
})
(define_expand "reduc_splus_v2df"
- [(match_operand:V2DF 0 "register_operand" "")
- (match_operand:V2DF 1 "register_operand" "")]
+ [(match_operand:V2DF 0 "register_operand")
+ (match_operand:V2DF 1 "register_operand")]
"TARGET_SSE3"
{
emit_insn (gen_sse3_haddv2df3 (operands[0], operands[1], operands[1]));
})
(define_expand "reduc_splus_v8sf"
- [(match_operand:V8SF 0 "register_operand" "")
- (match_operand:V8SF 1 "register_operand" "")]
+ [(match_operand:V8SF 0 "register_operand")
+ (match_operand:V8SF 1 "register_operand")]
"TARGET_AVX"
{
rtx tmp = gen_reg_rtx (V8SFmode);
})
(define_expand "reduc_splus_v4sf"
- [(match_operand:V4SF 0 "register_operand" "")
- (match_operand:V4SF 1 "register_operand" "")]
+ [(match_operand:V4SF 0 "register_operand")
+ (match_operand:V4SF 1 "register_operand")]
"TARGET_SSE"
{
if (TARGET_SSE3)
(define_expand "reduc_<code>_<mode>"
[(smaxmin:REDUC_SMINMAX_MODE
- (match_operand:REDUC_SMINMAX_MODE 0 "register_operand" "")
- (match_operand:REDUC_SMINMAX_MODE 1 "register_operand" ""))]
+ (match_operand:REDUC_SMINMAX_MODE 0 "register_operand")
+ (match_operand:REDUC_SMINMAX_MODE 1 "register_operand"))]
""
{
ix86_expand_reduc (gen_<code><mode>3, operands[0], operands[1]);
(define_expand "reduc_<code>_<mode>"
[(umaxmin:VI_256
- (match_operand:VI_256 0 "register_operand" "")
- (match_operand:VI_256 1 "register_operand" ""))]
+ (match_operand:VI_256 0 "register_operand")
+ (match_operand:VI_256 1 "register_operand"))]
"TARGET_AVX2"
{
ix86_expand_reduc (gen_<code><mode>3, operands[0], operands[1]);
(define_expand "reduc_umin_v8hi"
[(umin:V8HI
- (match_operand:V8HI 0 "register_operand" "")
- (match_operand:V8HI 1 "register_operand" ""))]
+ (match_operand:V8HI 0 "register_operand")
+ (match_operand:V8HI 1 "register_operand"))]
"TARGET_SSE4_1"
{
ix86_expand_reduc (gen_uminv8hi3, operands[0], operands[1]);
(set_attr "mode" "<MODE>")])
(define_expand "vcond<V_256:mode><VF_256:mode>"
- [(set (match_operand:V_256 0 "register_operand" "")
+ [(set (match_operand:V_256 0 "register_operand")
(if_then_else:V_256
(match_operator 3 ""
- [(match_operand:VF_256 4 "nonimmediate_operand" "")
- (match_operand:VF_256 5 "nonimmediate_operand" "")])
- (match_operand:V_256 1 "general_operand" "")
- (match_operand:V_256 2 "general_operand" "")))]
+ [(match_operand:VF_256 4 "nonimmediate_operand")
+ (match_operand:VF_256 5 "nonimmediate_operand")])
+ (match_operand:V_256 1 "general_operand")
+ (match_operand:V_256 2 "general_operand")))]
"TARGET_AVX
&& (GET_MODE_NUNITS (<V_256:MODE>mode)
== GET_MODE_NUNITS (<VF_256:MODE>mode))"
})
(define_expand "vcond<V_128:mode><VF_128:mode>"
- [(set (match_operand:V_128 0 "register_operand" "")
+ [(set (match_operand:V_128 0 "register_operand")
(if_then_else:V_128
(match_operator 3 ""
- [(match_operand:VF_128 4 "nonimmediate_operand" "")
- (match_operand:VF_128 5 "nonimmediate_operand" "")])
- (match_operand:V_128 1 "general_operand" "")
- (match_operand:V_128 2 "general_operand" "")))]
+ [(match_operand:VF_128 4 "nonimmediate_operand")
+ (match_operand:VF_128 5 "nonimmediate_operand")])
+ (match_operand:V_128 1 "general_operand")
+ (match_operand:V_128 2 "general_operand")))]
"TARGET_SSE
&& (GET_MODE_NUNITS (<V_128:MODE>mode)
== GET_MODE_NUNITS (<VF_128:MODE>mode))"
"TARGET_SSE"
{
static char buf[32];
- const char *insn;
- const char *suffix
- = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : "<ssemodesuffix>";
+ const char *ops;
+ const char *suffix;
+
+ switch (get_attr_mode (insn))
+ {
+ case MODE_V8SF:
+ case MODE_V4SF:
+ suffix = "ps";
+ break;
+ default:
+ suffix = "<ssemodesuffix>";
+ }
switch (which_alternative)
{
case 0:
- insn = "andn%s\t{%%2, %%0|%%0, %%2}";
+ ops = "andn%s\t{%%2, %%0|%%0, %%2}";
break;
case 1:
- insn = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
+ ops = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
break;
default:
gcc_unreachable ();
}
- snprintf (buf, sizeof (buf), insn, suffix);
+ snprintf (buf, sizeof (buf), ops, suffix);
return buf;
}
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog")
(set_attr "prefix" "orig,vex")
- (set_attr "mode" "<MODE>")])
+ (set (attr "mode")
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "<ssePSmode>")
+ (match_test "TARGET_AVX")
+ (const_string "<MODE>")
+ (match_test "optimize_function_for_size_p (cfun)")
+ (const_string "V4SF")
+ ]
+ (const_string "<MODE>")))])
(define_expand "<code><mode>3"
- [(set (match_operand:VF 0 "register_operand" "")
+ [(set (match_operand:VF 0 "register_operand")
(any_logic:VF
- (match_operand:VF 1 "nonimmediate_operand" "")
- (match_operand:VF 2 "nonimmediate_operand" "")))]
+ (match_operand:VF 1 "nonimmediate_operand")
+ (match_operand:VF 2 "nonimmediate_operand")))]
"TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
"TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
{
static char buf[32];
- const char *insn;
- const char *suffix
- = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : "<ssemodesuffix>";
+ const char *ops;
+ const char *suffix;
+
+ switch (get_attr_mode (insn))
+ {
+ case MODE_V8SF:
+ case MODE_V4SF:
+ suffix = "ps";
+ break;
+ default:
+ suffix = "<ssemodesuffix>";
+ }
switch (which_alternative)
{
case 0:
- insn = "<logic>%s\t{%%2, %%0|%%0, %%2}";
+ ops = "<logic>%s\t{%%2, %%0|%%0, %%2}";
break;
case 1:
- insn = "v<logic>%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
+ ops = "v<logic>%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
break;
default:
gcc_unreachable ();
}
- snprintf (buf, sizeof (buf), insn, suffix);
+ snprintf (buf, sizeof (buf), ops, suffix);
return buf;
}
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog")
(set_attr "prefix" "orig,vex")
- (set_attr "mode" "<MODE>")])
+ (set (attr "mode")
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "<ssePSmode>")
+ (match_test "TARGET_AVX")
+ (const_string "<MODE>")
+ (match_test "optimize_function_for_size_p (cfun)")
+ (const_string "V4SF")
+ ]
+ (const_string "<MODE>")))])
(define_expand "copysign<mode>3"
[(set (match_dup 4)
(and:VF
(not:VF (match_dup 3))
- (match_operand:VF 1 "nonimmediate_operand" "")))
+ (match_operand:VF 1 "nonimmediate_operand")))
(set (match_dup 5)
(and:VF (match_dup 3)
- (match_operand:VF 2 "nonimmediate_operand" "")))
- (set (match_operand:VF 0 "register_operand" "")
+ (match_operand:VF 2 "nonimmediate_operand")))
+ (set (match_operand:VF 0 "register_operand")
(ior:VF (match_dup 4) (match_dup 5)))]
"TARGET_SSE"
{
"SSE_FLOAT_MODE_P (<MODE>mode)"
{
static char buf[32];
- const char *insn;
+ const char *ops;
const char *suffix
- = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : "<ssevecmodesuffix>";
+ = (get_attr_mode (insn) == MODE_V4SF) ? "ps" : "<ssevecmodesuffix>";
+
+ switch (which_alternative)
+ {
+ case 0:
+ ops = "andn%s\t{%%2, %%0|%%0, %%2}";
+ break;
+ case 1:
+ ops = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
+ break;
+ default:
+ gcc_unreachable ();
+ }
+
+ snprintf (buf, sizeof (buf), ops, suffix);
+ return buf;
+}
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix" "orig,vex")
+ (set (attr "mode")
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "V4SF")
+ (match_test "TARGET_AVX")
+ (const_string "<ssevecmode>")
+ (match_test "optimize_function_for_size_p (cfun)")
+ (const_string "V4SF")
+ ]
+ (const_string "<ssevecmode>")))])
+
+(define_insn "*andnottf3"
+ [(set (match_operand:TF 0 "register_operand" "=x,x")
+ (and:TF
+ (not:TF (match_operand:TF 1 "register_operand" "0,x"))
+ (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE"
+{
+ static char buf[32];
+ const char *ops;
+ const char *tmp
+ = (get_attr_mode (insn) == MODE_V4SF) ? "andnps" : "pandn";
switch (which_alternative)
{
case 0:
- insn = "andn%s\t{%%2, %%0|%%0, %%2}";
+ ops = "%s\t{%%2, %%0|%%0, %%2}";
break;
case 1:
- insn = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
+ ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
break;
default:
gcc_unreachable ();
}
- snprintf (buf, sizeof (buf), insn, suffix);
+ snprintf (buf, sizeof (buf), ops, tmp);
return buf;
}
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog")
+ (set (attr "prefix_data16")
+ (if_then_else
+ (and (eq_attr "alternative" "0")
+ (eq_attr "mode" "TI"))
+ (const_string "1")
+ (const_string "*")))
(set_attr "prefix" "orig,vex")
- (set_attr "mode" "<ssevecmode>")])
+ (set (attr "mode")
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "V4SF")
+ (match_test "TARGET_AVX")
+ (const_string "TI")
+ (ior (not (match_test "TARGET_SSE2"))
+ (match_test "optimize_function_for_size_p (cfun)"))
+ (const_string "V4SF")
+ ]
+ (const_string "TI")))])
(define_insn "*<code><mode>3"
[(set (match_operand:MODEF 0 "register_operand" "=x,x")
"SSE_FLOAT_MODE_P (<MODE>mode)"
{
static char buf[32];
- const char *insn;
+ const char *ops;
const char *suffix
- = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : "<ssevecmodesuffix>";
+ = (get_attr_mode (insn) == MODE_V4SF) ? "ps" : "<ssevecmodesuffix>";
+
+ switch (which_alternative)
+ {
+ case 0:
+ ops = "<logic>%s\t{%%2, %%0|%%0, %%2}";
+ break;
+ case 1:
+ ops = "v<logic>%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
+ break;
+ default:
+ gcc_unreachable ();
+ }
+
+ snprintf (buf, sizeof (buf), ops, suffix);
+ return buf;
+}
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix" "orig,vex")
+ (set (attr "mode")
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "V4SF")
+ (match_test "TARGET_AVX")
+ (const_string "<ssevecmode>")
+ (match_test "optimize_function_for_size_p (cfun)")
+ (const_string "V4SF")
+ ]
+ (const_string "<ssevecmode>")))])
+
+(define_expand "<code>tf3"
+ [(set (match_operand:TF 0 "register_operand")
+ (any_logic:TF
+ (match_operand:TF 1 "nonimmediate_operand")
+ (match_operand:TF 2 "nonimmediate_operand")))]
+ "TARGET_SSE"
+ "ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);")
+
+(define_insn "*<code>tf3"
+ [(set (match_operand:TF 0 "register_operand" "=x,x")
+ (any_logic:TF
+ (match_operand:TF 1 "nonimmediate_operand" "%0,x")
+ (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE
+ && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
+{
+ static char buf[32];
+ const char *ops;
+ const char *tmp
+ = (get_attr_mode (insn) == MODE_V4SF) ? "<logic>ps" : "p<logic>";
switch (which_alternative)
{
case 0:
- insn = "<logic>%s\t{%%2, %%0|%%0, %%2}";
+ ops = "%s\t{%%2, %%0|%%0, %%2}";
break;
case 1:
- insn = "v<logic>%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
+ ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
break;
default:
gcc_unreachable ();
}
- snprintf (buf, sizeof (buf), insn, suffix);
+ snprintf (buf, sizeof (buf), ops, tmp);
return buf;
}
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog")
+ (set (attr "prefix_data16")
+ (if_then_else
+ (and (eq_attr "alternative" "0")
+ (eq_attr "mode" "TI"))
+ (const_string "1")
+ (const_string "*")))
(set_attr "prefix" "orig,vex")
- (set_attr "mode" "<ssevecmode>")])
+ (set (attr "mode")
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "V4SF")
+ (match_test "TARGET_AVX")
+ (const_string "TI")
+ (ior (not (match_test "TARGET_SSE2"))
+ (match_test "optimize_function_for_size_p (cfun)"))
+ (const_string "V4SF")
+ ]
+ (const_string "TI")))])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
(match_dup 4)
(const_int 1)))]
"TARGET_FMA4"
-{
- operands[4] = CONST0_RTX (<MODE>mode);
-})
+ "operands[4] = CONST0_RTX (<MODE>mode);")
(define_insn "*fma4i_vmfmadd_<mode>"
[(set (match_operand:VF_128 0 "register_operand" "=x,x")
(match_operand:VF_128 1 "nonimmediate_operand" "%x,x")
(match_operand:VF_128 2 "nonimmediate_operand" " x,m")
(match_operand:VF_128 3 "nonimmediate_operand" "xm,x"))
- (match_operand:VF_128 4 "const0_operand" "")
+ (match_operand:VF_128 4 "const0_operand")
(const_int 1)))]
"TARGET_FMA4"
"vfmadd<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
(match_operand:VF_128 2 "nonimmediate_operand" " x,m")
(neg:VF_128
(match_operand:VF_128 3 "nonimmediate_operand" "xm,x")))
- (match_operand:VF_128 4 "const0_operand" "")
+ (match_operand:VF_128 4 "const0_operand")
(const_int 1)))]
"TARGET_FMA4"
"vfmsub<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
(match_operand:VF_128 1 "nonimmediate_operand" "%x,x"))
(match_operand:VF_128 2 "nonimmediate_operand" " x,m")
(match_operand:VF_128 3 "nonimmediate_operand" "xm,x"))
- (match_operand:VF_128 4 "const0_operand" "")
+ (match_operand:VF_128 4 "const0_operand")
(const_int 1)))]
"TARGET_FMA4"
"vfnmadd<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
(match_operand:VF_128 2 "nonimmediate_operand" " x,m")
(neg:VF_128
(match_operand:VF_128 3 "nonimmediate_operand" "xm,x")))
- (match_operand:VF_128 4 "const0_operand" "")
+ (match_operand:VF_128 4 "const0_operand")
(const_int 1)))]
"TARGET_FMA4"
"vfnmsub<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
(set_attr "athlon_decode" "vector,double,*")
(set_attr "amdfam10_decode" "vector,double,*")
(set_attr "bdver1_decode" "double,direct,*")
+ (set_attr "btver2_decode" "double,double,double")
(set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "SF")])
(set_attr "athlon_decode" "vector,double,*")
(set_attr "amdfam10_decode" "vector,double,*")
(set_attr "bdver1_decode" "double,direct,*")
+ (set_attr "btver2_decode" "double,double,double")
(set_attr "length_vex" "*,*,4")
(set_attr "prefix_rex" "1,1,*")
(set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "<sseinsnmode>")])
(define_expand "floatuns<sseintvecmodelower><mode>2"
- [(match_operand:VF1 0 "register_operand" "")
- (match_operand:<sseintvecmode> 1 "register_operand" "")]
+ [(match_operand:VF1 0 "register_operand")
+ (match_operand:<sseintvecmode> 1 "register_operand")]
"TARGET_SSE2 && (<MODE>mode == V4SFmode || TARGET_AVX2)"
{
ix86_expand_vector_convert_uns_vsivsf (operands[0], operands[1]);
(set_attr "mode" "TI")])
(define_expand "fixuns_trunc<mode><sseintvecmodelower>2"
- [(match_operand:<sseintvecmode> 0 "register_operand" "")
- (match_operand:VF1 1 "register_operand" "")]
+ [(match_operand:<sseintvecmode> 0 "register_operand")
+ (match_operand:VF1 1 "register_operand")]
"TARGET_SSE2"
{
rtx tmp[3];
[(set_attr "type" "ssecvt")
(set_attr "unit" "mmx")
(set_attr "bdver1_decode" "double")
+ (set_attr "btver2_decode" "direct")
(set_attr "prefix_data16" "1")
(set_attr "mode" "DI")])
(set_attr "athlon_decode" "double,direct,*")
(set_attr "amdfam10_decode" "vector,double,*")
(set_attr "bdver1_decode" "double,direct,*")
+ (set_attr "btver2_decode" "double,double,double")
(set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "DF")])
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "bdver1_decode" "double,double")
+ (set_attr "btver2_decode" "double,double")
(set_attr "prefix_rep" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "SI")])
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
(set_attr "bdver1_decode" "double,double")
+ (set_attr "btver2_decode" "double,double")
(set_attr "prefix_rep" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "SI")])
(set_attr "mode" "OI")])
(define_expand "avx_cvtpd2dq256_2"
- [(set (match_operand:V8SI 0 "register_operand" "")
+ [(set (match_operand:V8SI 0 "register_operand")
(vec_concat:V8SI
- (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "")]
+ (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand")]
UNSPEC_FIX_NOTRUNC)
(match_dup 2)))]
"TARGET_AVX"
(vec_concat:V8SI
(unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "xm")]
UNSPEC_FIX_NOTRUNC)
- (match_operand:V4SI 2 "const0_operand" "")))]
+ (match_operand:V4SI 2 "const0_operand")))]
"TARGET_AVX"
"vcvtpd2dq{y}\t{%1, %x0|%x0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "vex")
+ (set_attr "btver2_decode" "vector")
(set_attr "mode" "OI")])
(define_expand "sse2_cvtpd2dq"
- [(set (match_operand:V4SI 0 "register_operand" "")
+ [(set (match_operand:V4SI 0 "register_operand")
(vec_concat:V4SI
- (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "")]
+ (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand")]
UNSPEC_FIX_NOTRUNC)
(match_dup 2)))]
"TARGET_SSE2"
(vec_concat:V4SI
(unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
UNSPEC_FIX_NOTRUNC)
- (match_operand:V2SI 2 "const0_operand" "")))]
+ (match_operand:V2SI 2 "const0_operand")))]
"TARGET_SSE2"
{
if (TARGET_AVX)
(set_attr "mode" "OI")])
(define_expand "avx_cvttpd2dq256_2"
- [(set (match_operand:V8SI 0 "register_operand" "")
+ [(set (match_operand:V8SI 0 "register_operand")
(vec_concat:V8SI
- (fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" ""))
+ (fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand"))
(match_dup 2)))]
"TARGET_AVX"
"operands[2] = CONST0_RTX (V4SImode);")
[(set (match_operand:V8SI 0 "register_operand" "=x")
(vec_concat:V8SI
(fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" "xm"))
- (match_operand:V4SI 2 "const0_operand" "")))]
+ (match_operand:V4SI 2 "const0_operand")))]
"TARGET_AVX"
"vcvttpd2dq{y}\t{%1, %x0|%x0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "vex")
+ (set_attr "btver2_decode" "vector")
(set_attr "mode" "OI")])
(define_expand "sse2_cvttpd2dq"
- [(set (match_operand:V4SI 0 "register_operand" "")
+ [(set (match_operand:V4SI 0 "register_operand")
(vec_concat:V4SI
- (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" ""))
+ (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand"))
(match_dup 2)))]
"TARGET_SSE2"
"operands[2] = CONST0_RTX (V2SImode);")
[(set (match_operand:V4SI 0 "register_operand" "=x")
(vec_concat:V4SI
(fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
- (match_operand:V2SI 2 "const0_operand" "")))]
+ (match_operand:V2SI 2 "const0_operand")))]
"TARGET_SSE2"
{
if (TARGET_AVX)
(set_attr "athlon_decode" "vector,double,*")
(set_attr "amdfam10_decode" "vector,double,*")
(set_attr "bdver1_decode" "direct,direct,*")
+ (set_attr "btver2_decode" "double,double,double")
(set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "SF")])
(set_attr "amdfam10_decode" "vector,double,*")
(set_attr "athlon_decode" "direct,direct,*")
(set_attr "bdver1_decode" "direct,direct,*")
+ (set_attr "btver2_decode" "double,double,double")
(set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "DF")])
"vcvtpd2ps{y}\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "vex")
+ (set_attr "btver2_decode" "vector")
(set_attr "mode" "V4SF")])
(define_expand "sse2_cvtpd2ps"
- [(set (match_operand:V4SF 0 "register_operand" "")
+ [(set (match_operand:V4SF 0 "register_operand")
(vec_concat:V4SF
(float_truncate:V2SF
- (match_operand:V2DF 1 "nonimmediate_operand" ""))
+ (match_operand:V2DF 1 "nonimmediate_operand"))
(match_dup 2)))]
"TARGET_SSE2"
"operands[2] = CONST0_RTX (V2SFmode);")
(vec_concat:V4SF
(float_truncate:V2SF
(match_operand:V2DF 1 "nonimmediate_operand" "xm"))
- (match_operand:V2SF 2 "const0_operand" "")))]
+ (match_operand:V2SF 2 "const0_operand")))]
"TARGET_SSE2"
{
if (TARGET_AVX)
(vec_select:V4SF
(vec_concat:V8SF
(match_dup 2)
- (match_operand:V4SF 1 "nonimmediate_operand" ""))
+ (match_operand:V4SF 1 "nonimmediate_operand"))
(parallel [(const_int 6) (const_int 7)
(const_int 2) (const_int 3)])))
- (set (match_operand:V2DF 0 "register_operand" "")
+ (set (match_operand:V2DF 0 "register_operand")
(float_extend:V2DF
(vec_select:V2SF
(match_dup 2)
(define_expand "vec_unpacks_hi_v8sf"
[(set (match_dup 2)
(vec_select:V4SF
- (match_operand:V8SF 1 "nonimmediate_operand" "")
+ (match_operand:V8SF 1 "nonimmediate_operand")
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)])))
- (set (match_operand:V4DF 0 "register_operand" "")
+ (set (match_operand:V4DF 0 "register_operand")
(float_extend:V4DF
(match_dup 2)))]
"TARGET_AVX"
"operands[2] = gen_reg_rtx (V4SFmode);")
(define_expand "vec_unpacks_lo_v4sf"
- [(set (match_operand:V2DF 0 "register_operand" "")
+ [(set (match_operand:V2DF 0 "register_operand")
(float_extend:V2DF
(vec_select:V2SF
- (match_operand:V4SF 1 "nonimmediate_operand" "")
+ (match_operand:V4SF 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 1)]))))]
"TARGET_SSE2")
(define_expand "vec_unpacks_lo_v8sf"
- [(set (match_operand:V4DF 0 "register_operand" "")
+ [(set (match_operand:V4DF 0 "register_operand")
(float_extend:V4DF
(vec_select:V4SF
- (match_operand:V8SF 1 "nonimmediate_operand" "")
+ (match_operand:V8SF 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)]))))]
"TARGET_AVX")
[(V8HI "V4SF") (V4SI "V2DF") (V16HI "V8SF") (V8SI "V4DF")])
(define_expand "vec_unpacks_float_hi_<mode>"
- [(match_operand:<sseunpackfltmode> 0 "register_operand" "")
- (match_operand:VI2_AVX2 1 "register_operand" "")]
+ [(match_operand:<sseunpackfltmode> 0 "register_operand")
+ (match_operand:VI2_AVX2 1 "register_operand")]
"TARGET_SSE2"
{
rtx tmp = gen_reg_rtx (<sseunpackmode>mode);
})
(define_expand "vec_unpacks_float_lo_<mode>"
- [(match_operand:<sseunpackfltmode> 0 "register_operand" "")
- (match_operand:VI2_AVX2 1 "register_operand" "")]
+ [(match_operand:<sseunpackfltmode> 0 "register_operand")
+ (match_operand:VI2_AVX2 1 "register_operand")]
"TARGET_SSE2"
{
rtx tmp = gen_reg_rtx (<sseunpackmode>mode);
})
(define_expand "vec_unpacku_float_hi_<mode>"
- [(match_operand:<sseunpackfltmode> 0 "register_operand" "")
- (match_operand:VI2_AVX2 1 "register_operand" "")]
+ [(match_operand:<sseunpackfltmode> 0 "register_operand")
+ (match_operand:VI2_AVX2 1 "register_operand")]
"TARGET_SSE2"
{
rtx tmp = gen_reg_rtx (<sseunpackmode>mode);
})
(define_expand "vec_unpacku_float_lo_<mode>"
- [(match_operand:<sseunpackfltmode> 0 "register_operand" "")
- (match_operand:VI2_AVX2 1 "register_operand" "")]
+ [(match_operand:<sseunpackfltmode> 0 "register_operand")
+ (match_operand:VI2_AVX2 1 "register_operand")]
"TARGET_SSE2"
{
rtx tmp = gen_reg_rtx (<sseunpackmode>mode);
(define_expand "vec_unpacks_float_hi_v4si"
[(set (match_dup 2)
(vec_select:V4SI
- (match_operand:V4SI 1 "nonimmediate_operand" "")
+ (match_operand:V4SI 1 "nonimmediate_operand")
(parallel [(const_int 2) (const_int 3)
(const_int 2) (const_int 3)])))
- (set (match_operand:V2DF 0 "register_operand" "")
+ (set (match_operand:V2DF 0 "register_operand")
(float:V2DF
(vec_select:V2SI
(match_dup 2)
"operands[2] = gen_reg_rtx (V4SImode);")
(define_expand "vec_unpacks_float_lo_v4si"
- [(set (match_operand:V2DF 0 "register_operand" "")
+ [(set (match_operand:V2DF 0 "register_operand")
(float:V2DF
(vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "")
+ (match_operand:V4SI 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 1)]))))]
"TARGET_SSE2")
(define_expand "vec_unpacks_float_hi_v8si"
[(set (match_dup 2)
(vec_select:V4SI
- (match_operand:V8SI 1 "nonimmediate_operand" "")
+ (match_operand:V8SI 1 "nonimmediate_operand")
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)])))
- (set (match_operand:V4DF 0 "register_operand" "")
+ (set (match_operand:V4DF 0 "register_operand")
(float:V4DF
(match_dup 2)))]
"TARGET_AVX"
"operands[2] = gen_reg_rtx (V4SImode);")
(define_expand "vec_unpacks_float_lo_v8si"
- [(set (match_operand:V4DF 0 "register_operand" "")
+ [(set (match_operand:V4DF 0 "register_operand")
(float:V4DF
(vec_select:V4SI
- (match_operand:V8SI 1 "nonimmediate_operand" "")
+ (match_operand:V8SI 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)]))))]
"TARGET_AVX")
(define_expand "vec_unpacku_float_hi_v4si"
[(set (match_dup 5)
(vec_select:V4SI
- (match_operand:V4SI 1 "nonimmediate_operand" "")
+ (match_operand:V4SI 1 "nonimmediate_operand")
(parallel [(const_int 2) (const_int 3)
(const_int 2) (const_int 3)])))
(set (match_dup 6)
(lt:V2DF (match_dup 6) (match_dup 3)))
(set (match_dup 8)
(and:V2DF (match_dup 7) (match_dup 4)))
- (set (match_operand:V2DF 0 "register_operand" "")
+ (set (match_operand:V2DF 0 "register_operand")
(plus:V2DF (match_dup 6) (match_dup 8)))]
"TARGET_SSE2"
{
[(set (match_dup 5)
(float:V2DF
(vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "")
+ (match_operand:V4SI 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 1)]))))
(set (match_dup 6)
(lt:V2DF (match_dup 5) (match_dup 3)))
(set (match_dup 7)
(and:V2DF (match_dup 6) (match_dup 4)))
- (set (match_operand:V2DF 0 "register_operand" "")
+ (set (match_operand:V2DF 0 "register_operand")
(plus:V2DF (match_dup 5) (match_dup 7)))]
"TARGET_SSE2"
{
})
(define_expand "vec_unpacku_float_hi_v8si"
- [(match_operand:V4DF 0 "register_operand" "")
- (match_operand:V8SI 1 "register_operand" "")]
+ [(match_operand:V4DF 0 "register_operand")
+ (match_operand:V8SI 1 "register_operand")]
"TARGET_AVX"
{
REAL_VALUE_TYPE TWO32r;
})
(define_expand "vec_unpacku_float_lo_v8si"
- [(match_operand:V4DF 0 "register_operand" "")
- (match_operand:V8SI 1 "nonimmediate_operand" "")]
+ [(match_operand:V4DF 0 "register_operand")
+ (match_operand:V8SI 1 "nonimmediate_operand")]
"TARGET_AVX"
{
REAL_VALUE_TYPE TWO32r;
(define_expand "vec_pack_trunc_v4df"
[(set (match_dup 3)
(float_truncate:V4SF
- (match_operand:V4DF 1 "nonimmediate_operand" "")))
+ (match_operand:V4DF 1 "nonimmediate_operand")))
(set (match_dup 4)
(float_truncate:V4SF
- (match_operand:V4DF 2 "nonimmediate_operand" "")))
- (set (match_operand:V8SF 0 "register_operand" "")
+ (match_operand:V4DF 2 "nonimmediate_operand")))
+ (set (match_operand:V8SF 0 "register_operand")
(vec_concat:V8SF
(match_dup 3)
(match_dup 4)))]
})
(define_expand "vec_pack_trunc_v2df"
- [(match_operand:V4SF 0 "register_operand" "")
- (match_operand:V2DF 1 "nonimmediate_operand" "")
- (match_operand:V2DF 2 "nonimmediate_operand" "")]
+ [(match_operand:V4SF 0 "register_operand")
+ (match_operand:V2DF 1 "nonimmediate_operand")
+ (match_operand:V2DF 2 "nonimmediate_operand")]
"TARGET_SSE2"
{
rtx tmp0, tmp1;
})
(define_expand "vec_pack_sfix_trunc_v4df"
- [(match_operand:V8SI 0 "register_operand" "")
- (match_operand:V4DF 1 "nonimmediate_operand" "")
- (match_operand:V4DF 2 "nonimmediate_operand" "")]
+ [(match_operand:V8SI 0 "register_operand")
+ (match_operand:V4DF 1 "nonimmediate_operand")
+ (match_operand:V4DF 2 "nonimmediate_operand")]
"TARGET_AVX"
{
rtx r1, r2;
})
(define_expand "vec_pack_sfix_trunc_v2df"
- [(match_operand:V4SI 0 "register_operand" "")
- (match_operand:V2DF 1 "nonimmediate_operand" "")
- (match_operand:V2DF 2 "nonimmediate_operand" "")]
+ [(match_operand:V4SI 0 "register_operand")
+ (match_operand:V2DF 1 "nonimmediate_operand")
+ (match_operand:V2DF 2 "nonimmediate_operand")]
"TARGET_SSE2"
{
rtx tmp0, tmp1;
[(V4DF "V8SI") (V2DF "V4SI")])
(define_expand "vec_pack_ufix_trunc_<mode>"
- [(match_operand:<ssepackfltmode> 0 "register_operand" "")
- (match_operand:VF2 1 "register_operand" "")
- (match_operand:VF2 2 "register_operand" "")]
+ [(match_operand:<ssepackfltmode> 0 "register_operand")
+ (match_operand:VF2 1 "register_operand")
+ (match_operand:VF2 2 "register_operand")]
"TARGET_SSE2"
{
rtx tmp[7];
})
(define_expand "vec_pack_sfix_v4df"
- [(match_operand:V8SI 0 "register_operand" "")
- (match_operand:V4DF 1 "nonimmediate_operand" "")
- (match_operand:V4DF 2 "nonimmediate_operand" "")]
+ [(match_operand:V8SI 0 "register_operand")
+ (match_operand:V4DF 1 "nonimmediate_operand")
+ (match_operand:V4DF 2 "nonimmediate_operand")]
"TARGET_AVX"
{
rtx r1, r2;
})
(define_expand "vec_pack_sfix_v2df"
- [(match_operand:V4SI 0 "register_operand" "")
- (match_operand:V2DF 1 "nonimmediate_operand" "")
- (match_operand:V2DF 2 "nonimmediate_operand" "")]
+ [(match_operand:V4SI 0 "register_operand")
+ (match_operand:V2DF 1 "nonimmediate_operand")
+ (match_operand:V2DF 2 "nonimmediate_operand")]
"TARGET_SSE2"
{
rtx tmp0, tmp1;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "sse_movhlps_exp"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
+ [(set (match_operand:V4SF 0 "nonimmediate_operand")
(vec_select:V4SF
(vec_concat:V8SF
- (match_operand:V4SF 1 "nonimmediate_operand" "")
- (match_operand:V4SF 2 "nonimmediate_operand" ""))
+ (match_operand:V4SF 1 "nonimmediate_operand")
+ (match_operand:V4SF 2 "nonimmediate_operand"))
(parallel [(const_int 6)
(const_int 7)
(const_int 2)
(set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")])
(define_expand "sse_movlhps_exp"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
+ [(set (match_operand:V4SF 0 "nonimmediate_operand")
(vec_select:V4SF
(vec_concat:V8SF
- (match_operand:V4SF 1 "nonimmediate_operand" "")
- (match_operand:V4SF 2 "nonimmediate_operand" ""))
+ (match_operand:V4SF 1 "nonimmediate_operand")
+ (match_operand:V4SF 2 "nonimmediate_operand"))
(parallel [(const_int 0)
(const_int 1)
(const_int 4)
(const_int 3) (const_int 11)
(const_int 6) (const_int 14)
(const_int 7) (const_int 15)])))
- (set (match_operand:V8SF 0 "register_operand" "")
+ (set (match_operand:V8SF 0 "register_operand")
(vec_select:V8SF
(vec_concat:V16SF
(match_dup 3)
(const_int 3) (const_int 11)
(const_int 6) (const_int 14)
(const_int 7) (const_int 15)])))
- (set (match_operand:V8SF 0 "register_operand" "")
+ (set (match_operand:V8SF 0 "register_operand")
(vec_select:V8SF
(vec_concat:V16SF
(match_dup 3)
(set_attr "mode" "V4SF")])
(define_expand "avx_shufps256"
- [(match_operand:V8SF 0 "register_operand" "")
- (match_operand:V8SF 1 "register_operand" "")
- (match_operand:V8SF 2 "nonimmediate_operand" "")
- (match_operand:SI 3 "const_int_operand" "")]
+ [(match_operand:V8SF 0 "register_operand")
+ (match_operand:V8SF 1 "register_operand")
+ (match_operand:V8SF 2 "nonimmediate_operand")
+ (match_operand:SI 3 "const_int_operand")]
"TARGET_AVX"
{
int mask = INTVAL (operands[3]);
(vec_concat:V16SF
(match_operand:V8SF 1 "register_operand" "x")
(match_operand:V8SF 2 "nonimmediate_operand" "xm"))
- (parallel [(match_operand 3 "const_0_to_3_operand" "")
- (match_operand 4 "const_0_to_3_operand" "")
- (match_operand 5 "const_8_to_11_operand" "")
- (match_operand 6 "const_8_to_11_operand" "")
- (match_operand 7 "const_4_to_7_operand" "")
- (match_operand 8 "const_4_to_7_operand" "")
- (match_operand 9 "const_12_to_15_operand" "")
- (match_operand 10 "const_12_to_15_operand" "")])))]
+ (parallel [(match_operand 3 "const_0_to_3_operand" )
+ (match_operand 4 "const_0_to_3_operand" )
+ (match_operand 5 "const_8_to_11_operand" )
+ (match_operand 6 "const_8_to_11_operand" )
+ (match_operand 7 "const_4_to_7_operand" )
+ (match_operand 8 "const_4_to_7_operand" )
+ (match_operand 9 "const_12_to_15_operand")
+ (match_operand 10 "const_12_to_15_operand")])))]
"TARGET_AVX
&& (INTVAL (operands[3]) == (INTVAL (operands[7]) - 4)
&& INTVAL (operands[4]) == (INTVAL (operands[8]) - 4)
return "vshufps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
}
- [(set_attr "type" "sselog")
+ [(set_attr "type" "sseshuf")
(set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
(define_expand "sse_shufps"
- [(match_operand:V4SF 0 "register_operand" "")
- (match_operand:V4SF 1 "register_operand" "")
- (match_operand:V4SF 2 "nonimmediate_operand" "")
- (match_operand:SI 3 "const_int_operand" "")]
+ [(match_operand:V4SF 0 "register_operand")
+ (match_operand:V4SF 1 "register_operand")
+ (match_operand:V4SF 2 "nonimmediate_operand")
+ (match_operand:SI 3 "const_int_operand")]
"TARGET_SSE"
{
int mask = INTVAL (operands[3]);
(vec_concat:<ssedoublevecmode>
(match_operand:VI4F_128 1 "register_operand" "0,x")
(match_operand:VI4F_128 2 "nonimmediate_operand" "xm,xm"))
- (parallel [(match_operand 3 "const_0_to_3_operand" "")
- (match_operand 4 "const_0_to_3_operand" "")
- (match_operand 5 "const_4_to_7_operand" "")
- (match_operand 6 "const_4_to_7_operand" "")])))]
+ (parallel [(match_operand 3 "const_0_to_3_operand")
+ (match_operand 4 "const_0_to_3_operand")
+ (match_operand 5 "const_4_to_7_operand")
+ (match_operand 6 "const_4_to_7_operand")])))]
"TARGET_SSE"
{
int mask = 0;
}
}
[(set_attr "isa" "noavx,avx")
- (set_attr "type" "sselog")
+ (set_attr "type" "sseshuf")
(set_attr "length_immediate" "1")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "V4SF")])
(set_attr "mode" "V2SF,V4SF,V2SF")])
(define_expand "sse_loadhps_exp"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
+ [(set (match_operand:V4SF 0 "nonimmediate_operand")
(vec_concat:V4SF
(vec_select:V2SF
- (match_operand:V4SF 1 "nonimmediate_operand" "")
+ (match_operand:V4SF 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 1)]))
- (match_operand:V2SF 2 "nonimmediate_operand" "")))]
+ (match_operand:V2SF 2 "nonimmediate_operand")))]
"TARGET_SSE"
{
rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);
(set_attr "mode" "V2SF,V4SF,V2SF")])
(define_expand "sse_loadlps_exp"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
+ [(set (match_operand:V4SF 0 "nonimmediate_operand")
(vec_concat:V4SF
- (match_operand:V2SF 2 "nonimmediate_operand" "")
+ (match_operand:V2SF 2 "nonimmediate_operand")
(vec_select:V2SF
- (match_operand:V4SF 1 "nonimmediate_operand" "")
+ (match_operand:V4SF 1 "nonimmediate_operand")
(parallel [(const_int 2) (const_int 3)]))))]
"TARGET_SSE"
{
vmovlps\t{%2, %1, %0|%0, %1, %2}
%vmovlps\t{%2, %0|%0, %2}"
[(set_attr "isa" "noavx,avx,noavx,avx,*")
- (set_attr "type" "sselog,sselog,ssemov,ssemov,ssemov")
+ (set_attr "type" "sseshuf,sseshuf,ssemov,ssemov,ssemov")
(set_attr "length_immediate" "1,1,*,*,*")
(set_attr "prefix" "orig,vex,orig,vex,maybe_vex")
(set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")])
(set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
+(define_insn "avx2_vec_dupv8sf_1"
+ [(set (match_operand:V8SF 0 "register_operand" "=x")
+ (vec_duplicate:V8SF
+ (vec_select:SF
+ (match_operand:V8SF 1 "register_operand" "x")
+ (parallel [(const_int 0)]))))]
+ "TARGET_AVX2"
+ "vbroadcastss\t{%x1, %0|%0, %x1}"
+ [(set_attr "type" "sselog1")
+ (set_attr "prefix" "vex")
+ (set_attr "mode" "V8SF")])
+
(define_insn "vec_dupv4sf"
[(set (match_operand:V4SF 0 "register_operand" "=x,x,x")
(vec_duplicate:V4SF
vbroadcastss\t{%1, %0|%0, %1}
shufps\t{$0, %0, %0|%0, %0, 0}"
[(set_attr "isa" "avx,avx,noavx")
- (set_attr "type" "sselog1,ssemov,sselog1")
+ (set_attr "type" "sseshuf1,ssemov,sseshuf1")
(set_attr "length_immediate" "1,0,1")
(set_attr "prefix_extra" "0,1,*")
(set_attr "prefix" "vex,vex,orig")
(set_attr "mode" "V4SF,V4SF,V2SF,V2SF")])
(define_expand "vec_init<mode>"
- [(match_operand:V_128 0 "register_operand" "")
- (match_operand 1 "" "")]
+ [(match_operand:V_128 0 "register_operand")
+ (match_operand 1)]
"TARGET_SSE"
{
ix86_expand_vector_init (false, operands[0], operands[1]);
(vec_duplicate:V4SF
(match_operand:SF 2 "nonimmediate_operand" "xm,xm"))
(match_operand:V4SF 1 "register_operand" "0,x")
- (match_operand:SI 3 "const_int_operand" "")))]
+ (match_operand:SI 3 "const_int_operand")))]
"TARGET_SSE4_1
&& ((unsigned) exact_log2 (INTVAL (operands[3]))
< GET_MODE_NUNITS (V4SFmode))"
(set_attr "mode" "V4SF")])
(define_split
- [(set (match_operand:VI4F_128 0 "memory_operand" "")
+ [(set (match_operand:VI4F_128 0 "memory_operand")
(vec_merge:VI4F_128
(vec_duplicate:VI4F_128
- (match_operand:<ssescalarmode> 1 "nonmemory_operand" ""))
+ (match_operand:<ssescalarmode> 1 "nonmemory_operand"))
(match_dup 0)
(const_int 1)))]
"TARGET_SSE && reload_completed"
})
(define_expand "vec_set<mode>"
- [(match_operand:V 0 "register_operand" "")
- (match_operand:<ssescalarmode> 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")]
+ [(match_operand:V 0 "register_operand")
+ (match_operand:<ssescalarmode> 1 "register_operand")
+ (match_operand 2 "const_int_operand")]
"TARGET_SSE"
{
ix86_expand_vector_set (false, operands[0], operands[1],
})
(define_expand "avx_vextractf128<mode>"
- [(match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "")
- (match_operand:V_256 1 "register_operand" "")
- (match_operand:SI 2 "const_0_to_1_operand" "")]
+ [(match_operand:<ssehalfvecmode> 0 "nonimmediate_operand")
+ (match_operand:V_256 1 "register_operand")
+ (match_operand:SI 2 "const_0_to_1_operand")]
"TARGET_AVX"
{
rtx (*insn)(rtx, rtx);
(V4DF "TARGET_AVX") V2DF])
(define_expand "vec_extract<mode>"
- [(match_operand:<ssescalarmode> 0 "register_operand" "")
- (match_operand:VEC_EXTRACT_MODE 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")]
+ [(match_operand:<ssescalarmode> 0 "register_operand")
+ (match_operand:VEC_EXTRACT_MODE 1 "register_operand")
+ (match_operand 2 "const_int_operand")]
"TARGET_SSE"
{
ix86_expand_vector_extract (false, operands[0], operands[1],
(match_dup 2))
(parallel [(const_int 1) (const_int 5)
(const_int 3) (const_int 7)])))
- (set (match_operand:V4DF 0 "register_operand" "")
+ (set (match_operand:V4DF 0 "register_operand")
(vec_select:V4DF
(vec_concat:V8DF
(match_dup 3)
(define_expand "vec_interleave_highv2df"
- [(set (match_operand:V2DF 0 "register_operand" "")
+ [(set (match_operand:V2DF 0 "register_operand")
(vec_select:V2DF
(vec_concat:V4DF
- (match_operand:V2DF 1 "nonimmediate_operand" "")
- (match_operand:V2DF 2 "nonimmediate_operand" ""))
+ (match_operand:V2DF 1 "nonimmediate_operand")
+ (match_operand:V2DF 2 "nonimmediate_operand"))
(parallel [(const_int 1)
(const_int 3)])))]
"TARGET_SSE2"
;; Recall that the 256-bit unpck insns only shuffle within their lanes.
(define_expand "avx_movddup256"
- [(set (match_operand:V4DF 0 "register_operand" "")
+ [(set (match_operand:V4DF 0 "register_operand")
(vec_select:V4DF
(vec_concat:V8DF
- (match_operand:V4DF 1 "nonimmediate_operand" "")
+ (match_operand:V4DF 1 "nonimmediate_operand")
(match_dup 1))
(parallel [(const_int 0) (const_int 4)
(const_int 2) (const_int 6)])))]
"TARGET_AVX")
(define_expand "avx_unpcklpd256"
- [(set (match_operand:V4DF 0 "register_operand" "")
+ [(set (match_operand:V4DF 0 "register_operand")
(vec_select:V4DF
(vec_concat:V8DF
- (match_operand:V4DF 1 "register_operand" "")
- (match_operand:V4DF 2 "nonimmediate_operand" ""))
+ (match_operand:V4DF 1 "register_operand")
+ (match_operand:V4DF 2 "nonimmediate_operand"))
(parallel [(const_int 0) (const_int 4)
(const_int 2) (const_int 6)])))]
"TARGET_AVX")
(match_dup 2))
(parallel [(const_int 1) (const_int 5)
(const_int 3) (const_int 7)])))
- (set (match_operand:V4DF 0 "register_operand" "")
+ (set (match_operand:V4DF 0 "register_operand")
(vec_select:V4DF
(vec_concat:V8DF
(match_dup 3)
})
(define_expand "vec_interleave_lowv2df"
- [(set (match_operand:V2DF 0 "register_operand" "")
+ [(set (match_operand:V2DF 0 "register_operand")
(vec_select:V2DF
(vec_concat:V4DF
- (match_operand:V2DF 1 "nonimmediate_operand" "")
- (match_operand:V2DF 2 "nonimmediate_operand" ""))
+ (match_operand:V2DF 1 "nonimmediate_operand")
+ (match_operand:V2DF 2 "nonimmediate_operand"))
(parallel [(const_int 0)
(const_int 2)])))]
"TARGET_SSE2"
(set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,V1DF")])
(define_split
- [(set (match_operand:V2DF 0 "memory_operand" "")
+ [(set (match_operand:V2DF 0 "memory_operand")
(vec_select:V2DF
(vec_concat:V4DF
- (match_operand:V2DF 1 "register_operand" "")
+ (match_operand:V2DF 1 "register_operand")
(match_dup 1))
(parallel [(const_int 0)
(const_int 2)])))]
})
(define_split
- [(set (match_operand:V2DF 0 "register_operand" "")
+ [(set (match_operand:V2DF 0 "register_operand")
(vec_select:V2DF
(vec_concat:V4DF
- (match_operand:V2DF 1 "memory_operand" "")
+ (match_operand:V2DF 1 "memory_operand")
(match_dup 1))
- (parallel [(match_operand:SI 2 "const_0_to_1_operand" "")
- (match_operand:SI 3 "const_int_operand" "")])))]
+ (parallel [(match_operand:SI 2 "const_0_to_1_operand")
+ (match_operand:SI 3 "const_int_operand")])))]
"TARGET_SSE3 && INTVAL (operands[2]) + 2 == INTVAL (operands[3])"
[(set (match_dup 0) (vec_duplicate:V2DF (match_dup 1)))]
{
})
(define_expand "avx_shufpd256"
- [(match_operand:V4DF 0 "register_operand" "")
- (match_operand:V4DF 1 "register_operand" "")
- (match_operand:V4DF 2 "nonimmediate_operand" "")
- (match_operand:SI 3 "const_int_operand" "")]
+ [(match_operand:V4DF 0 "register_operand")
+ (match_operand:V4DF 1 "register_operand")
+ (match_operand:V4DF 2 "nonimmediate_operand")
+ (match_operand:SI 3 "const_int_operand")]
"TARGET_AVX"
{
int mask = INTVAL (operands[3]);
(vec_concat:V8DF
(match_operand:V4DF 1 "register_operand" "x")
(match_operand:V4DF 2 "nonimmediate_operand" "xm"))
- (parallel [(match_operand 3 "const_0_to_1_operand" "")
- (match_operand 4 "const_4_to_5_operand" "")
- (match_operand 5 "const_2_to_3_operand" "")
- (match_operand 6 "const_6_to_7_operand" "")])))]
+ (parallel [(match_operand 3 "const_0_to_1_operand")
+ (match_operand 4 "const_4_to_5_operand")
+ (match_operand 5 "const_2_to_3_operand")
+ (match_operand 6 "const_6_to_7_operand")])))]
"TARGET_AVX"
{
int mask;
return "vshufpd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
}
- [(set_attr "type" "sselog")
+ [(set_attr "type" "sseshuf")
(set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V4DF")])
(define_expand "sse2_shufpd"
- [(match_operand:V2DF 0 "register_operand" "")
- (match_operand:V2DF 1 "register_operand" "")
- (match_operand:V2DF 2 "nonimmediate_operand" "")
- (match_operand:SI 3 "const_int_operand" "")]
+ [(match_operand:V2DF 0 "register_operand")
+ (match_operand:V2DF 1 "register_operand")
+ (match_operand:V2DF 2 "nonimmediate_operand")
+ (match_operand:SI 3 "const_int_operand")]
"TARGET_SSE2"
{
int mask = INTVAL (operands[3]);
(vec_concat:<ssedoublevecmode>
(match_operand:VI8F_128 1 "register_operand" "0,x")
(match_operand:VI8F_128 2 "nonimmediate_operand" "xm,xm"))
- (parallel [(match_operand 3 "const_0_to_1_operand" "")
- (match_operand 4 "const_2_to_3_operand" "")])))]
+ (parallel [(match_operand 3 "const_0_to_1_operand")
+ (match_operand 4 "const_2_to_3_operand")])))]
"TARGET_SSE2"
{
int mask;
}
}
[(set_attr "isa" "noavx,avx")
- (set_attr "type" "sselog")
+ (set_attr "type" "sseshuf")
(set_attr "length_immediate" "1")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "V2DF")])
(set_attr "mode" "V1DF,V1DF,V2DF,DF,DF,DF")])
(define_split
- [(set (match_operand:DF 0 "register_operand" "")
+ [(set (match_operand:DF 0 "register_operand")
(vec_select:DF
- (match_operand:V2DF 1 "memory_operand" "")
+ (match_operand:V2DF 1 "memory_operand")
(parallel [(const_int 1)])))]
"TARGET_SSE2 && reload_completed"
[(set (match_dup 0) (match_dup 1))]
(set_attr "mode" "V1DF,DF,DF,DF,DF")])
(define_split
- [(set (match_operand:DF 0 "register_operand" "")
+ [(set (match_operand:DF 0 "register_operand")
(vec_select:DF
- (match_operand:V2DF 1 "nonimmediate_operand" "")
+ (match_operand:V2DF 1 "nonimmediate_operand")
(parallel [(const_int 0)])))]
"TARGET_SSE2 && reload_completed"
[(const_int 0)]
(set_attr "mode" "V2SF,V4SF,V2SF")])
(define_expand "sse2_loadhpd_exp"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
+ [(set (match_operand:V2DF 0 "nonimmediate_operand")
(vec_concat:V2DF
(vec_select:DF
- (match_operand:V2DF 1 "nonimmediate_operand" "")
+ (match_operand:V2DF 1 "nonimmediate_operand")
(parallel [(const_int 0)]))
- (match_operand:DF 2 "nonimmediate_operand" "")))]
+ (match_operand:DF 2 "nonimmediate_operand")))]
"TARGET_SSE2"
{
rtx dst = ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);
(set_attr "mode" "V1DF,V1DF,V2DF,V2DF,DF,DF,DF")])
(define_split
- [(set (match_operand:V2DF 0 "memory_operand" "")
+ [(set (match_operand:V2DF 0 "memory_operand")
(vec_concat:V2DF
(vec_select:DF (match_dup 0) (parallel [(const_int 0)]))
- (match_operand:DF 1 "register_operand" "")))]
+ (match_operand:DF 1 "register_operand")))]
"TARGET_SSE2 && reload_completed"
[(set (match_dup 0) (match_dup 1))]
"operands[0] = adjust_address (operands[0], DFmode, 8);")
(define_expand "sse2_loadlpd_exp"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
+ [(set (match_operand:V2DF 0 "nonimmediate_operand")
(vec_concat:V2DF
- (match_operand:DF 2 "nonimmediate_operand" "")
+ (match_operand:DF 2 "nonimmediate_operand")
(vec_select:DF
- (match_operand:V2DF 1 "nonimmediate_operand" "")
+ (match_operand:V2DF 1 "nonimmediate_operand")
(parallel [(const_int 1)]))))]
"TARGET_SSE2"
{
(set_attr "mode" "DF,V1DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,DF,DF,DF")])
(define_split
- [(set (match_operand:V2DF 0 "memory_operand" "")
+ [(set (match_operand:V2DF 0 "memory_operand")
(vec_concat:V2DF
- (match_operand:DF 1 "register_operand" "")
+ (match_operand:DF 1 "register_operand")
(vec_select:DF (match_dup 0) (parallel [(const_int 1)]))))]
"TARGET_SSE2 && reload_completed"
[(set (match_dup 0) (match_dup 1))]
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "neg<mode>2"
- [(set (match_operand:VI_AVX2 0 "register_operand" "")
+ [(set (match_operand:VI_AVX2 0 "register_operand")
(minus:VI_AVX2
(match_dup 2)
- (match_operand:VI_AVX2 1 "nonimmediate_operand" "")))]
+ (match_operand:VI_AVX2 1 "nonimmediate_operand")))]
"TARGET_SSE2"
"operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
(define_expand "<plusminus_insn><mode>3"
- [(set (match_operand:VI_AVX2 0 "register_operand" "")
+ [(set (match_operand:VI_AVX2 0 "register_operand")
(plusminus:VI_AVX2
- (match_operand:VI_AVX2 1 "nonimmediate_operand" "")
- (match_operand:VI_AVX2 2 "nonimmediate_operand" "")))]
+ (match_operand:VI_AVX2 1 "nonimmediate_operand")
+ (match_operand:VI_AVX2 2 "nonimmediate_operand")))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(set_attr "mode" "<sseinsnmode>")])
(define_expand "<sse2_avx2>_<plusminus_insn><mode>3"
- [(set (match_operand:VI12_AVX2 0 "register_operand" "")
+ [(set (match_operand:VI12_AVX2 0 "register_operand")
(sat_plusminus:VI12_AVX2
- (match_operand:VI12_AVX2 1 "nonimmediate_operand" "")
- (match_operand:VI12_AVX2 2 "nonimmediate_operand" "")))]
+ (match_operand:VI12_AVX2 1 "nonimmediate_operand")
+ (match_operand:VI12_AVX2 2 "nonimmediate_operand")))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
-(define_insn_and_split "mul<mode>3"
- [(set (match_operand:VI1_AVX2 0 "register_operand" "")
- (mult:VI1_AVX2 (match_operand:VI1_AVX2 1 "register_operand" "")
- (match_operand:VI1_AVX2 2 "register_operand" "")))]
- "TARGET_SSE2
- && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
+(define_expand "mul<mode>3"
+ [(set (match_operand:VI1_AVX2 0 "register_operand")
+ (mult:VI1_AVX2 (match_operand:VI1_AVX2 1 "register_operand")
+ (match_operand:VI1_AVX2 2 "register_operand")))]
+ "TARGET_SSE2"
{
- rtx t[6];
- int i;
- enum machine_mode mulmode = <sseunpackmode>mode;
-
- for (i = 0; i < 6; ++i)
- t[i] = gen_reg_rtx (<MODE>mode);
-
- /* Unpack data such that we've got a source byte in each low byte of
- each word. We don't care what goes into the high byte of each word.
- Rather than trying to get zero in there, most convenient is to let
- it be a copy of the low byte. */
- emit_insn (gen_<vec_avx2>_interleave_high<mode> (t[0], operands[1],
- operands[1]));
- emit_insn (gen_<vec_avx2>_interleave_high<mode> (t[1], operands[2],
- operands[2]));
- emit_insn (gen_<vec_avx2>_interleave_low<mode> (t[2], operands[1],
- operands[1]));
- emit_insn (gen_<vec_avx2>_interleave_low<mode> (t[3], operands[2],
- operands[2]));
-
- /* Multiply words. The end-of-line annotations here give a picture of what
- the output of that instruction looks like. Dot means don't care; the
- letters are the bytes of the result with A being the most significant. */
- emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (mulmode, t[4]),
- gen_rtx_MULT (mulmode, /* .A.B.C.D.E.F.G.H */
- gen_lowpart (mulmode, t[0]),
- gen_lowpart (mulmode, t[1]))));
- emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (mulmode, t[5]),
- gen_rtx_MULT (mulmode, /* .I.J.K.L.M.N.O.P */
- gen_lowpart (mulmode, t[2]),
- gen_lowpart (mulmode, t[3]))));
-
- /* Extract the even bytes and merge them back together. */
- if (<MODE>mode == V16QImode)
- ix86_expand_vec_extract_even_odd (operands[0], t[5], t[4], 0);
- else
- {
- /* Since avx2_interleave_{low,high}v32qi used above aren't cross-lane,
- this can't be normal even extraction, but one where additionally
- the second and third quarter are swapped. That is even one insn
- shorter than even extraction. */
- rtvec v = rtvec_alloc (32);
- for (i = 0; i < 32; ++i)
- RTVEC_ELT (v, i)
- = GEN_INT (i * 2 + ((i & 24) == 8 ? 16 : (i & 24) == 16 ? -16 : 0));
- t[0] = operands[0];
- t[1] = t[5];
- t[2] = t[4];
- t[3] = gen_rtx_CONST_VECTOR (<MODE>mode, v);
- ix86_expand_vec_perm_const (t);
- }
-
- set_unique_reg_note (get_last_insn (), REG_EQUAL,
- gen_rtx_MULT (<MODE>mode, operands[1], operands[2]));
+ ix86_expand_vecop_qihi (MULT, operands[0], operands[1], operands[2]);
DONE;
})
(define_expand "mul<mode>3"
- [(set (match_operand:VI2_AVX2 0 "register_operand" "")
- (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "nonimmediate_operand" "")
- (match_operand:VI2_AVX2 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:VI2_AVX2 0 "register_operand")
+ (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "nonimmediate_operand")
+ (match_operand:VI2_AVX2 2 "nonimmediate_operand")))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
(set_attr "mode" "<sseinsnmode>")])
(define_expand "<s>mul<mode>3_highpart"
- [(set (match_operand:VI2_AVX2 0 "register_operand" "")
+ [(set (match_operand:VI2_AVX2 0 "register_operand")
(truncate:VI2_AVX2
(lshiftrt:<ssedoublemode>
(mult:<ssedoublemode>
(any_extend:<ssedoublemode>
- (match_operand:VI2_AVX2 1 "nonimmediate_operand" ""))
+ (match_operand:VI2_AVX2 1 "nonimmediate_operand"))
(any_extend:<ssedoublemode>
- (match_operand:VI2_AVX2 2 "nonimmediate_operand" "")))
+ (match_operand:VI2_AVX2 2 "nonimmediate_operand")))
(const_int 16))))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "<sseinsnmode>")])
-(define_expand "avx2_umulv4siv4di3"
- [(set (match_operand:V4DI 0 "register_operand" "")
+(define_expand "vec_widen_umult_even_v8si"
+ [(set (match_operand:V4DI 0 "register_operand")
(mult:V4DI
(zero_extend:V4DI
(vec_select:V4SI
- (match_operand:V8SI 1 "nonimmediate_operand" "")
+ (match_operand:V8SI 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 2)
(const_int 4) (const_int 6)])))
(zero_extend:V4DI
(vec_select:V4SI
- (match_operand:V8SI 2 "nonimmediate_operand" "")
+ (match_operand:V8SI 2 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 2)
(const_int 4) (const_int 6)])))))]
"TARGET_AVX2"
"ix86_fixup_binary_operands_no_copy (MULT, V8SImode, operands);")
-(define_insn "*avx_umulv4siv4di3"
+(define_insn "*vec_widen_umult_even_v8si"
[(set (match_operand:V4DI 0 "register_operand" "=x")
(mult:V4DI
(zero_extend:V4DI
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
-(define_expand "sse2_umulv2siv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "")
+(define_expand "vec_widen_umult_even_v4si"
+ [(set (match_operand:V2DI 0 "register_operand")
(mult:V2DI
(zero_extend:V2DI
(vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "")
+ (match_operand:V4SI 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 2)])))
(zero_extend:V2DI
(vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "")
+ (match_operand:V4SI 2 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 2)])))))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);")
-(define_insn "*sse2_umulv2siv2di3"
+(define_insn "*vec_widen_umult_even_v4si"
[(set (match_operand:V2DI 0 "register_operand" "=x,x")
(mult:V2DI
(zero_extend:V2DI
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
-(define_expand "avx2_mulv4siv4di3"
- [(set (match_operand:V4DI 0 "register_operand" "")
+(define_expand "vec_widen_smult_even_v8si"
+ [(set (match_operand:V4DI 0 "register_operand")
(mult:V4DI
(sign_extend:V4DI
(vec_select:V4SI
- (match_operand:V8SI 1 "nonimmediate_operand" "")
+ (match_operand:V8SI 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 2)
(const_int 4) (const_int 6)])))
(sign_extend:V4DI
(vec_select:V4SI
- (match_operand:V8SI 2 "nonimmediate_operand" "")
+ (match_operand:V8SI 2 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 2)
(const_int 4) (const_int 6)])))))]
"TARGET_AVX2"
"ix86_fixup_binary_operands_no_copy (MULT, V8SImode, operands);")
-(define_insn "*avx2_mulv4siv4di3"
+(define_insn "*vec_widen_smult_even_v8si"
[(set (match_operand:V4DI 0 "register_operand" "=x")
(mult:V4DI
(sign_extend:V4DI
(set_attr "mode" "OI")])
(define_expand "sse4_1_mulv2siv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "")
+ [(set (match_operand:V2DI 0 "register_operand")
(mult:V2DI
(sign_extend:V2DI
(vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "")
+ (match_operand:V4SI 1 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 2)])))
(sign_extend:V2DI
(vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "")
+ (match_operand:V4SI 2 "nonimmediate_operand")
(parallel [(const_int 0) (const_int 2)])))))]
"TARGET_SSE4_1"
"ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);")
(set_attr "mode" "TI")])
(define_expand "avx2_pmaddwd"
- [(set (match_operand:V8SI 0 "register_operand" "")
+ [(set (match_operand:V8SI 0 "register_operand")
(plus:V8SI
(mult:V8SI
(sign_extend:V8SI
(vec_select:V8HI
- (match_operand:V16HI 1 "nonimmediate_operand" "")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)
- (const_int 8)
- (const_int 10)
- (const_int 12)
- (const_int 14)])))
+ (match_operand:V16HI 1 "nonimmediate_operand")
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)
+ (const_int 8) (const_int 10)
+ (const_int 12) (const_int 14)])))
(sign_extend:V8SI
(vec_select:V8HI
- (match_operand:V16HI 2 "nonimmediate_operand" "")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)
- (const_int 8)
- (const_int 10)
- (const_int 12)
- (const_int 14)]))))
+ (match_operand:V16HI 2 "nonimmediate_operand")
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)
+ (const_int 8) (const_int 10)
+ (const_int 12) (const_int 14)]))))
(mult:V8SI
(sign_extend:V8SI
(vec_select:V8HI (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)
- (const_int 9)
- (const_int 11)
- (const_int 13)
- (const_int 15)])))
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)
+ (const_int 9) (const_int 11)
+ (const_int 13) (const_int 15)])))
(sign_extend:V8SI
(vec_select:V8HI (match_dup 2)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)
- (const_int 9)
- (const_int 11)
- (const_int 13)
- (const_int 15)]))))))]
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)
+ (const_int 9) (const_int 11)
+ (const_int 13) (const_int 15)]))))))]
"TARGET_AVX2"
"ix86_fixup_binary_operands_no_copy (MULT, V16HImode, operands);")
-(define_expand "sse2_pmaddwd"
- [(set (match_operand:V4SI 0 "register_operand" "")
- (plus:V4SI
- (mult:V4SI
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 1 "nonimmediate_operand" "")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)])))
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 2 "nonimmediate_operand" "")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)]))))
- (mult:V4SI
- (sign_extend:V4SI
- (vec_select:V4HI (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))
- (sign_extend:V4SI
- (vec_select:V4HI (match_dup 2)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)]))))))]
- "TARGET_SSE2"
- "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
-
(define_insn "*avx2_pmaddwd"
[(set (match_operand:V8SI 0 "register_operand" "=x")
(plus:V8SI
(sign_extend:V8SI
(vec_select:V8HI
(match_operand:V16HI 1 "nonimmediate_operand" "%x")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)
- (const_int 8)
- (const_int 10)
- (const_int 12)
- (const_int 14)])))
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)
+ (const_int 8) (const_int 10)
+ (const_int 12) (const_int 14)])))
(sign_extend:V8SI
(vec_select:V8HI
(match_operand:V16HI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)
- (const_int 8)
- (const_int 10)
- (const_int 12)
- (const_int 14)]))))
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)
+ (const_int 8) (const_int 10)
+ (const_int 12) (const_int 14)]))))
(mult:V8SI
(sign_extend:V8SI
(vec_select:V8HI (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)
- (const_int 9)
- (const_int 11)
- (const_int 13)
- (const_int 15)])))
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)
+ (const_int 9) (const_int 11)
+ (const_int 13) (const_int 15)])))
(sign_extend:V8SI
(vec_select:V8HI (match_dup 2)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)
- (const_int 9)
- (const_int 11)
- (const_int 13)
- (const_int 15)]))))))]
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)
+ (const_int 9) (const_int 11)
+ (const_int 13) (const_int 15)]))))))]
"TARGET_AVX2 && ix86_binary_operator_ok (MULT, V16HImode, operands)"
"vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
-(define_insn "*sse2_pmaddwd"
- [(set (match_operand:V4SI 0 "register_operand" "=x,x")
+(define_expand "sse2_pmaddwd"
+ [(set (match_operand:V4SI 0 "register_operand")
(plus:V4SI
(mult:V4SI
(sign_extend:V4SI
(vec_select:V4HI
- (match_operand:V8HI 1 "nonimmediate_operand" "%0,x")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)])))
+ (match_operand:V8HI 1 "nonimmediate_operand")
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)])))
(sign_extend:V4SI
(vec_select:V4HI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)]))))
+ (match_operand:V8HI 2 "nonimmediate_operand")
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)]))))
(mult:V4SI
(sign_extend:V4SI
(vec_select:V4HI (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)])))
(sign_extend:V4SI
(vec_select:V4HI (match_dup 2)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)]))))))]
- "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
- "@
- pmaddwd\t{%2, %0|%0, %2}
- vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "isa" "noavx,avx")
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)]))))))]
+ "TARGET_SSE2"
+ "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
+
+(define_insn "*sse2_pmaddwd"
+ [(set (match_operand:V4SI 0 "register_operand" "=x,x")
+ (plus:V4SI
+ (mult:V4SI
+ (sign_extend:V4SI
+ (vec_select:V4HI
+ (match_operand:V8HI 1 "nonimmediate_operand" "%0,x")
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)])))
+ (sign_extend:V4SI
+ (vec_select:V4HI
+ (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)]))))
+ (mult:V4SI
+ (sign_extend:V4SI
+ (vec_select:V4HI (match_dup 1)
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)])))
+ (sign_extend:V4SI
+ (vec_select:V4HI (match_dup 2)
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)]))))))]
+ "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
+ "@
+ pmaddwd\t{%2, %0|%0, %2}
+ vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
(set_attr "atom_unit" "simul")
(set_attr "prefix_data16" "1,*")
(set_attr "mode" "TI")])
(define_expand "mul<mode>3"
- [(set (match_operand:VI4_AVX2 0 "register_operand" "")
- (mult:VI4_AVX2 (match_operand:VI4_AVX2 1 "register_operand" "")
- (match_operand:VI4_AVX2 2 "register_operand" "")))]
+ [(set (match_operand:VI4_AVX2 0 "register_operand")
+ (mult:VI4_AVX2
+ (match_operand:VI4_AVX2 1 "nonimmediate_operand")
+ (match_operand:VI4_AVX2 2 "nonimmediate_operand")))]
"TARGET_SSE2"
{
- if (TARGET_SSE4_1 || TARGET_AVX)
- ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);
+ if (TARGET_SSE4_1)
+ {
+ if (CONSTANT_P (operands[2]))
+ operands[2] = validize_mem (force_const_mem (<MODE>mode, operands[2]));
+ ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);
+ }
+ else
+ {
+ ix86_expand_sse2_mulv4si3 (operands[0], operands[1], operands[2]);
+ DONE;
+ }
})
(define_insn "*<sse4_1_avx2>_mul<mode>3"
[(set (match_operand:VI4_AVX2 0 "register_operand" "=x,x")
- (mult:VI4_AVX2 (match_operand:VI4_AVX2 1 "nonimmediate_operand" "%0,x")
- (match_operand:VI4_AVX2 2 "nonimmediate_operand" "xm,xm")))]
+ (mult:VI4_AVX2
+ (match_operand:VI4_AVX2 1 "nonimmediate_operand" "%0,x")
+ (match_operand:VI4_AVX2 2 "nonimmediate_operand" "xm,xm")))]
"TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
"@
pmulld\t{%2, %0|%0, %2}
(set_attr "type" "sseimul")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
+ (set_attr "btver2_decode" "vector,vector")
(set_attr "mode" "<sseinsnmode>")])
-(define_insn_and_split "*sse2_mulv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "")
- (mult:V4SI (match_operand:V4SI 1 "register_operand" "")
- (match_operand:V4SI 2 "register_operand" "")))]
- "TARGET_SSE2 && !TARGET_SSE4_1 && !TARGET_AVX
- && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
-{
- rtx t1, t2, t3, t4, t5, t6, thirtytwo;
- rtx op0, op1, op2;
-
- op0 = operands[0];
- op1 = operands[1];
- op2 = operands[2];
- t1 = gen_reg_rtx (V4SImode);
- t2 = gen_reg_rtx (V4SImode);
- t3 = gen_reg_rtx (V4SImode);
- t4 = gen_reg_rtx (V4SImode);
- t5 = gen_reg_rtx (V4SImode);
- t6 = gen_reg_rtx (V4SImode);
- thirtytwo = GEN_INT (32);
-
- /* Multiply elements 2 and 0. */
- emit_insn (gen_sse2_umulv2siv2di3 (gen_lowpart (V2DImode, t1),
- op1, op2));
-
- /* Shift both input vectors down one element, so that elements 3
- and 1 are now in the slots for elements 2 and 0. For K8, at
- least, this is faster than using a shuffle. */
- emit_insn (gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, t2),
- gen_lowpart (V1TImode, op1),
- thirtytwo));
- emit_insn (gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, t3),
- gen_lowpart (V1TImode, op2),
- thirtytwo));
- /* Multiply elements 3 and 1. */
- emit_insn (gen_sse2_umulv2siv2di3 (gen_lowpart (V2DImode, t4),
- t2, t3));
-
- /* Move the results in element 2 down to element 1; we don't care
- what goes in elements 2 and 3. */
- emit_insn (gen_sse2_pshufd_1 (t5, t1, const0_rtx, const2_rtx,
- const0_rtx, const0_rtx));
- emit_insn (gen_sse2_pshufd_1 (t6, t4, const0_rtx, const2_rtx,
- const0_rtx, const0_rtx));
-
- /* Merge the parts back together. */
- emit_insn (gen_vec_interleave_lowv4si (op0, t5, t6));
-
- set_unique_reg_note (get_last_insn (), REG_EQUAL,
- gen_rtx_MULT (V4SImode, operands[1], operands[2]));
- DONE;
-})
-
-(define_insn_and_split "mul<mode>3"
- [(set (match_operand:VI8_AVX2 0 "register_operand" "")
- (mult:VI8_AVX2 (match_operand:VI8_AVX2 1 "register_operand" "")
- (match_operand:VI8_AVX2 2 "register_operand" "")))]
- "TARGET_SSE2
- && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
+(define_expand "mul<mode>3"
+ [(set (match_operand:VI8_AVX2 0 "register_operand")
+ (mult:VI8_AVX2 (match_operand:VI8_AVX2 1 "register_operand")
+ (match_operand:VI8_AVX2 2 "register_operand")))]
+ "TARGET_SSE2"
{
- rtx t1, t2, t3, t4, t5, t6, thirtytwo;
- rtx op0, op1, op2;
-
- op0 = operands[0];
- op1 = operands[1];
- op2 = operands[2];
-
- if (TARGET_XOP && <MODE>mode == V2DImode)
- {
- /* op1: A,B,C,D, op2: E,F,G,H */
- op1 = gen_lowpart (V4SImode, op1);
- op2 = gen_lowpart (V4SImode, op2);
-
- t1 = gen_reg_rtx (V4SImode);
- t2 = gen_reg_rtx (V4SImode);
- t3 = gen_reg_rtx (V2DImode);
- t4 = gen_reg_rtx (V2DImode);
-
- /* t1: B,A,D,C */
- emit_insn (gen_sse2_pshufd_1 (t1, op1,
- GEN_INT (1),
- GEN_INT (0),
- GEN_INT (3),
- GEN_INT (2)));
-
- /* t2: (B*E),(A*F),(D*G),(C*H) */
- emit_insn (gen_mulv4si3 (t2, t1, op2));
-
- /* t4: (B*E)+(A*F), (D*G)+(C*H) */
- emit_insn (gen_xop_phadddq (t3, t2));
-
- /* t5: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
- emit_insn (gen_ashlv2di3 (t4, t3, GEN_INT (32)));
-
- /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
- emit_insn (gen_xop_pmacsdql (op0, op1, op2, t4));
- }
- else
- {
- t1 = gen_reg_rtx (<MODE>mode);
- t2 = gen_reg_rtx (<MODE>mode);
- t3 = gen_reg_rtx (<MODE>mode);
- t4 = gen_reg_rtx (<MODE>mode);
- t5 = gen_reg_rtx (<MODE>mode);
- t6 = gen_reg_rtx (<MODE>mode);
- thirtytwo = GEN_INT (32);
-
- /* Multiply low parts. */
- emit_insn (gen_<sse2_avx2>_umulv<ssescalarnum>si<mode>3
- (t1, gen_lowpart (<ssepackmode>mode, op1),
- gen_lowpart (<ssepackmode>mode, op2)));
-
- /* Shift input vectors right 32 bits so we can multiply high parts. */
- emit_insn (gen_lshr<mode>3 (t2, op1, thirtytwo));
- emit_insn (gen_lshr<mode>3 (t3, op2, thirtytwo));
-
- /* Multiply high parts by low parts. */
- emit_insn (gen_<sse2_avx2>_umulv<ssescalarnum>si<mode>3
- (t4, gen_lowpart (<ssepackmode>mode, op1),
- gen_lowpart (<ssepackmode>mode, t3)));
- emit_insn (gen_<sse2_avx2>_umulv<ssescalarnum>si<mode>3
- (t5, gen_lowpart (<ssepackmode>mode, op2),
- gen_lowpart (<ssepackmode>mode, t2)));
-
- /* Shift them back. */
- emit_insn (gen_ashl<mode>3 (t4, t4, thirtytwo));
- emit_insn (gen_ashl<mode>3 (t5, t5, thirtytwo));
-
- /* Add the three parts together. */
- emit_insn (gen_add<mode>3 (t6, t1, t4));
- emit_insn (gen_add<mode>3 (op0, t6, t5));
- }
-
- set_unique_reg_note (get_last_insn (), REG_EQUAL,
- gen_rtx_MULT (<MODE>mode, operands[1], operands[2]));
+ ix86_expand_sse2_mulvxdi3 (operands[0], operands[1], operands[2]);
DONE;
})
(define_expand "vec_widen_<s>mult_hi_<mode>"
- [(match_operand:<sseunpackmode> 0 "register_operand" "")
+ [(match_operand:<sseunpackmode> 0 "register_operand")
(any_extend:<sseunpackmode>
- (match_operand:VI2_AVX2 1 "register_operand" ""))
- (match_operand:VI2_AVX2 2 "register_operand" "")]
+ (match_operand:VI124_AVX2 1 "register_operand"))
+ (match_operand:VI124_AVX2 2 "register_operand")]
"TARGET_SSE2"
{
- rtx op1, op2, t1, t2, dest;
-
- op1 = operands[1];
- op2 = operands[2];
- t1 = gen_reg_rtx (<MODE>mode);
- t2 = gen_reg_rtx (<MODE>mode);
- dest = gen_lowpart (<MODE>mode, operands[0]);
-
- emit_insn (gen_mul<mode>3 (t1, op1, op2));
- emit_insn (gen_<s>mul<mode>3_highpart (t2, op1, op2));
- emit_insn (gen_vec_interleave_high<mode> (dest, t1, t2));
+ ix86_expand_mul_widen_hilo (operands[0], operands[1], operands[2],
+ <u_bool>, true);
DONE;
})
(define_expand "vec_widen_<s>mult_lo_<mode>"
- [(match_operand:<sseunpackmode> 0 "register_operand" "")
+ [(match_operand:<sseunpackmode> 0 "register_operand")
(any_extend:<sseunpackmode>
- (match_operand:VI2_AVX2 1 "register_operand" ""))
- (match_operand:VI2_AVX2 2 "register_operand" "")]
+ (match_operand:VI124_AVX2 1 "register_operand"))
+ (match_operand:VI124_AVX2 2 "register_operand")]
"TARGET_SSE2"
{
- rtx op1, op2, t1, t2, dest;
-
- op1 = operands[1];
- op2 = operands[2];
- t1 = gen_reg_rtx (<MODE>mode);
- t2 = gen_reg_rtx (<MODE>mode);
- dest = gen_lowpart (<MODE>mode, operands[0]);
-
- emit_insn (gen_mul<mode>3 (t1, op1, op2));
- emit_insn (gen_<s>mul<mode>3_highpart (t2, op1, op2));
- emit_insn (gen_vec_interleave_low<mode> (dest, t1, t2));
- DONE;
-})
-
-(define_expand "vec_widen_<s>mult_hi_v8si"
- [(match_operand:V4DI 0 "register_operand" "")
- (any_extend:V4DI (match_operand:V8SI 1 "nonimmediate_operand" ""))
- (match_operand:V8SI 2 "nonimmediate_operand" "")]
- "TARGET_AVX2"
-{
- rtx t1, t2, t3, t4;
-
- t1 = gen_reg_rtx (V4DImode);
- t2 = gen_reg_rtx (V4DImode);
- t3 = gen_reg_rtx (V8SImode);
- t4 = gen_reg_rtx (V8SImode);
- emit_insn (gen_avx2_permv4di_1 (t1, gen_lowpart (V4DImode, operands[1]),
- const0_rtx, const2_rtx,
- const1_rtx, GEN_INT (3)));
- emit_insn (gen_avx2_permv4di_1 (t2, gen_lowpart (V4DImode, operands[2]),
- const0_rtx, const2_rtx,
- const1_rtx, GEN_INT (3)));
- emit_insn (gen_avx2_pshufdv3 (t3, gen_lowpart (V8SImode, t1),
- GEN_INT (2 + (2 << 2) + (3 << 4) + (3 << 6))));
- emit_insn (gen_avx2_pshufdv3 (t4, gen_lowpart (V8SImode, t2),
- GEN_INT (2 + (2 << 2) + (3 << 4) + (3 << 6))));
- emit_insn (gen_avx2_<u>mulv4siv4di3 (operands[0], t3, t4));
- DONE;
-})
-
-(define_expand "vec_widen_<s>mult_lo_v8si"
- [(match_operand:V4DI 0 "register_operand" "")
- (any_extend:V4DI (match_operand:V8SI 1 "nonimmediate_operand" ""))
- (match_operand:V8SI 2 "nonimmediate_operand" "")]
- "TARGET_AVX2"
-{
- rtx t1, t2, t3, t4;
-
- t1 = gen_reg_rtx (V4DImode);
- t2 = gen_reg_rtx (V4DImode);
- t3 = gen_reg_rtx (V8SImode);
- t4 = gen_reg_rtx (V8SImode);
- emit_insn (gen_avx2_permv4di_1 (t1, gen_lowpart (V4DImode, operands[1]),
- const0_rtx, const2_rtx,
- const1_rtx, GEN_INT (3)));
- emit_insn (gen_avx2_permv4di_1 (t2, gen_lowpart (V4DImode, operands[2]),
- const0_rtx, const2_rtx,
- const1_rtx, GEN_INT (3)));
- emit_insn (gen_avx2_pshufdv3 (t3, gen_lowpart (V8SImode, t1),
- GEN_INT (0 + (0 << 2) + (1 << 4) + (1 << 6))));
- emit_insn (gen_avx2_pshufdv3 (t4, gen_lowpart (V8SImode, t2),
- GEN_INT (0 + (0 << 2) + (1 << 4) + (1 << 6))));
- emit_insn (gen_avx2_<u>mulv4siv4di3 (operands[0], t3, t4));
- DONE;
-})
-
-(define_expand "vec_widen_smult_hi_v4si"
- [(match_operand:V2DI 0 "register_operand" "")
- (match_operand:V4SI 1 "register_operand" "")
- (match_operand:V4SI 2 "register_operand" "")]
- "TARGET_SSE4_1"
-{
- rtx op1, op2, t1, t2;
-
- op1 = operands[1];
- op2 = operands[2];
- t1 = gen_reg_rtx (V4SImode);
- t2 = gen_reg_rtx (V4SImode);
-
- if (TARGET_XOP)
- {
- rtx t3 = gen_reg_rtx (V2DImode);
-
- emit_insn (gen_sse2_pshufd_1 (t1, op1, GEN_INT (0), GEN_INT (2),
- GEN_INT (1), GEN_INT (3)));
- emit_insn (gen_sse2_pshufd_1 (t2, op2, GEN_INT (0), GEN_INT (2),
- GEN_INT (1), GEN_INT (3)));
- emit_move_insn (t3, CONST0_RTX (V2DImode));
-
- emit_insn (gen_xop_pmacsdqh (operands[0], t1, t2, t3));
- DONE;
- }
-
- emit_insn (gen_vec_interleave_highv4si (t1, op1, op1));
- emit_insn (gen_vec_interleave_highv4si (t2, op2, op2));
- emit_insn (gen_sse4_1_mulv2siv2di3 (operands[0], t1, t2));
- DONE;
-})
-
-(define_expand "vec_widen_smult_lo_v4si"
- [(match_operand:V2DI 0 "register_operand" "")
- (match_operand:V4SI 1 "register_operand" "")
- (match_operand:V4SI 2 "register_operand" "")]
- "TARGET_SSE4_1"
-{
- rtx op1, op2, t1, t2;
-
- op1 = operands[1];
- op2 = operands[2];
- t1 = gen_reg_rtx (V4SImode);
- t2 = gen_reg_rtx (V4SImode);
-
- if (TARGET_XOP)
- {
- rtx t3 = gen_reg_rtx (V2DImode);
-
- emit_insn (gen_sse2_pshufd_1 (t1, op1, GEN_INT (0), GEN_INT (2),
- GEN_INT (1), GEN_INT (3)));
- emit_insn (gen_sse2_pshufd_1 (t2, op2, GEN_INT (0), GEN_INT (2),
- GEN_INT (1), GEN_INT (3)));
- emit_move_insn (t3, CONST0_RTX (V2DImode));
-
- emit_insn (gen_xop_pmacsdql (operands[0], t1, t2, t3));
- DONE;
- }
-
- emit_insn (gen_vec_interleave_lowv4si (t1, op1, op1));
- emit_insn (gen_vec_interleave_lowv4si (t2, op2, op2));
- emit_insn (gen_sse4_1_mulv2siv2di3 (operands[0], t1, t2));
+ ix86_expand_mul_widen_hilo (operands[0], operands[1], operands[2],
+ <u_bool>, false);
DONE;
})
-(define_expand "vec_widen_umult_hi_v4si"
- [(match_operand:V2DI 0 "register_operand" "")
- (match_operand:V4SI 1 "register_operand" "")
- (match_operand:V4SI 2 "register_operand" "")]
+;; Most widen_<s>mult_even_<mode> can be handled directly from other
+;; named patterns, but signed V4SI needs special help for plain SSE2.
+(define_expand "vec_widen_smult_even_v4si"
+ [(match_operand:V2DI 0 "register_operand")
+ (match_operand:V4SI 1 "register_operand")
+ (match_operand:V4SI 2 "register_operand")]
"TARGET_SSE2"
{
- rtx op1, op2, t1, t2;
-
- op1 = operands[1];
- op2 = operands[2];
- t1 = gen_reg_rtx (V4SImode);
- t2 = gen_reg_rtx (V4SImode);
-
- emit_insn (gen_vec_interleave_highv4si (t1, op1, op1));
- emit_insn (gen_vec_interleave_highv4si (t2, op2, op2));
- emit_insn (gen_sse2_umulv2siv2di3 (operands[0], t1, t2));
+ ix86_expand_mul_widen_evenodd (operands[0], operands[1], operands[2],
+ false, false);
DONE;
})
-(define_expand "vec_widen_umult_lo_v4si"
- [(match_operand:V2DI 0 "register_operand" "")
- (match_operand:V4SI 1 "register_operand" "")
- (match_operand:V4SI 2 "register_operand" "")]
+(define_expand "vec_widen_<s>mult_odd_<mode>"
+ [(match_operand:<sseunpackmode> 0 "register_operand")
+ (any_extend:<sseunpackmode>
+ (match_operand:VI4_AVX2 1 "register_operand"))
+ (match_operand:VI4_AVX2 2 "register_operand")]
"TARGET_SSE2"
{
- rtx op1, op2, t1, t2;
-
- op1 = operands[1];
- op2 = operands[2];
- t1 = gen_reg_rtx (V4SImode);
- t2 = gen_reg_rtx (V4SImode);
-
- emit_insn (gen_vec_interleave_lowv4si (t1, op1, op1));
- emit_insn (gen_vec_interleave_lowv4si (t2, op2, op2));
- emit_insn (gen_sse2_umulv2siv2di3 (operands[0], t1, t2));
+ ix86_expand_mul_widen_evenodd (operands[0], operands[1], operands[2],
+ <u_bool>, true);
DONE;
})
(define_expand "sdot_prod<mode>"
- [(match_operand:<sseunpackmode> 0 "register_operand" "")
- (match_operand:VI2_AVX2 1 "register_operand" "")
- (match_operand:VI2_AVX2 2 "register_operand" "")
- (match_operand:<sseunpackmode> 3 "register_operand" "")]
+ [(match_operand:<sseunpackmode> 0 "register_operand")
+ (match_operand:VI2_AVX2 1 "register_operand")
+ (match_operand:VI2_AVX2 2 "register_operand")
+ (match_operand:<sseunpackmode> 3 "register_operand")]
"TARGET_SSE2"
{
rtx t = gen_reg_rtx (<sseunpackmode>mode);
DONE;
})
-(define_code_attr sse2_sse4_1
- [(zero_extend "sse2") (sign_extend "sse4_1")])
-
-(define_expand "<s>dot_prodv4si"
- [(match_operand:V2DI 0 "register_operand" "")
- (any_extend:V2DI (match_operand:V4SI 1 "register_operand" ""))
- (match_operand:V4SI 2 "register_operand" "")
- (match_operand:V2DI 3 "register_operand" "")]
- "<CODE> == ZERO_EXTEND ? TARGET_SSE2 : TARGET_SSE4_1"
-{
- rtx t1, t2, t3, t4;
-
- t1 = gen_reg_rtx (V2DImode);
- emit_insn (gen_<sse2_sse4_1>_<u>mulv2siv2di3 (t1, operands[1], operands[2]));
- emit_insn (gen_addv2di3 (t1, t1, operands[3]));
-
- t2 = gen_reg_rtx (V4SImode);
- t3 = gen_reg_rtx (V4SImode);
- emit_insn (gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, t2),
- gen_lowpart (V1TImode, operands[1]),
- GEN_INT (32)));
- emit_insn (gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, t3),
- gen_lowpart (V1TImode, operands[2]),
- GEN_INT (32)));
-
- t4 = gen_reg_rtx (V2DImode);
- emit_insn (gen_<sse2_sse4_1>_<u>mulv2siv2di3 (t4, t2, t3));
-
- emit_insn (gen_addv2di3 (operands[0], t1, t4));
- DONE;
-})
-
-(define_expand "<s>dot_prodv8si"
- [(match_operand:V4DI 0 "register_operand" "")
- (any_extend:V4DI (match_operand:V8SI 1 "register_operand" ""))
- (match_operand:V8SI 2 "register_operand" "")
- (match_operand:V4DI 3 "register_operand" "")]
- "TARGET_AVX2"
+;; Normally we use widen_mul_even/odd, but combine can't quite get it all
+;; back together when madd is available.
+(define_expand "sdot_prodv4si"
+ [(match_operand:V2DI 0 "register_operand")
+ (match_operand:V4SI 1 "register_operand")
+ (match_operand:V4SI 2 "register_operand")
+ (match_operand:V2DI 3 "register_operand")]
+ "TARGET_XOP"
{
- rtx t1, t2, t3, t4;
-
- t1 = gen_reg_rtx (V4DImode);
- emit_insn (gen_avx2_<u>mulv4siv4di3 (t1, operands[1], operands[2]));
- emit_insn (gen_addv4di3 (t1, t1, operands[3]));
-
- t2 = gen_reg_rtx (V8SImode);
- t3 = gen_reg_rtx (V8SImode);
- emit_insn (gen_avx2_lshrv2ti3 (gen_lowpart (V2TImode, t2),
- gen_lowpart (V2TImode, operands[1]),
- GEN_INT (32)));
- emit_insn (gen_avx2_lshrv2ti3 (gen_lowpart (V2TImode, t3),
- gen_lowpart (V2TImode, operands[2]),
- GEN_INT (32)));
-
- t4 = gen_reg_rtx (V4DImode);
- emit_insn (gen_avx2_<u>mulv4siv4di3 (t4, t2, t3));
-
- emit_insn (gen_addv4di3 (operands[0], t1, t4));
+ rtx t = gen_reg_rtx (V2DImode);
+ emit_insn (gen_xop_pmacsdqh (t, operands[1], operands[2], operands[3]));
+ emit_insn (gen_xop_pmacsdql (operands[0], operands[1], operands[2], t));
DONE;
})
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseishft")
(set (attr "length_immediate")
- (if_then_else (match_operand 2 "const_int_operand" "")
+ (if_then_else (match_operand 2 "const_int_operand")
(const_string "1")
(const_string "0")))
(set_attr "prefix_data16" "1,*")
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseishft")
(set (attr "length_immediate")
- (if_then_else (match_operand 2 "const_int_operand" "")
+ (if_then_else (match_operand 2 "const_int_operand")
(const_string "1")
(const_string "0")))
(set_attr "prefix_data16" "1,*")
(set_attr "mode" "<sseinsnmode>")])
(define_expand "vec_shl_<mode>"
- [(set (match_operand:VI_128 0 "register_operand" "")
+ [(set (match_operand:VI_128 0 "register_operand")
(ashift:V1TI
- (match_operand:VI_128 1 "register_operand" "")
- (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))]
+ (match_operand:VI_128 1 "register_operand")
+ (match_operand:SI 2 "const_0_to_255_mul_8_operand")))]
"TARGET_SSE2"
{
operands[0] = gen_lowpart (V1TImode, operands[0]);
(set_attr "mode" "<sseinsnmode>")])
(define_expand "vec_shr_<mode>"
- [(set (match_operand:VI_128 0 "register_operand" "")
+ [(set (match_operand:VI_128 0 "register_operand")
(lshiftrt:V1TI
- (match_operand:VI_128 1 "register_operand" "")
- (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))]
+ (match_operand:VI_128 1 "register_operand")
+ (match_operand:SI 2 "const_0_to_255_mul_8_operand")))]
"TARGET_SSE2"
{
operands[0] = gen_lowpart (V1TImode, operands[0]);
(define_expand "<code><mode>3"
- [(set (match_operand:VI124_256 0 "register_operand" "")
+ [(set (match_operand:VI124_256 0 "register_operand")
(maxmin:VI124_256
- (match_operand:VI124_256 1 "nonimmediate_operand" "")
- (match_operand:VI124_256 2 "nonimmediate_operand" "")))]
+ (match_operand:VI124_256 1 "nonimmediate_operand")
+ (match_operand:VI124_256 2 "nonimmediate_operand")))]
"TARGET_AVX2"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(set_attr "mode" "OI")])
(define_expand "<code><mode>3"
- [(set (match_operand:VI8_AVX2 0 "register_operand" "")
+ [(set (match_operand:VI8_AVX2 0 "register_operand")
(maxmin:VI8_AVX2
- (match_operand:VI8_AVX2 1 "register_operand" "")
- (match_operand:VI8_AVX2 2 "register_operand" "")))]
+ (match_operand:VI8_AVX2 1 "register_operand")
+ (match_operand:VI8_AVX2 2 "register_operand")))]
"TARGET_SSE4_2"
{
enum rtx_code code;
})
(define_expand "<code><mode>3"
- [(set (match_operand:VI124_128 0 "register_operand" "")
+ [(set (match_operand:VI124_128 0 "register_operand")
(smaxmin:VI124_128
- (match_operand:VI124_128 1 "nonimmediate_operand" "")
- (match_operand:VI124_128 2 "nonimmediate_operand" "")))]
+ (match_operand:VI124_128 1 "nonimmediate_operand")
+ (match_operand:VI124_128 2 "nonimmediate_operand")))]
"TARGET_SSE2"
{
if (TARGET_SSE4_1 || <MODE>mode == V8HImode)
(set_attr "mode" "TI")])
(define_expand "<code><mode>3"
- [(set (match_operand:VI124_128 0 "register_operand" "")
+ [(set (match_operand:VI124_128 0 "register_operand")
(umaxmin:VI124_128
- (match_operand:VI124_128 1 "nonimmediate_operand" "")
- (match_operand:VI124_128 2 "nonimmediate_operand" "")))]
+ (match_operand:VI124_128 1 "nonimmediate_operand")
+ (match_operand:VI124_128 2 "nonimmediate_operand")))]
"TARGET_SSE2"
{
if (TARGET_SSE4_1 || <MODE>mode == V16QImode)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "avx2_eq<mode>3"
- [(set (match_operand:VI_256 0 "register_operand" "")
+ [(set (match_operand:VI_256 0 "register_operand")
(eq:VI_256
- (match_operand:VI_256 1 "nonimmediate_operand" "")
- (match_operand:VI_256 2 "nonimmediate_operand" "")))]
+ (match_operand:VI_256 1 "nonimmediate_operand")
+ (match_operand:VI_256 2 "nonimmediate_operand")))]
"TARGET_AVX2"
"ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
(set_attr "mode" "TI")])
(define_expand "sse2_eq<mode>3"
- [(set (match_operand:VI124_128 0 "register_operand" "")
+ [(set (match_operand:VI124_128 0 "register_operand")
(eq:VI124_128
- (match_operand:VI124_128 1 "nonimmediate_operand" "")
- (match_operand:VI124_128 2 "nonimmediate_operand" "")))]
+ (match_operand:VI124_128 1 "nonimmediate_operand")
+ (match_operand:VI124_128 2 "nonimmediate_operand")))]
"TARGET_SSE2 && !TARGET_XOP "
"ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
(define_expand "sse4_1_eqv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "")
+ [(set (match_operand:V2DI 0 "register_operand")
(eq:V2DI
- (match_operand:V2DI 1 "nonimmediate_operand" "")
- (match_operand:V2DI 2 "nonimmediate_operand" "")))]
+ (match_operand:V2DI 1 "nonimmediate_operand")
+ (match_operand:V2DI 2 "nonimmediate_operand")))]
"TARGET_SSE4_1"
"ix86_fixup_binary_operands_no_copy (EQ, V2DImode, operands);")
(set_attr "mode" "TI")])
(define_expand "vcond<V_256:mode><VI_256:mode>"
- [(set (match_operand:V_256 0 "register_operand" "")
+ [(set (match_operand:V_256 0 "register_operand")
(if_then_else:V_256
(match_operator 3 ""
- [(match_operand:VI_256 4 "nonimmediate_operand" "")
- (match_operand:VI_256 5 "general_operand" "")])
- (match_operand:V_256 1 "" "")
- (match_operand:V_256 2 "" "")))]
+ [(match_operand:VI_256 4 "nonimmediate_operand")
+ (match_operand:VI_256 5 "general_operand")])
+ (match_operand:V_256 1)
+ (match_operand:V_256 2)))]
"TARGET_AVX2
&& (GET_MODE_NUNITS (<V_256:MODE>mode)
== GET_MODE_NUNITS (<VI_256:MODE>mode))"
})
(define_expand "vcond<V_128:mode><VI124_128:mode>"
- [(set (match_operand:V_128 0 "register_operand" "")
+ [(set (match_operand:V_128 0 "register_operand")
(if_then_else:V_128
(match_operator 3 ""
- [(match_operand:VI124_128 4 "nonimmediate_operand" "")
- (match_operand:VI124_128 5 "general_operand" "")])
- (match_operand:V_128 1 "" "")
- (match_operand:V_128 2 "" "")))]
+ [(match_operand:VI124_128 4 "nonimmediate_operand")
+ (match_operand:VI124_128 5 "general_operand")])
+ (match_operand:V_128 1)
+ (match_operand:V_128 2)))]
"TARGET_SSE2
&& (GET_MODE_NUNITS (<V_128:MODE>mode)
== GET_MODE_NUNITS (<VI124_128:MODE>mode))"
})
(define_expand "vcond<VI8F_128:mode>v2di"
- [(set (match_operand:VI8F_128 0 "register_operand" "")
+ [(set (match_operand:VI8F_128 0 "register_operand")
(if_then_else:VI8F_128
(match_operator 3 ""
- [(match_operand:V2DI 4 "nonimmediate_operand" "")
- (match_operand:V2DI 5 "general_operand" "")])
- (match_operand:VI8F_128 1 "" "")
- (match_operand:VI8F_128 2 "" "")))]
+ [(match_operand:V2DI 4 "nonimmediate_operand")
+ (match_operand:V2DI 5 "general_operand")])
+ (match_operand:VI8F_128 1)
+ (match_operand:VI8F_128 2)))]
"TARGET_SSE4_2"
{
bool ok = ix86_expand_int_vcond (operands);
})
(define_expand "vcondu<V_256:mode><VI_256:mode>"
- [(set (match_operand:V_256 0 "register_operand" "")
+ [(set (match_operand:V_256 0 "register_operand")
(if_then_else:V_256
(match_operator 3 ""
- [(match_operand:VI_256 4 "nonimmediate_operand" "")
- (match_operand:VI_256 5 "nonimmediate_operand" "")])
- (match_operand:V_256 1 "general_operand" "")
- (match_operand:V_256 2 "general_operand" "")))]
+ [(match_operand:VI_256 4 "nonimmediate_operand")
+ (match_operand:VI_256 5 "nonimmediate_operand")])
+ (match_operand:V_256 1 "general_operand")
+ (match_operand:V_256 2 "general_operand")))]
"TARGET_AVX2
&& (GET_MODE_NUNITS (<V_256:MODE>mode)
== GET_MODE_NUNITS (<VI_256:MODE>mode))"
})
(define_expand "vcondu<V_128:mode><VI124_128:mode>"
- [(set (match_operand:V_128 0 "register_operand" "")
+ [(set (match_operand:V_128 0 "register_operand")
(if_then_else:V_128
(match_operator 3 ""
- [(match_operand:VI124_128 4 "nonimmediate_operand" "")
- (match_operand:VI124_128 5 "nonimmediate_operand" "")])
- (match_operand:V_128 1 "general_operand" "")
- (match_operand:V_128 2 "general_operand" "")))]
+ [(match_operand:VI124_128 4 "nonimmediate_operand")
+ (match_operand:VI124_128 5 "nonimmediate_operand")])
+ (match_operand:V_128 1 "general_operand")
+ (match_operand:V_128 2 "general_operand")))]
"TARGET_SSE2
&& (GET_MODE_NUNITS (<V_128:MODE>mode)
== GET_MODE_NUNITS (<VI124_128:MODE>mode))"
})
(define_expand "vcondu<VI8F_128:mode>v2di"
- [(set (match_operand:VI8F_128 0 "register_operand" "")
+ [(set (match_operand:VI8F_128 0 "register_operand")
(if_then_else:VI8F_128
(match_operator 3 ""
- [(match_operand:V2DI 4 "nonimmediate_operand" "")
- (match_operand:V2DI 5 "nonimmediate_operand" "")])
- (match_operand:VI8F_128 1 "general_operand" "")
- (match_operand:VI8F_128 2 "general_operand" "")))]
+ [(match_operand:V2DI 4 "nonimmediate_operand")
+ (match_operand:V2DI 5 "nonimmediate_operand")])
+ (match_operand:VI8F_128 1 "general_operand")
+ (match_operand:VI8F_128 2 "general_operand")))]
"TARGET_SSE4_2"
{
bool ok = ix86_expand_int_vcond (operands);
(V8SF "TARGET_AVX2") (V4DF "TARGET_AVX2")])
(define_expand "vec_perm<mode>"
- [(match_operand:VEC_PERM_AVX2 0 "register_operand" "")
- (match_operand:VEC_PERM_AVX2 1 "register_operand" "")
- (match_operand:VEC_PERM_AVX2 2 "register_operand" "")
- (match_operand:<sseintvecmode> 3 "register_operand" "")]
+ [(match_operand:VEC_PERM_AVX2 0 "register_operand")
+ (match_operand:VEC_PERM_AVX2 1 "register_operand")
+ (match_operand:VEC_PERM_AVX2 2 "register_operand")
+ (match_operand:<sseintvecmode> 3 "register_operand")]
"TARGET_SSSE3 || TARGET_AVX || TARGET_XOP"
{
ix86_expand_vec_perm (operands);
(V32QI "TARGET_AVX2") (V16HI "TARGET_AVX2")])
(define_expand "vec_perm_const<mode>"
- [(match_operand:VEC_PERM_CONST 0 "register_operand" "")
- (match_operand:VEC_PERM_CONST 1 "register_operand" "")
- (match_operand:VEC_PERM_CONST 2 "register_operand" "")
- (match_operand:<sseintvecmode> 3 "" "")]
+ [(match_operand:VEC_PERM_CONST 0 "register_operand")
+ (match_operand:VEC_PERM_CONST 1 "register_operand")
+ (match_operand:VEC_PERM_CONST 2 "register_operand")
+ (match_operand:<sseintvecmode> 3)]
""
{
if (ix86_expand_vec_perm_const (operands))
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "one_cmpl<mode>2"
- [(set (match_operand:VI 0 "register_operand" "")
- (xor:VI (match_operand:VI 1 "nonimmediate_operand" "")
+ [(set (match_operand:VI 0 "register_operand")
+ (xor:VI (match_operand:VI 1 "nonimmediate_operand")
(match_dup 2)))]
"TARGET_SSE"
{
})
(define_expand "<sse2_avx2>_andnot<mode>3"
- [(set (match_operand:VI_AVX2 0 "register_operand" "")
+ [(set (match_operand:VI_AVX2 0 "register_operand")
(and:VI_AVX2
- (not:VI_AVX2 (match_operand:VI_AVX2 1 "register_operand" ""))
- (match_operand:VI_AVX2 2 "nonimmediate_operand" "")))]
+ (not:VI_AVX2 (match_operand:VI_AVX2 1 "register_operand"))
+ (match_operand:VI_AVX2 2 "nonimmediate_operand")))]
"TARGET_SSE2")
(define_insn "*andnot<mode>3"
(const_string "*")))
(set_attr "prefix" "orig,vex")
(set (attr "mode")
- (cond [(and (not (match_test "TARGET_AVX2"))
- (match_test "GET_MODE_SIZE (<MODE>mode) > 16"))
- (const_string "V8SF")
- (not (match_test "TARGET_SSE2"))
- (const_string "V4SF")
- ]
- (const_string "<sseinsnmode>")))])
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "<ssePSmode>")
+ (match_test "TARGET_AVX2")
+ (const_string "<sseinsnmode>")
+ (match_test "TARGET_AVX")
+ (if_then_else
+ (match_test "GET_MODE_SIZE (<MODE>mode) > 16")
+ (const_string "V8SF")
+ (const_string "<sseinsnmode>"))
+ (ior (not (match_test "TARGET_SSE2"))
+ (match_test "optimize_function_for_size_p (cfun)"))
+ (const_string "V4SF")
+ ]
+ (const_string "<sseinsnmode>")))])
(define_expand "<code><mode>3"
- [(set (match_operand:VI 0 "register_operand" "")
+ [(set (match_operand:VI 0 "register_operand")
(any_logic:VI
- (match_operand:VI 1 "nonimmediate_operand" "")
- (match_operand:VI 2 "nonimmediate_operand" "")))]
+ (match_operand:VI 1 "nonimmediate_or_const_vector_operand")
+ (match_operand:VI 2 "nonimmediate_or_const_vector_operand")))]
"TARGET_SSE"
- "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
+{
+ ix86_expand_vector_logical_operator (<CODE>, <MODE>mode, operands);
+ DONE;
+})
(define_insn "*<code><mode>3"
[(set (match_operand:VI 0 "register_operand" "=x,x")
(const_string "*")))
(set_attr "prefix" "orig,vex")
(set (attr "mode")
- (cond [(and (not (match_test "TARGET_AVX2"))
- (match_test "GET_MODE_SIZE (<MODE>mode) > 16"))
- (const_string "V8SF")
- (not (match_test "TARGET_SSE2"))
- (const_string "V4SF")
- ]
- (const_string "<sseinsnmode>")))])
-
-(define_insn "*andnottf3"
- [(set (match_operand:TF 0 "register_operand" "=x,x")
- (and:TF
- (not:TF (match_operand:TF 1 "register_operand" "0,x"))
- (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))]
- "TARGET_SSE2"
- "@
- pandn\t{%2, %0|%0, %2}
- vpandn\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "isa" "noavx,avx")
- (set_attr "type" "sselog")
- (set_attr "prefix_data16" "1,*")
- (set_attr "prefix" "orig,vex")
- (set_attr "mode" "TI")])
-
-(define_expand "<code>tf3"
- [(set (match_operand:TF 0 "register_operand" "")
- (any_logic:TF
- (match_operand:TF 1 "nonimmediate_operand" "")
- (match_operand:TF 2 "nonimmediate_operand" "")))]
- "TARGET_SSE2"
- "ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);")
-
-(define_insn "*<code>tf3"
- [(set (match_operand:TF 0 "register_operand" "=x,x")
- (any_logic:TF
- (match_operand:TF 1 "nonimmediate_operand" "%0,x")
- (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))]
- "TARGET_SSE2
- && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
- "@
- p<logic>\t{%2, %0|%0, %2}
- vp<logic>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "isa" "noavx,avx")
- (set_attr "type" "sselog")
- (set_attr "prefix_data16" "1,*")
- (set_attr "prefix" "orig,vex")
- (set_attr "mode" "TI")])
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "<ssePSmode>")
+ (match_test "TARGET_AVX2")
+ (const_string "<sseinsnmode>")
+ (match_test "TARGET_AVX")
+ (if_then_else
+ (match_test "GET_MODE_SIZE (<MODE>mode) > 16")
+ (const_string "V8SF")
+ (const_string "<sseinsnmode>"))
+ (ior (not (match_test "TARGET_SSE2"))
+ (match_test "optimize_function_for_size_p (cfun)"))
+ (const_string "V4SF")
+ ]
+ (const_string "<sseinsnmode>")))])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "vec_pack_trunc_<mode>"
- [(match_operand:<ssepackmode> 0 "register_operand" "")
- (match_operand:VI248_AVX2 1 "register_operand" "")
- (match_operand:VI248_AVX2 2 "register_operand" "")]
+ [(match_operand:<ssepackmode> 0 "register_operand")
+ (match_operand:VI248_AVX2 1 "register_operand")
+ (match_operand:VI248_AVX2 2 "register_operand")]
"TARGET_SSE2"
{
rtx op1 = gen_lowpart (<ssepackmode>mode, operands[1]);
rtx t2 = gen_reg_rtx (<MODE>mode);
emit_insn (gen_avx2_interleave_low<mode> (t1, operands[1], operands[2]));
emit_insn (gen_avx2_interleave_high<mode> (t2, operands[1], operands[2]));
- emit_insn (gen_avx2_permv2ti (gen_lowpart (V4DImode, operands[0]),
- gen_lowpart (V4DImode, t1),
- gen_lowpart (V4DImode, t2), GEN_INT (1 + (3 << 4))));
+ emit_insn (gen_avx2_permv2ti
+ (gen_lowpart (V4DImode, operands[0]),
+ gen_lowpart (V4DImode, t1),
+ gen_lowpart (V4DImode, t2), GEN_INT (1 + (3 << 4))));
DONE;
})
rtx t2 = gen_reg_rtx (<MODE>mode);
emit_insn (gen_avx2_interleave_low<mode> (t1, operands[1], operands[2]));
emit_insn (gen_avx2_interleave_high<mode> (t2, operands[1], operands[2]));
- emit_insn (gen_avx2_permv2ti (gen_lowpart (V4DImode, operands[0]),
- gen_lowpart (V4DImode, t1),
- gen_lowpart (V4DImode, t2), GEN_INT (0 + (2 << 4))));
+ emit_insn (gen_avx2_permv2ti
+ (gen_lowpart (V4DImode, operands[0]),
+ gen_lowpart (V4DImode, t1),
+ gen_lowpart (V4DImode, t2), GEN_INT (0 + (2 << 4))));
DONE;
})
(vec_duplicate:PINSR_MODE
(match_operand:<ssescalarmode> 2 "nonimmediate_operand" "r,m,r,m"))
(match_operand:PINSR_MODE 1 "register_operand" "0,0,x,x")
- (match_operand:SI 3 "const_int_operand" "")))]
+ (match_operand:SI 3 "const_int_operand")))]
"TARGET_SSE2
&& ((unsigned) exact_log2 (INTVAL (operands[3]))
< GET_MODE_NUNITS (<MODE>mode))"
(set_attr "mode" "TI")])
(define_expand "avx2_pshufdv3"
- [(match_operand:V8SI 0 "register_operand" "")
- (match_operand:V8SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_0_to_255_operand" "")]
+ [(match_operand:V8SI 0 "register_operand")
+ (match_operand:V8SI 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_0_to_255_operand")]
"TARGET_AVX2"
{
int mask = INTVAL (operands[2]);
[(set (match_operand:V8SI 0 "register_operand" "=x")
(vec_select:V8SI
(match_operand:V8SI 1 "nonimmediate_operand" "xm")
- (parallel [(match_operand 2 "const_0_to_3_operand" "")
- (match_operand 3 "const_0_to_3_operand" "")
- (match_operand 4 "const_0_to_3_operand" "")
- (match_operand 5 "const_0_to_3_operand" "")
- (match_operand 6 "const_4_to_7_operand" "")
- (match_operand 7 "const_4_to_7_operand" "")
- (match_operand 8 "const_4_to_7_operand" "")
- (match_operand 9 "const_4_to_7_operand" "")])))]
+ (parallel [(match_operand 2 "const_0_to_3_operand")
+ (match_operand 3 "const_0_to_3_operand")
+ (match_operand 4 "const_0_to_3_operand")
+ (match_operand 5 "const_0_to_3_operand")
+ (match_operand 6 "const_4_to_7_operand")
+ (match_operand 7 "const_4_to_7_operand")
+ (match_operand 8 "const_4_to_7_operand")
+ (match_operand 9 "const_4_to_7_operand")])))]
"TARGET_AVX2
&& INTVAL (operands[2]) + 4 == INTVAL (operands[6])
&& INTVAL (operands[3]) + 4 == INTVAL (operands[7])
(set_attr "mode" "OI")])
(define_expand "sse2_pshufd"
- [(match_operand:V4SI 0 "register_operand" "")
- (match_operand:V4SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_int_operand" "")]
+ [(match_operand:V4SI 0 "register_operand")
+ (match_operand:V4SI 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_int_operand")]
"TARGET_SSE2"
{
int mask = INTVAL (operands[2]);
[(set (match_operand:V4SI 0 "register_operand" "=x")
(vec_select:V4SI
(match_operand:V4SI 1 "nonimmediate_operand" "xm")
- (parallel [(match_operand 2 "const_0_to_3_operand" "")
- (match_operand 3 "const_0_to_3_operand" "")
- (match_operand 4 "const_0_to_3_operand" "")
- (match_operand 5 "const_0_to_3_operand" "")])))]
+ (parallel [(match_operand 2 "const_0_to_3_operand")
+ (match_operand 3 "const_0_to_3_operand")
+ (match_operand 4 "const_0_to_3_operand")
+ (match_operand 5 "const_0_to_3_operand")])))]
"TARGET_SSE2"
{
int mask = 0;
(set_attr "mode" "TI")])
(define_expand "avx2_pshuflwv3"
- [(match_operand:V16HI 0 "register_operand" "")
- (match_operand:V16HI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_0_to_255_operand" "")]
+ [(match_operand:V16HI 0 "register_operand")
+ (match_operand:V16HI 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_0_to_255_operand")]
"TARGET_AVX2"
{
int mask = INTVAL (operands[2]);
[(set (match_operand:V16HI 0 "register_operand" "=x")
(vec_select:V16HI
(match_operand:V16HI 1 "nonimmediate_operand" "xm")
- (parallel [(match_operand 2 "const_0_to_3_operand" "")
- (match_operand 3 "const_0_to_3_operand" "")
- (match_operand 4 "const_0_to_3_operand" "")
- (match_operand 5 "const_0_to_3_operand" "")
+ (parallel [(match_operand 2 "const_0_to_3_operand")
+ (match_operand 3 "const_0_to_3_operand")
+ (match_operand 4 "const_0_to_3_operand")
+ (match_operand 5 "const_0_to_3_operand")
(const_int 4)
(const_int 5)
(const_int 6)
(const_int 7)
- (match_operand 6 "const_8_to_11_operand" "")
- (match_operand 7 "const_8_to_11_operand" "")
- (match_operand 8 "const_8_to_11_operand" "")
- (match_operand 9 "const_8_to_11_operand" "")
+ (match_operand 6 "const_8_to_11_operand")
+ (match_operand 7 "const_8_to_11_operand")
+ (match_operand 8 "const_8_to_11_operand")
+ (match_operand 9 "const_8_to_11_operand")
(const_int 12)
(const_int 13)
(const_int 14)
(set_attr "mode" "OI")])
(define_expand "sse2_pshuflw"
- [(match_operand:V8HI 0 "register_operand" "")
- (match_operand:V8HI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_int_operand" "")]
+ [(match_operand:V8HI 0 "register_operand")
+ (match_operand:V8HI 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_int_operand")]
"TARGET_SSE2"
{
int mask = INTVAL (operands[2]);
[(set (match_operand:V8HI 0 "register_operand" "=x")
(vec_select:V8HI
(match_operand:V8HI 1 "nonimmediate_operand" "xm")
- (parallel [(match_operand 2 "const_0_to_3_operand" "")
- (match_operand 3 "const_0_to_3_operand" "")
- (match_operand 4 "const_0_to_3_operand" "")
- (match_operand 5 "const_0_to_3_operand" "")
+ (parallel [(match_operand 2 "const_0_to_3_operand")
+ (match_operand 3 "const_0_to_3_operand")
+ (match_operand 4 "const_0_to_3_operand")
+ (match_operand 5 "const_0_to_3_operand")
(const_int 4)
(const_int 5)
(const_int 6)
(set_attr "mode" "TI")])
(define_expand "avx2_pshufhwv3"
- [(match_operand:V16HI 0 "register_operand" "")
- (match_operand:V16HI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_0_to_255_operand" "")]
+ [(match_operand:V16HI 0 "register_operand")
+ (match_operand:V16HI 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_0_to_255_operand")]
"TARGET_AVX2"
{
int mask = INTVAL (operands[2]);
(const_int 1)
(const_int 2)
(const_int 3)
- (match_operand 2 "const_4_to_7_operand" "")
- (match_operand 3 "const_4_to_7_operand" "")
- (match_operand 4 "const_4_to_7_operand" "")
- (match_operand 5 "const_4_to_7_operand" "")
+ (match_operand 2 "const_4_to_7_operand")
+ (match_operand 3 "const_4_to_7_operand")
+ (match_operand 4 "const_4_to_7_operand")
+ (match_operand 5 "const_4_to_7_operand")
(const_int 8)
(const_int 9)
(const_int 10)
(const_int 11)
- (match_operand 6 "const_12_to_15_operand" "")
- (match_operand 7 "const_12_to_15_operand" "")
- (match_operand 8 "const_12_to_15_operand" "")
- (match_operand 9 "const_12_to_15_operand" "")])))]
+ (match_operand 6 "const_12_to_15_operand")
+ (match_operand 7 "const_12_to_15_operand")
+ (match_operand 8 "const_12_to_15_operand")
+ (match_operand 9 "const_12_to_15_operand")])))]
"TARGET_AVX2
&& INTVAL (operands[2]) + 8 == INTVAL (operands[6])
&& INTVAL (operands[3]) + 8 == INTVAL (operands[7])
(set_attr "mode" "OI")])
(define_expand "sse2_pshufhw"
- [(match_operand:V8HI 0 "register_operand" "")
- (match_operand:V8HI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_int_operand" "")]
+ [(match_operand:V8HI 0 "register_operand")
+ (match_operand:V8HI 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_int_operand")]
"TARGET_SSE2"
{
int mask = INTVAL (operands[2]);
(const_int 1)
(const_int 2)
(const_int 3)
- (match_operand 2 "const_4_to_7_operand" "")
- (match_operand 3 "const_4_to_7_operand" "")
- (match_operand 4 "const_4_to_7_operand" "")
- (match_operand 5 "const_4_to_7_operand" "")])))]
+ (match_operand 2 "const_4_to_7_operand")
+ (match_operand 3 "const_4_to_7_operand")
+ (match_operand 4 "const_4_to_7_operand")
+ (match_operand 5 "const_4_to_7_operand")])))]
"TARGET_SSE2"
{
int mask = 0;
(set_attr "mode" "TI")])
(define_expand "sse2_loadd"
- [(set (match_operand:V4SI 0 "register_operand" "")
+ [(set (match_operand:V4SI 0 "register_operand")
(vec_merge:V4SI
(vec_duplicate:V4SI
- (match_operand:SI 1 "nonimmediate_operand" ""))
+ (match_operand:SI 1 "nonimmediate_operand"))
(match_dup 2)
(const_int 1)))]
"TARGET_SSE"
[(set (match_operand:SI 0 "register_operand" "=r")
(vec_select:SI
(match_operand:V4SI 1 "memory_operand" "o")
- (parallel [(match_operand 2 "const_0_to_3_operand" "")])))]
+ (parallel [(match_operand 2 "const_0_to_3_operand")])))]
""
"#"
"reload_completed"
})
(define_expand "sse_storeq"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ [(set (match_operand:DI 0 "nonimmediate_operand")
(vec_select:DI
- (match_operand:V2DI 1 "register_operand" "")
+ (match_operand:V2DI 1 "register_operand")
(parallel [(const_int 0)])))]
"TARGET_SSE")
"#")
(define_split
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ [(set (match_operand:DI 0 "nonimmediate_operand")
(vec_select:DI
- (match_operand:V2DI 1 "register_operand" "")
+ (match_operand:V2DI 1 "register_operand")
(parallel [(const_int 0)])))]
"TARGET_SSE
&& reload_completed
(set_attr "mode" "TI,TI,TI,TI,V4SF,V2SF,V2SF")])
(define_expand "vec_unpacks_lo_<mode>"
- [(match_operand:<sseunpackmode> 0 "register_operand" "")
- (match_operand:VI124_AVX2 1 "register_operand" "")]
+ [(match_operand:<sseunpackmode> 0 "register_operand")
+ (match_operand:VI124_AVX2 1 "register_operand")]
"TARGET_SSE2"
- "ix86_expand_sse_unpack (operands, false, false); DONE;")
+ "ix86_expand_sse_unpack (operands[0], operands[1], false, false); DONE;")
(define_expand "vec_unpacks_hi_<mode>"
- [(match_operand:<sseunpackmode> 0 "register_operand" "")
- (match_operand:VI124_AVX2 1 "register_operand" "")]
+ [(match_operand:<sseunpackmode> 0 "register_operand")
+ (match_operand:VI124_AVX2 1 "register_operand")]
"TARGET_SSE2"
- "ix86_expand_sse_unpack (operands, false, true); DONE;")
+ "ix86_expand_sse_unpack (operands[0], operands[1], false, true); DONE;")
(define_expand "vec_unpacku_lo_<mode>"
- [(match_operand:<sseunpackmode> 0 "register_operand" "")
- (match_operand:VI124_AVX2 1 "register_operand" "")]
+ [(match_operand:<sseunpackmode> 0 "register_operand")
+ (match_operand:VI124_AVX2 1 "register_operand")]
"TARGET_SSE2"
- "ix86_expand_sse_unpack (operands, true, false); DONE;")
+ "ix86_expand_sse_unpack (operands[0], operands[1], true, false); DONE;")
(define_expand "vec_unpacku_hi_<mode>"
- [(match_operand:<sseunpackmode> 0 "register_operand" "")
- (match_operand:VI124_AVX2 1 "register_operand" "")]
+ [(match_operand:<sseunpackmode> 0 "register_operand")
+ (match_operand:VI124_AVX2 1 "register_operand")]
"TARGET_SSE2"
- "ix86_expand_sse_unpack (operands, true, true); DONE;")
+ "ix86_expand_sse_unpack (operands[0], operands[1], true, true); DONE;")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(define_expand "avx2_uavgv32qi3"
- [(set (match_operand:V32QI 0 "register_operand" "")
- (truncate:V32QI
- (lshiftrt:V32HI
- (plus:V32HI
- (plus:V32HI
- (zero_extend:V32HI
- (match_operand:V32QI 1 "nonimmediate_operand" ""))
- (zero_extend:V32HI
- (match_operand:V32QI 2 "nonimmediate_operand" "")))
- (const_vector:V32QI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
- (const_int 1))))]
- "TARGET_AVX2"
- "ix86_fixup_binary_operands_no_copy (PLUS, V32QImode, operands);")
-
-(define_expand "sse2_uavgv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "")
- (truncate:V16QI
- (lshiftrt:V16HI
- (plus:V16HI
- (plus:V16HI
- (zero_extend:V16HI
- (match_operand:V16QI 1 "nonimmediate_operand" ""))
- (zero_extend:V16HI
- (match_operand:V16QI 2 "nonimmediate_operand" "")))
- (const_vector:V16QI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
- (const_int 1))))]
- "TARGET_SSE2"
- "ix86_fixup_binary_operands_no_copy (PLUS, V16QImode, operands);")
-
-(define_insn "*avx2_uavgv32qi3"
- [(set (match_operand:V32QI 0 "register_operand" "=x")
- (truncate:V32QI
- (lshiftrt:V32HI
- (plus:V32HI
- (plus:V32HI
- (zero_extend:V32HI
- (match_operand:V32QI 1 "nonimmediate_operand" "%x"))
- (zero_extend:V32HI
- (match_operand:V32QI 2 "nonimmediate_operand" "xm")))
- (const_vector:V32QI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
- (const_int 1))))]
- "TARGET_AVX2 && ix86_binary_operator_ok (PLUS, V32QImode, operands)"
- "vpavgb\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix" "vex")
- (set_attr "mode" "OI")])
-
-(define_insn "*sse2_uavgv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=x,x")
- (truncate:V16QI
- (lshiftrt:V16HI
- (plus:V16HI
- (plus:V16HI
- (zero_extend:V16HI
- (match_operand:V16QI 1 "nonimmediate_operand" "%0,x"))
- (zero_extend:V16HI
- (match_operand:V16QI 2 "nonimmediate_operand" "xm,xm")))
- (const_vector:V16QI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
- (const_int 1))))]
- "TARGET_SSE2 && ix86_binary_operator_ok (PLUS, V16QImode, operands)"
- "@
- pavgb\t{%2, %0|%0, %2}
- vpavgb\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "isa" "noavx,avx")
- (set_attr "type" "sseiadd")
- (set_attr "prefix_data16" "1,*")
- (set_attr "prefix" "orig,vex")
- (set_attr "mode" "TI")])
-
-(define_expand "avx2_uavgv16hi3"
- [(set (match_operand:V16HI 0 "register_operand" "")
- (truncate:V16HI
- (lshiftrt:V16SI
- (plus:V16SI
- (plus:V16SI
- (zero_extend:V16SI
- (match_operand:V16HI 1 "nonimmediate_operand" ""))
- (zero_extend:V16SI
- (match_operand:V16HI 2 "nonimmediate_operand" "")))
- (const_vector:V16HI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
- (const_int 1))))]
- "TARGET_AVX2"
- "ix86_fixup_binary_operands_no_copy (PLUS, V16HImode, operands);")
-
-(define_expand "sse2_uavgv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "")
- (truncate:V8HI
- (lshiftrt:V8SI
- (plus:V8SI
- (plus:V8SI
- (zero_extend:V8SI
- (match_operand:V8HI 1 "nonimmediate_operand" ""))
- (zero_extend:V8SI
- (match_operand:V8HI 2 "nonimmediate_operand" "")))
- (const_vector:V8HI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
+(define_expand "<sse2_avx2>_uavg<mode>3"
+ [(set (match_operand:VI12_AVX2 0 "register_operand")
+ (truncate:VI12_AVX2
+ (lshiftrt:<ssedoublemode>
+ (plus:<ssedoublemode>
+ (plus:<ssedoublemode>
+ (zero_extend:<ssedoublemode>
+ (match_operand:VI12_AVX2 1 "nonimmediate_operand"))
+ (zero_extend:<ssedoublemode>
+ (match_operand:VI12_AVX2 2 "nonimmediate_operand")))
+ (match_dup 3))
(const_int 1))))]
"TARGET_SSE2"
- "ix86_fixup_binary_operands_no_copy (PLUS, V8HImode, operands);")
-
-(define_insn "*avx2_uavgv16hi3"
- [(set (match_operand:V16HI 0 "register_operand" "=x")
- (truncate:V16HI
- (lshiftrt:V16SI
- (plus:V16SI
- (plus:V16SI
- (zero_extend:V16SI
- (match_operand:V16HI 1 "nonimmediate_operand" "%x"))
- (zero_extend:V16SI
- (match_operand:V16HI 2 "nonimmediate_operand" "xm")))
- (const_vector:V16HI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
- (const_int 1))))]
- "TARGET_AVX2 && ix86_binary_operator_ok (PLUS, V16HImode, operands)"
- "vpavgw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix" "vex")
- (set_attr "mode" "OI")])
+{
+ operands[3] = CONST1_RTX(<MODE>mode);
+ ix86_fixup_binary_operands_no_copy (PLUS, <MODE>mode, operands);
+})
-(define_insn "*sse2_uavgv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x,x")
- (truncate:V8HI
- (lshiftrt:V8SI
- (plus:V8SI
- (plus:V8SI
- (zero_extend:V8SI
- (match_operand:V8HI 1 "nonimmediate_operand" "%0,x"))
- (zero_extend:V8SI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")))
- (const_vector:V8HI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
+(define_insn "*<sse2_avx2>_uavg<mode>3"
+ [(set (match_operand:VI12_AVX2 0 "register_operand" "=x,x")
+ (truncate:VI12_AVX2
+ (lshiftrt:<ssedoublemode>
+ (plus:<ssedoublemode>
+ (plus:<ssedoublemode>
+ (zero_extend:<ssedoublemode>
+ (match_operand:VI12_AVX2 1 "nonimmediate_operand" "%0,x"))
+ (zero_extend:<ssedoublemode>
+ (match_operand:VI12_AVX2 2 "nonimmediate_operand" "xm,xm")))
+ (match_operand:VI12_AVX2 3 "const1_operand"))
(const_int 1))))]
- "TARGET_SSE2 && ix86_binary_operator_ok (PLUS, V8HImode, operands)"
+ "TARGET_SSE2 && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
"@
- pavgw\t{%2, %0|%0, %2}
- vpavgw\t{%2, %1, %0|%0, %1, %2}"
+ pavg<ssemodesuffix>\t{%2, %0|%0, %2}
+ vpavg<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
(set_attr "prefix_data16" "1,*")
(set_attr "prefix" "orig,vex")
- (set_attr "mode" "TI")])
+ (set_attr "mode" "<sseinsnmode>")])
;; The correct representation for this is absolutely enormous, and
;; surely not generally useful.
(define_insn "<sse2_avx2>_psadbw"
[(set (match_operand:VI8_AVX2 0 "register_operand" "=x,x")
- (unspec:VI8_AVX2 [(match_operand:<ssebytemode> 1 "register_operand" "0,x")
- (match_operand:<ssebytemode> 2 "nonimmediate_operand" "xm,xm")]
- UNSPEC_PSADBW))]
+ (unspec:VI8_AVX2
+ [(match_operand:<ssebytemode> 1 "register_operand" "0,x")
+ (match_operand:<ssebytemode> 2 "nonimmediate_operand" "xm,xm")]
+ UNSPEC_PSADBW))]
"TARGET_SSE2"
"@
psadbw\t{%2, %0|%0, %2}
(set_attr "mode" "SI")])
(define_expand "sse2_maskmovdqu"
- [(set (match_operand:V16QI 0 "memory_operand" "")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
- (match_operand:V16QI 2 "register_operand" "")
+ [(set (match_operand:V16QI 0 "memory_operand")
+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand")
+ (match_operand:V16QI 2 "register_operand")
(match_dup 0)]
UNSPEC_MASKMOV))]
"TARGET_SSE2")
"monitor\t%0, %1, %2"
[(set_attr "length" "3")])
-(define_insn "sse3_monitor64"
- [(unspec_volatile [(match_operand:DI 0 "register_operand" "a")
+(define_insn "sse3_monitor64_<mode>"
+ [(unspec_volatile [(match_operand:P 0 "register_operand" "a")
(match_operand:SI 1 "register_operand" "c")
(match_operand:SI 2 "register_operand" "d")]
UNSPECV_MONITOR)]
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(define_insn "avx2_phaddwv16hi3"
+(define_code_iterator ssse3_plusminus [plus ss_plus minus ss_minus])
+
+(define_insn "avx2_ph<plusminus_mnemonic>wv16hi3"
[(set (match_operand:V16HI 0 "register_operand" "=x")
(vec_concat:V16HI
(vec_concat:V8HI
(vec_concat:V4HI
(vec_concat:V2HI
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI
(match_operand:V16HI 1 "register_operand" "x")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2HI
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
(vec_concat:V4HI
(vec_concat:V2HI
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 8)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 9)])))
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 10)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 11)]))))
(vec_concat:V2HI
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 12)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 13)])))
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 14)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 15)]))))))
(vec_concat:V8HI
(vec_concat:V4HI
(vec_concat:V2HI
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI
(match_operand:V16HI 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
(vec_concat:V2HI
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))
(vec_concat:V4HI
(vec_concat:V2HI
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 8)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 9)])))
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 10)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 11)]))))
(vec_concat:V2HI
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 12)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 13)])))
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 14)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 15)]))))))))]
"TARGET_AVX2"
- "vphaddw\t{%2, %1, %0|%0, %1, %2}"
+ "vph<plusminus_mnemonic>w\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
-(define_insn "ssse3_phaddwv8hi3"
+(define_insn "ssse3_ph<plusminus_mnemonic>wv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x,x")
(vec_concat:V8HI
(vec_concat:V4HI
(vec_concat:V2HI
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI
(match_operand:V8HI 1 "register_operand" "0,x")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2HI
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
(vec_concat:V4HI
(vec_concat:V2HI
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI
(match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
(vec_concat:V2HI
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
"TARGET_SSSE3"
"@
- phaddw\t{%2, %0|%0, %2}
- vphaddw\t{%2, %1, %0|%0, %1, %2}"
+ ph<plusminus_mnemonic>w\t{%2, %0|%0, %2}
+ vph<plusminus_mnemonic>w\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
-(define_insn "ssse3_phaddwv4hi3"
+(define_insn "ssse3_ph<plusminus_mnemonic>wv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
(vec_concat:V4HI
(vec_concat:V2HI
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI
(match_operand:V4HI 1 "register_operand" "0")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2HI
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI
(match_operand:V4HI 2 "nonimmediate_operand" "ym")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (plus:HI
+ (ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
"TARGET_SSSE3"
- "phaddw\t{%2, %0|%0, %2}"
+ "ph<plusminus_mnemonic>w\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1")
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
-(define_insn "avx2_phadddv8si3"
+(define_insn "avx2_ph<plusminus_mnemonic>dv8si3"
[(set (match_operand:V8SI 0 "register_operand" "=x")
(vec_concat:V8SI
(vec_concat:V4SI
(vec_concat:V2SI
- (plus:SI
+ (plusminus:SI
(vec_select:SI
(match_operand:V8SI 1 "register_operand" "x")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
- (plus:SI
+ (plusminus:SI
(vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2SI
- (plus:SI
+ (plusminus:SI
(vec_select:SI (match_dup 1) (parallel [(const_int 4)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 5)])))
- (plus:SI
+ (plusminus:SI
(vec_select:SI (match_dup 1) (parallel [(const_int 6)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 7)])))))
(vec_concat:V4SI
(vec_concat:V2SI
- (plus:SI
+ (plusminus:SI
(vec_select:SI
(match_operand:V8SI 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
- (plus:SI
+ (plusminus:SI
(vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))
(vec_concat:V2SI
- (plus:SI
+ (plusminus:SI
(vec_select:SI (match_dup 2) (parallel [(const_int 4)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 5)])))
- (plus:SI
+ (plusminus:SI
(vec_select:SI (match_dup 2) (parallel [(const_int 6)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 7)])))))))]
"TARGET_AVX2"
- "vphaddd\t{%2, %1, %0|%0, %1, %2}"
+ "vph<plusminus_mnemonic>d\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
-(define_insn "ssse3_phadddv4si3"
+(define_insn "ssse3_ph<plusminus_mnemonic>dv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x,x")
(vec_concat:V4SI
(vec_concat:V2SI
- (plus:SI
+ (plusminus:SI
(vec_select:SI
(match_operand:V4SI 1 "register_operand" "0,x")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
- (plus:SI
+ (plusminus:SI
(vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2SI
- (plus:SI
+ (plusminus:SI
(vec_select:SI
(match_operand:V4SI 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
- (plus:SI
+ (plusminus:SI
(vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
"TARGET_SSSE3"
"@
- phaddd\t{%2, %0|%0, %2}
- vphaddd\t{%2, %1, %0|%0, %1, %2}"
+ ph<plusminus_mnemonic>d\t{%2, %0|%0, %2}
+ vph<plusminus_mnemonic>d\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
-(define_insn "ssse3_phadddv2si3"
+(define_insn "ssse3_ph<plusminus_mnemonic>dv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
(vec_concat:V2SI
- (plus:SI
+ (plusminus:SI
(vec_select:SI
(match_operand:V2SI 1 "register_operand" "0")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
- (plus:SI
+ (plusminus:SI
(vec_select:SI
(match_operand:V2SI 2 "nonimmediate_operand" "ym")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
"TARGET_SSSE3"
- "phaddd\t{%2, %0|%0, %2}"
+ "ph<plusminus_mnemonic>d\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1")
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
-(define_insn "avx2_phaddswv16hi3"
- [(set (match_operand:V16HI 0 "register_operand" "=x")
- (vec_concat:V16HI
- (vec_concat:V8HI
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ss_plus:HI
- (vec_select:HI
- (match_operand:V16HI 1 "register_operand" "x")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (ss_plus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ss_plus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
- (ss_plus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ss_plus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 8)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 9)])))
- (ss_plus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 10)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 11)]))))
- (vec_concat:V2HI
- (ss_plus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 12)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 13)])))
- (ss_plus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 14)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 15)]))))))
- (vec_concat:V8HI
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ss_plus:HI
- (vec_select:HI
- (match_operand:V16HI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (ss_plus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ss_plus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
- (ss_plus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ss_plus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 8)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 9)])))
- (ss_plus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 10)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 11)]))))
- (vec_concat:V2HI
- (ss_plus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 12)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 13)])))
- (ss_plus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 14)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 15)]))))))))]
- "TARGET_AVX2"
- "vphaddsw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "OI")])
-
-(define_insn "ssse3_phaddswv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x,x")
- (vec_concat:V8HI
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ss_plus:HI
- (vec_select:HI
- (match_operand:V8HI 1 "register_operand" "0,x")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (ss_plus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ss_plus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
- (ss_plus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ss_plus:HI
- (vec_select:HI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (ss_plus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ss_plus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
- (ss_plus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
- "TARGET_SSSE3"
- "@
- phaddsw\t{%2, %0|%0, %2}
- vphaddsw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "isa" "noavx,avx")
- (set_attr "type" "sseiadd")
- (set_attr "atom_unit" "complex")
- (set_attr "prefix_data16" "1,*")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "orig,vex")
- (set_attr "mode" "TI")])
-
-(define_insn "ssse3_phaddswv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ss_plus:HI
- (vec_select:HI
- (match_operand:V4HI 1 "register_operand" "0")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (ss_plus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ss_plus:HI
- (vec_select:HI
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (ss_plus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
- "TARGET_SSSE3"
- "phaddsw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "atom_unit" "complex")
- (set_attr "prefix_extra" "1")
- (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
- (set_attr "mode" "DI")])
-
-(define_insn "avx2_phsubwv16hi3"
- [(set (match_operand:V16HI 0 "register_operand" "=x")
- (vec_concat:V16HI
- (vec_concat:V8HI
- (vec_concat:V4HI
- (vec_concat:V2HI
- (minus:HI
- (vec_select:HI
- (match_operand:V16HI 1 "register_operand" "x")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
- (minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
- (vec_concat:V4HI
- (vec_concat:V2HI
- (minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 8)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 9)])))
- (minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 10)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 11)]))))
- (vec_concat:V2HI
- (minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 12)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 13)])))
- (minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 14)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 15)]))))))
- (vec_concat:V8HI
- (vec_concat:V4HI
- (vec_concat:V2HI
- (minus:HI
- (vec_select:HI
- (match_operand:V16HI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
- (minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))
- (vec_concat:V4HI
- (vec_concat:V2HI
- (minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 8)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 9)])))
- (minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 10)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 11)]))))
- (vec_concat:V2HI
- (minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 12)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 13)])))
- (minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 14)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 15)]))))))))]
- "TARGET_AVX2"
- "vphsubw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "OI")])
-
-(define_insn "ssse3_phsubwv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x,x")
- (vec_concat:V8HI
- (vec_concat:V4HI
- (vec_concat:V2HI
- (minus:HI
- (vec_select:HI
- (match_operand:V8HI 1 "register_operand" "0,x")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
- (minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
- (vec_concat:V4HI
- (vec_concat:V2HI
- (minus:HI
- (vec_select:HI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
- (minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
- "TARGET_SSSE3"
- "@
- phsubw\t{%2, %0|%0, %2}
- vphsubw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "isa" "noavx,avx")
- (set_attr "type" "sseiadd")
- (set_attr "atom_unit" "complex")
- (set_attr "prefix_data16" "1,*")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "orig,vex")
- (set_attr "mode" "TI")])
-
-(define_insn "ssse3_phsubwv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (vec_concat:V4HI
- (vec_concat:V2HI
- (minus:HI
- (vec_select:HI
- (match_operand:V4HI 1 "register_operand" "0")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (minus:HI
- (vec_select:HI
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
- "TARGET_SSSE3"
- "phsubw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "atom_unit" "complex")
- (set_attr "prefix_extra" "1")
- (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
- (set_attr "mode" "DI")])
-
-(define_insn "avx2_phsubdv8si3"
- [(set (match_operand:V8SI 0 "register_operand" "=x")
- (vec_concat:V8SI
- (vec_concat:V4SI
- (vec_concat:V2SI
- (minus:SI
- (vec_select:SI
- (match_operand:V8SI 1 "register_operand" "x")
- (parallel [(const_int 0)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
- (minus:SI
- (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2SI
- (minus:SI
- (vec_select:SI (match_dup 1) (parallel [(const_int 4)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 5)])))
- (minus:SI
- (vec_select:SI (match_dup 1) (parallel [(const_int 6)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 7)])))))
- (vec_concat:V4SI
- (vec_concat:V2SI
- (minus:SI
- (vec_select:SI
- (match_operand:V8SI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
- (minus:SI
- (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))
- (vec_concat:V2SI
- (minus:SI
- (vec_select:SI (match_dup 2) (parallel [(const_int 4)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 5)])))
- (minus:SI
- (vec_select:SI (match_dup 2) (parallel [(const_int 6)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 7)])))))))]
- "TARGET_AVX2"
- "vphsubd\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "OI")])
-
-(define_insn "ssse3_phsubdv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=x,x")
- (vec_concat:V4SI
- (vec_concat:V2SI
- (minus:SI
- (vec_select:SI
- (match_operand:V4SI 1 "register_operand" "0,x")
- (parallel [(const_int 0)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
- (minus:SI
- (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2SI
- (minus:SI
- (vec_select:SI
- (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm")
- (parallel [(const_int 0)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
- (minus:SI
- (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
- "TARGET_SSSE3"
- "@
- phsubd\t{%2, %0|%0, %2}
- vphsubd\t{%2, %1, %0|%0, %1, %2}"
-
- [(set_attr "isa" "noavx,avx")
- (set_attr "type" "sseiadd")
- (set_attr "atom_unit" "complex")
- (set_attr "prefix_data16" "1,*")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "orig,vex")
- (set_attr "mode" "TI")])
-
-(define_insn "ssse3_phsubdv2si3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (vec_concat:V2SI
- (minus:SI
- (vec_select:SI
- (match_operand:V2SI 1 "register_operand" "0")
- (parallel [(const_int 0)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
- (minus:SI
- (vec_select:SI
- (match_operand:V2SI 2 "nonimmediate_operand" "ym")
- (parallel [(const_int 0)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
- "TARGET_SSSE3"
- "phsubd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "atom_unit" "complex")
- (set_attr "prefix_extra" "1")
- (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
- (set_attr "mode" "DI")])
-
-(define_insn "avx2_phsubswv16hi3"
- [(set (match_operand:V16HI 0 "register_operand" "=x")
- (vec_concat:V16HI
- (vec_concat:V8HI
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ss_minus:HI
- (vec_select:HI
- (match_operand:V16HI 1 "register_operand" "x")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (ss_minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ss_minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
- (ss_minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ss_minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 8)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 9)])))
- (ss_minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 10)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 11)]))))
- (vec_concat:V2HI
- (ss_minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 12)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 13)])))
- (ss_minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 14)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 15)]))))))
- (vec_concat:V8HI
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ss_minus:HI
- (vec_select:HI
- (match_operand:V16HI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (ss_minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ss_minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
- (ss_minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ss_minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 8)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 9)])))
- (ss_minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 10)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 11)]))))
- (vec_concat:V2HI
- (ss_minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 12)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 13)])))
- (ss_minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 14)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 15)]))))))))]
- "TARGET_AVX2"
- "vphsubsw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "OI")])
-
-(define_insn "ssse3_phsubswv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x,x")
- (vec_concat:V8HI
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ss_minus:HI
- (vec_select:HI
- (match_operand:V8HI 1 "register_operand" "0,x")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (ss_minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ss_minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
- (ss_minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ss_minus:HI
- (vec_select:HI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (ss_minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ss_minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
- (ss_minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
- "TARGET_SSSE3"
- "@
- phsubsw\t{%2, %0|%0, %2}
- vphsubsw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "isa" "noavx,avx")
- (set_attr "type" "sseiadd")
- (set_attr "atom_unit" "complex")
- (set_attr "prefix_data16" "1,*")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "orig,vex")
- (set_attr "mode" "TI")])
-
-(define_insn "ssse3_phsubswv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ss_minus:HI
- (vec_select:HI
- (match_operand:V4HI 1 "register_operand" "0")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (ss_minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ss_minus:HI
- (vec_select:HI
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (ss_minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
- "TARGET_SSSE3"
- "phsubsw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "atom_unit" "complex")
- (set_attr "prefix_extra" "1")
- (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
- (set_attr "mode" "DI")])
-
-(define_insn "avx2_pmaddubsw256"
+(define_insn "avx2_pmaddubsw256"
[(set (match_operand:V16HI 0 "register_operand" "=x")
(ss_plus:V16HI
(mult:V16HI
(zero_extend:V16HI
(vec_select:V16QI
(match_operand:V32QI 1 "register_operand" "x")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)
- (const_int 8)
- (const_int 10)
- (const_int 12)
- (const_int 14)
- (const_int 16)
- (const_int 18)
- (const_int 20)
- (const_int 22)
- (const_int 24)
- (const_int 26)
- (const_int 28)
- (const_int 30)])))
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)
+ (const_int 8) (const_int 10)
+ (const_int 12) (const_int 14)
+ (const_int 16) (const_int 18)
+ (const_int 20) (const_int 22)
+ (const_int 24) (const_int 26)
+ (const_int 28) (const_int 30)])))
(sign_extend:V16HI
(vec_select:V16QI
(match_operand:V32QI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)
- (const_int 8)
- (const_int 10)
- (const_int 12)
- (const_int 14)
- (const_int 16)
- (const_int 18)
- (const_int 20)
- (const_int 22)
- (const_int 24)
- (const_int 26)
- (const_int 28)
- (const_int 30)]))))
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)
+ (const_int 8) (const_int 10)
+ (const_int 12) (const_int 14)
+ (const_int 16) (const_int 18)
+ (const_int 20) (const_int 22)
+ (const_int 24) (const_int 26)
+ (const_int 28) (const_int 30)]))))
(mult:V16HI
(zero_extend:V16HI
(vec_select:V16QI (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)
- (const_int 9)
- (const_int 11)
- (const_int 13)
- (const_int 15)
- (const_int 17)
- (const_int 19)
- (const_int 21)
- (const_int 23)
- (const_int 25)
- (const_int 27)
- (const_int 29)
- (const_int 31)])))
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)
+ (const_int 9) (const_int 11)
+ (const_int 13) (const_int 15)
+ (const_int 17) (const_int 19)
+ (const_int 21) (const_int 23)
+ (const_int 25) (const_int 27)
+ (const_int 29) (const_int 31)])))
(sign_extend:V16HI
(vec_select:V16QI (match_dup 2)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)
- (const_int 9)
- (const_int 11)
- (const_int 13)
- (const_int 15)
- (const_int 17)
- (const_int 19)
- (const_int 21)
- (const_int 23)
- (const_int 25)
- (const_int 27)
- (const_int 29)
- (const_int 31)]))))))]
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)
+ (const_int 9) (const_int 11)
+ (const_int 13) (const_int 15)
+ (const_int 17) (const_int 19)
+ (const_int 21) (const_int 23)
+ (const_int 25) (const_int 27)
+ (const_int 29) (const_int 31)]))))))]
"TARGET_AVX2"
"vpmaddubsw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
(zero_extend:V8HI
(vec_select:V8QI
(match_operand:V16QI 1 "register_operand" "0,x")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)
- (const_int 8)
- (const_int 10)
- (const_int 12)
- (const_int 14)])))
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)
+ (const_int 8) (const_int 10)
+ (const_int 12) (const_int 14)])))
(sign_extend:V8HI
(vec_select:V8QI
(match_operand:V16QI 2 "nonimmediate_operand" "xm,xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)
- (const_int 8)
- (const_int 10)
- (const_int 12)
- (const_int 14)]))))
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)
+ (const_int 8) (const_int 10)
+ (const_int 12) (const_int 14)]))))
(mult:V8HI
(zero_extend:V8HI
(vec_select:V8QI (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)
- (const_int 9)
- (const_int 11)
- (const_int 13)
- (const_int 15)])))
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)
+ (const_int 9) (const_int 11)
+ (const_int 13) (const_int 15)])))
(sign_extend:V8HI
(vec_select:V8QI (match_dup 2)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)
- (const_int 9)
- (const_int 11)
- (const_int 13)
- (const_int 15)]))))))]
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)
+ (const_int 9) (const_int 11)
+ (const_int 13) (const_int 15)]))))))]
"TARGET_SSSE3"
"@
pmaddubsw\t{%2, %0|%0, %2}
(zero_extend:V4HI
(vec_select:V4QI
(match_operand:V8QI 1 "register_operand" "0")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)])))
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)])))
(sign_extend:V4HI
(vec_select:V4QI
(match_operand:V8QI 2 "nonimmediate_operand" "ym")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)]))))
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)]))))
(mult:V4HI
(zero_extend:V4HI
(vec_select:V4QI (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)])))
(sign_extend:V4HI
(vec_select:V4QI (match_dup 2)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)]))))))]
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)]))))))]
"TARGET_SSSE3"
"pmaddubsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
-(define_expand "avx2_umulhrswv16hi3"
- [(set (match_operand:V16HI 0 "register_operand" "")
- (truncate:V16HI
- (lshiftrt:V16SI
- (plus:V16SI
- (lshiftrt:V16SI
- (mult:V16SI
- (sign_extend:V16SI
- (match_operand:V16HI 1 "nonimmediate_operand" ""))
- (sign_extend:V16SI
- (match_operand:V16HI 2 "nonimmediate_operand" "")))
- (const_int 14))
- (const_vector:V16HI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
- (const_int 1))))]
- "TARGET_AVX2"
- "ix86_fixup_binary_operands_no_copy (MULT, V16HImode, operands);")
-
-(define_insn "*avx2_umulhrswv16hi3"
- [(set (match_operand:V16HI 0 "register_operand" "=x")
- (truncate:V16HI
- (lshiftrt:V16SI
- (plus:V16SI
- (lshiftrt:V16SI
- (mult:V16SI
- (sign_extend:V16SI
- (match_operand:V16HI 1 "nonimmediate_operand" "%x"))
- (sign_extend:V16SI
- (match_operand:V16HI 2 "nonimmediate_operand" "xm")))
- (const_int 14))
- (const_vector:V16HI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
- (const_int 1))))]
- "TARGET_AVX2 && ix86_binary_operator_ok (MULT, V16HImode, operands)"
- "vpmulhrsw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseimul")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "OI")])
+(define_mode_iterator PMULHRSW
+ [V4HI V8HI (V16HI "TARGET_AVX2")])
-(define_expand "ssse3_pmulhrswv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "")
- (truncate:V8HI
- (lshiftrt:V8SI
- (plus:V8SI
- (lshiftrt:V8SI
- (mult:V8SI
- (sign_extend:V8SI
- (match_operand:V8HI 1 "nonimmediate_operand" ""))
- (sign_extend:V8SI
- (match_operand:V8HI 2 "nonimmediate_operand" "")))
+(define_expand "<ssse3_avx2>_pmulhrsw<mode>3"
+ [(set (match_operand:PMULHRSW 0 "register_operand")
+ (truncate:PMULHRSW
+ (lshiftrt:<ssedoublemode>
+ (plus:<ssedoublemode>
+ (lshiftrt:<ssedoublemode>
+ (mult:<ssedoublemode>
+ (sign_extend:<ssedoublemode>
+ (match_operand:PMULHRSW 1 "nonimmediate_operand"))
+ (sign_extend:<ssedoublemode>
+ (match_operand:PMULHRSW 2 "nonimmediate_operand")))
(const_int 14))
- (const_vector:V8HI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
+ (match_dup 3))
(const_int 1))))]
- "TARGET_SSSE3"
- "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
+ "TARGET_AVX2"
+{
+ operands[3] = CONST1_RTX(<MODE>mode);
+ ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);
+})
-(define_insn "*ssse3_pmulhrswv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x,x")
- (truncate:V8HI
- (lshiftrt:V8SI
- (plus:V8SI
- (lshiftrt:V8SI
- (mult:V8SI
- (sign_extend:V8SI
- (match_operand:V8HI 1 "nonimmediate_operand" "%0,x"))
- (sign_extend:V8SI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")))
+(define_insn "*<ssse3_avx2>_pmulhrsw<mode>3"
+ [(set (match_operand:VI2_AVX2 0 "register_operand" "=x,x")
+ (truncate:VI2_AVX2
+ (lshiftrt:<ssedoublemode>
+ (plus:<ssedoublemode>
+ (lshiftrt:<ssedoublemode>
+ (mult:<ssedoublemode>
+ (sign_extend:<ssedoublemode>
+ (match_operand:VI2_AVX2 1 "nonimmediate_operand" "%0,x"))
+ (sign_extend:<ssedoublemode>
+ (match_operand:VI2_AVX2 2 "nonimmediate_operand" "xm,xm")))
(const_int 14))
- (const_vector:V8HI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
+ (match_operand:VI2_AVX2 3 "const1_operand"))
(const_int 1))))]
- "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
+ "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
"@
pmulhrsw\t{%2, %0|%0, %2}
vpmulhrsw\t{%2, %1, %0|%0, %1, %2}"
(set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
- (set_attr "mode" "TI")])
-
-(define_expand "ssse3_pmulhrswv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "")
- (truncate:V4HI
- (lshiftrt:V4SI
- (plus:V4SI
- (lshiftrt:V4SI
- (mult:V4SI
- (sign_extend:V4SI
- (match_operand:V4HI 1 "nonimmediate_operand" ""))
- (sign_extend:V4SI
- (match_operand:V4HI 2 "nonimmediate_operand" "")))
- (const_int 14))
- (const_vector:V4HI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
- (const_int 1))))]
- "TARGET_SSSE3"
- "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
+ (set_attr "mode" "<sseinsnmode>")])
(define_insn "*ssse3_pmulhrswv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
(sign_extend:V4SI
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))
(const_int 14))
- (const_vector:V4HI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
+ (match_operand:V4HI 3 "const1_operand"))
(const_int 1))))]
"TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
"pmulhrsw\t{%2, %0|%0, %2}"
(define_insn "<ssse3_avx2>_pshufb<mode>3"
[(set (match_operand:VI1_AVX2 0 "register_operand" "=x,x")
- (unspec:VI1_AVX2 [(match_operand:VI1_AVX2 1 "register_operand" "0,x")
- (match_operand:VI1_AVX2 2 "nonimmediate_operand" "xm,xm")]
- UNSPEC_PSHUFB))]
+ (unspec:VI1_AVX2
+ [(match_operand:VI1_AVX2 1 "register_operand" "0,x")
+ (match_operand:VI1_AVX2 2 "nonimmediate_operand" "xm,xm")]
+ UNSPEC_PSHUFB))]
"TARGET_SSSE3"
"@
pshufb\t{%2, %0|%0, %2}
(set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
+ (set_attr "btver2_decode" "vector,vector")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "ssse3_pshufbv8qi3"
(define_insn "<ssse3_avx2>_palignr<mode>"
[(set (match_operand:SSESCALARMODE 0 "register_operand" "=x,x")
- (unspec:SSESCALARMODE [(match_operand:SSESCALARMODE 1 "register_operand" "0,x")
- (match_operand:SSESCALARMODE 2 "nonimmediate_operand" "xm,xm")
- (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n")]
- UNSPEC_PALIGNR))]
+ (unspec:SSESCALARMODE
+ [(match_operand:SSESCALARMODE 1 "register_operand" "0,x")
+ (match_operand:SSESCALARMODE 2 "nonimmediate_operand" "xm,xm")
+ (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n")]
+ UNSPEC_PALIGNR))]
"TARGET_SSSE3"
{
operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
(define_insn "sse4a_extrqi"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
- (match_operand 2 "const_0_to_255_operand" "")
- (match_operand 3 "const_0_to_255_operand" "")]
+ (match_operand 2 "const_0_to_255_operand")
+ (match_operand 3 "const_0_to_255_operand")]
UNSPEC_EXTRQI))]
"TARGET_SSE4A"
"extrq\t{%3, %2, %0|%0, %2, %3}"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
(match_operand:V2DI 2 "register_operand" "x")
- (match_operand 3 "const_0_to_255_operand" "")
- (match_operand 4 "const_0_to_255_operand" "")]
+ (match_operand 3 "const_0_to_255_operand")
+ (match_operand 4 "const_0_to_255_operand")]
UNSPEC_INSERTQI))]
"TARGET_SSE4A"
"insertq\t{%4, %3, %2, %0|%0, %2, %3, %4}"
(vec_merge:VF
(match_operand:VF 2 "nonimmediate_operand" "xm,xm")
(match_operand:VF 1 "register_operand" "0,x")
- (match_operand:SI 3 "const_0_to_<blendbits>_operand" "")))]
+ (match_operand:SI 3 "const_0_to_<blendbits>_operand")))]
"TARGET_SSE4_1"
"@
blend<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
(set_attr "mode" "<MODE>")])
(define_insn "<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>"
- [(set (match_operand:VF 0 "reg_not_xmm0_operand_maybe_avx" "=x,x")
+ [(set (match_operand:VF 0 "register_operand" "=x,x")
(unspec:VF
- [(match_operand:VF 1 "reg_not_xmm0_operand_maybe_avx" "0,x")
- (match_operand:VF 2 "nonimm_not_xmm0_operand_maybe_avx" "xm,xm")
+ [(match_operand:VF 1 "register_operand" "0,x")
+ (match_operand:VF 2 "nonimmediate_operand" "xm,xm")
(match_operand:VF 3 "register_operand" "Yz,x")]
UNSPEC_BLENDV))]
"TARGET_SSE4_1"
(set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
+ (set_attr "btver2_decode" "vector,vector")
(set_attr "mode" "<MODE>")])
(define_insn "<sse4_1>_dp<ssemodesuffix><avxsizesuffix>"
(set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
+ (set_attr "btver2_decode" "vector,vector")
(set_attr "mode" "<MODE>")])
(define_insn "<sse4_1_avx2>_movntdqa"
(define_insn "<sse4_1_avx2>_mpsadbw"
[(set (match_operand:VI1_AVX2 0 "register_operand" "=x,x")
- (unspec:VI1_AVX2 [(match_operand:VI1_AVX2 1 "register_operand" "0,x")
- (match_operand:VI1_AVX2 2 "nonimmediate_operand" "xm,xm")
- (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
- UNSPEC_MPSADBW))]
+ (unspec:VI1_AVX2
+ [(match_operand:VI1_AVX2 1 "register_operand" "0,x")
+ (match_operand:VI1_AVX2 2 "nonimmediate_operand" "xm,xm")
+ (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
+ UNSPEC_MPSADBW))]
"TARGET_SSE4_1"
"@
mpsadbw\t{%3, %2, %0|%0, %2, %3}
(set_attr "length_immediate" "1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
+ (set_attr "btver2_decode" "vector,vector")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "avx2_packusdw"
(set_attr "mode" "TI")])
(define_insn "<sse4_1_avx2>_pblendvb"
- [(set (match_operand:VI1_AVX2 0 "reg_not_xmm0_operand_maybe_avx" "=x,x")
+ [(set (match_operand:VI1_AVX2 0 "register_operand" "=x,x")
(unspec:VI1_AVX2
- [(match_operand:VI1_AVX2 1 "reg_not_xmm0_operand_maybe_avx" "0,x")
- (match_operand:VI1_AVX2 2 "nonimm_not_xmm0_operand_maybe_avx" "xm,xm")
+ [(match_operand:VI1_AVX2 1 "register_operand" "0,x")
+ (match_operand:VI1_AVX2 2 "nonimmediate_operand" "xm,xm")
(match_operand:VI1_AVX2 3 "register_operand" "Yz,x")]
UNSPEC_BLENDV))]
"TARGET_SSE4_1"
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "*,1")
(set_attr "prefix" "orig,vex")
+ (set_attr "btver2_decode" "vector,vector")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "sse4_1_pblendw"
;; The builtin uses an 8-bit immediate. Expand that.
(define_expand "avx2_pblendw"
- [(set (match_operand:V16HI 0 "register_operand" "")
+ [(set (match_operand:V16HI 0 "register_operand")
(vec_merge:V16HI
- (match_operand:V16HI 2 "nonimmediate_operand" "")
- (match_operand:V16HI 1 "register_operand" "")
- (match_operand:SI 3 "const_0_to_255_operand" "")))]
+ (match_operand:V16HI 2 "nonimmediate_operand")
+ (match_operand:V16HI 1 "register_operand")
+ (match_operand:SI 3 "const_0_to_255_operand")))]
"TARGET_AVX2"
{
HOST_WIDE_INT val = INTVAL (operands[3]) & 0xff;
(any_extend:V8HI
(vec_select:V8QI
(match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 1)
- (const_int 2)
- (const_int 3)
- (const_int 4)
- (const_int 5)
- (const_int 6)
- (const_int 7)]))))]
+ (parallel [(const_int 0) (const_int 1)
+ (const_int 2) (const_int 3)
+ (const_int 4) (const_int 5)
+ (const_int 6) (const_int 7)]))))]
"TARGET_SSE4_1"
"%vpmov<extsuffix>bw\t{%1, %0|%0, %q1}"
[(set_attr "type" "ssemov")
(any_extend:V8SI
(vec_select:V8QI
(match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 1)
- (const_int 2)
- (const_int 3)
- (const_int 4)
- (const_int 5)
- (const_int 6)
- (const_int 7)]))))]
+ (parallel [(const_int 0) (const_int 1)
+ (const_int 2) (const_int 3)
+ (const_int 4) (const_int 5)
+ (const_int 6) (const_int 7)]))))]
"TARGET_AVX2"
"vpmov<extsuffix>bd\t{%1, %0|%0, %q1}"
[(set_attr "type" "ssemov")
(any_extend:V4SI
(vec_select:V4QI
(match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 1)
- (const_int 2)
- (const_int 3)]))))]
+ (parallel [(const_int 0) (const_int 1)
+ (const_int 2) (const_int 3)]))))]
"TARGET_SSE4_1"
"%vpmov<extsuffix>bd\t{%1, %0|%0, %k1}"
[(set_attr "type" "ssemov")
(any_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 1)
- (const_int 2)
- (const_int 3)]))))]
+ (parallel [(const_int 0) (const_int 1)
+ (const_int 2) (const_int 3)]))))]
"TARGET_SSE4_1"
"%vpmov<extsuffix>wd\t{%1, %0|%0, %q1}"
[(set_attr "type" "ssemov")
(any_extend:V4DI
(vec_select:V4QI
(match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 1)
- (const_int 2)
- (const_int 3)]))))]
+ (parallel [(const_int 0) (const_int 1)
+ (const_int 2) (const_int 3)]))))]
"TARGET_AVX2"
"vpmov<extsuffix>bq\t{%1, %0|%0, %k1}"
[(set_attr "type" "ssemov")
(any_extend:V2DI
(vec_select:V2QI
(match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 1)]))))]
+ (parallel [(const_int 0) (const_int 1)]))))]
"TARGET_SSE4_1"
"%vpmov<extsuffix>bq\t{%1, %0|%0, %w1}"
[(set_attr "type" "ssemov")
(any_extend:V4DI
(vec_select:V4HI
(match_operand:V8HI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 1)
- (const_int 2)
- (const_int 3)]))))]
+ (parallel [(const_int 0) (const_int 1)
+ (const_int 2) (const_int 3)]))))]
"TARGET_AVX2"
"vpmov<extsuffix>wq\t{%1, %0|%0, %q1}"
[(set_attr "type" "ssemov")
(any_extend:V2DI
(vec_select:V2HI
(match_operand:V8HI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 1)]))))]
+ (parallel [(const_int 0) (const_int 1)]))))]
"TARGET_SSE4_1"
"%vpmov<extsuffix>wq\t{%1, %0|%0, %k1}"
[(set_attr "type" "ssemov")
(any_extend:V2DI
(vec_select:V2SI
(match_operand:V4SI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 1)]))))]
+ (parallel [(const_int 0) (const_int 1)]))))]
"TARGET_SSE4_1"
"%vpmov<extsuffix>dq\t{%1, %0|%0, %q1}"
[(set_attr "type" "ssemov")
[(set_attr "type" "ssecomi")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
+ (set_attr "btver2_decode" "vector")
(set_attr "mode" "OI")])
(define_insn "sse4_1_ptest"
(set_attr "mode" "<MODE>")])
(define_expand "<sse4_1>_round<ssemodesuffix>_sfix<avxsizesuffix>"
- [(match_operand:<sseintvecmode> 0 "register_operand" "")
- (match_operand:VF1 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_0_to_15_operand" "")]
+ [(match_operand:<sseintvecmode> 0 "register_operand")
+ (match_operand:VF1 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_0_to_15_operand")]
"TARGET_ROUND"
{
rtx tmp = gen_reg_rtx (<MODE>mode);
})
(define_expand "<sse4_1>_round<ssemodesuffix>_vec_pack_sfix<avxsizesuffix>"
- [(match_operand:<ssepackfltmode> 0 "register_operand" "")
- (match_operand:VF2 1 "nonimmediate_operand" "")
- (match_operand:VF2 2 "nonimmediate_operand" "")
- (match_operand:SI 3 "const_0_to_15_operand" "")]
+ [(match_operand:<ssepackfltmode> 0 "register_operand")
+ (match_operand:VF2 1 "nonimmediate_operand")
+ (match_operand:VF2 2 "nonimmediate_operand")
+ (match_operand:SI 3 "const_0_to_15_operand")]
"TARGET_ROUND"
{
rtx tmp0, tmp1;
(define_expand "round<mode>2"
[(set (match_dup 4)
(plus:VF
- (match_operand:VF 1 "register_operand" "")
+ (match_operand:VF 1 "register_operand")
(match_dup 3)))
- (set (match_operand:VF 0 "register_operand" "")
+ (set (match_operand:VF 0 "register_operand")
(unspec:VF
[(match_dup 4) (match_dup 5)]
UNSPEC_ROUND))]
})
(define_expand "round<mode>2_sfix"
- [(match_operand:<sseintvecmode> 0 "register_operand" "")
- (match_operand:VF1 1 "register_operand" "")]
+ [(match_operand:<sseintvecmode> 0 "register_operand")
+ (match_operand:VF1 1 "register_operand")]
"TARGET_ROUND && !flag_trapping_math"
{
rtx tmp = gen_reg_rtx (<MODE>mode);
})
(define_expand "round<mode>2_vec_pack_sfix"
- [(match_operand:<ssepackfltmode> 0 "register_operand" "")
- (match_operand:VF2 1 "register_operand" "")
- (match_operand:VF2 2 "register_operand" "")]
+ [(match_operand:<ssepackfltmode> 0 "register_operand")
+ (match_operand:VF2 1 "register_operand")
+ (match_operand:VF2 2 "register_operand")]
"TARGET_ROUND && !flag_trapping_math"
{
rtx tmp0, tmp1;
(define_insn_and_split "sse4_2_pcmpestr"
[(set (match_operand:SI 0 "register_operand" "=c,c")
(unspec:SI
- [(match_operand:V16QI 2 "reg_not_xmm0_operand" "x,x")
+ [(match_operand:V16QI 2 "register_operand" "x,x")
(match_operand:SI 3 "register_operand" "a,a")
- (match_operand:V16QI 4 "nonimm_not_xmm0_operand" "x,m")
+ (match_operand:V16QI 4 "nonimmediate_operand" "x,m")
(match_operand:SI 5 "register_operand" "d,d")
(match_operand:SI 6 "const_0_to_255_operand" "n,n")]
UNSPEC_PCMPESTR))
(set_attr "memory" "none,load")
(set_attr "mode" "TI")])
+(define_insn_and_split "*sse4_2_pcmpestr_unaligned"
+ [(set (match_operand:SI 0 "register_operand" "=c")
+ (unspec:SI
+ [(match_operand:V16QI 2 "register_operand" "x")
+ (match_operand:SI 3 "register_operand" "a")
+ (unspec:V16QI
+ [(match_operand:V16QI 4 "memory_operand" "m")]
+ UNSPEC_LOADU)
+ (match_operand:SI 5 "register_operand" "d")
+ (match_operand:SI 6 "const_0_to_255_operand" "n")]
+ UNSPEC_PCMPESTR))
+ (set (match_operand:V16QI 1 "register_operand" "=Yz")
+ (unspec:V16QI
+ [(match_dup 2)
+ (match_dup 3)
+ (unspec:V16QI [(match_dup 4)] UNSPEC_LOADU)
+ (match_dup 5)
+ (match_dup 6)]
+ UNSPEC_PCMPESTR))
+ (set (reg:CC FLAGS_REG)
+ (unspec:CC
+ [(match_dup 2)
+ (match_dup 3)
+ (unspec:V16QI [(match_dup 4)] UNSPEC_LOADU)
+ (match_dup 5)
+ (match_dup 6)]
+ UNSPEC_PCMPESTR))]
+ "TARGET_SSE4_2
+ && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ int ecx = !find_regno_note (curr_insn, REG_UNUSED, REGNO (operands[0]));
+ int xmm0 = !find_regno_note (curr_insn, REG_UNUSED, REGNO (operands[1]));
+ int flags = !find_regno_note (curr_insn, REG_UNUSED, FLAGS_REG);
+
+ if (ecx)
+ emit_insn (gen_sse4_2_pcmpestri (operands[0], operands[2],
+ operands[3], operands[4],
+ operands[5], operands[6]));
+ if (xmm0)
+ emit_insn (gen_sse4_2_pcmpestrm (operands[1], operands[2],
+ operands[3], operands[4],
+ operands[5], operands[6]));
+ if (flags && !(ecx || xmm0))
+ emit_insn (gen_sse4_2_pcmpestr_cconly (NULL, NULL,
+ operands[2], operands[3],
+ operands[4], operands[5],
+ operands[6]));
+ if (!(flags || ecx || xmm0))
+ emit_note (NOTE_INSN_DELETED);
+
+ DONE;
+}
+ [(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
+ (set_attr "memory" "load")
+ (set_attr "mode" "TI")])
+
(define_insn "sse4_2_pcmpestri"
[(set (match_operand:SI 0 "register_operand" "=c,c")
(unspec:SI
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "length_immediate" "1")
+ (set_attr "btver2_decode" "vector")
(set_attr "memory" "none,load")
(set_attr "mode" "TI")])
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
+ (set_attr "btver2_decode" "vector")
(set_attr "memory" "none,load")
(set_attr "mode" "TI")])
(set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
- (set_attr "memory" "none,load,none,load")
- (set_attr "prefix" "maybe_vex")
+ (set_attr "memory" "none,load,none,load")
+ (set_attr "btver2_decode" "vector,vector,vector,vector")
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "mode" "TI")])
+
+(define_insn_and_split "sse4_2_pcmpistr"
+ [(set (match_operand:SI 0 "register_operand" "=c,c")
+ (unspec:SI
+ [(match_operand:V16QI 2 "register_operand" "x,x")
+ (match_operand:V16QI 3 "nonimmediate_operand" "x,m")
+ (match_operand:SI 4 "const_0_to_255_operand" "n,n")]
+ UNSPEC_PCMPISTR))
+ (set (match_operand:V16QI 1 "register_operand" "=Yz,Yz")
+ (unspec:V16QI
+ [(match_dup 2)
+ (match_dup 3)
+ (match_dup 4)]
+ UNSPEC_PCMPISTR))
+ (set (reg:CC FLAGS_REG)
+ (unspec:CC
+ [(match_dup 2)
+ (match_dup 3)
+ (match_dup 4)]
+ UNSPEC_PCMPISTR))]
+ "TARGET_SSE4_2
+ && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ int ecx = !find_regno_note (curr_insn, REG_UNUSED, REGNO (operands[0]));
+ int xmm0 = !find_regno_note (curr_insn, REG_UNUSED, REGNO (operands[1]));
+ int flags = !find_regno_note (curr_insn, REG_UNUSED, FLAGS_REG);
+
+ if (ecx)
+ emit_insn (gen_sse4_2_pcmpistri (operands[0], operands[2],
+ operands[3], operands[4]));
+ if (xmm0)
+ emit_insn (gen_sse4_2_pcmpistrm (operands[1], operands[2],
+ operands[3], operands[4]));
+ if (flags && !(ecx || xmm0))
+ emit_insn (gen_sse4_2_pcmpistr_cconly (NULL, NULL,
+ operands[2], operands[3],
+ operands[4]));
+ if (!(flags || ecx || xmm0))
+ emit_note (NOTE_INSN_DELETED);
+
+ DONE;
+}
+ [(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
+ (set_attr "memory" "none,load")
(set_attr "mode" "TI")])
-(define_insn_and_split "sse4_2_pcmpistr"
- [(set (match_operand:SI 0 "register_operand" "=c,c")
+(define_insn_and_split "*sse4_2_pcmpistr_unaligned"
+ [(set (match_operand:SI 0 "register_operand" "=c")
(unspec:SI
- [(match_operand:V16QI 2 "reg_not_xmm0_operand" "x,x")
- (match_operand:V16QI 3 "nonimm_not_xmm0_operand" "x,m")
- (match_operand:SI 4 "const_0_to_255_operand" "n,n")]
+ [(match_operand:V16QI 2 "register_operand" "x")
+ (unspec:V16QI
+ [(match_operand:V16QI 3 "memory_operand" "m")]
+ UNSPEC_LOADU)
+ (match_operand:SI 4 "const_0_to_255_operand" "n")]
UNSPEC_PCMPISTR))
- (set (match_operand:V16QI 1 "register_operand" "=Yz,Yz")
+ (set (match_operand:V16QI 1 "register_operand" "=Yz")
(unspec:V16QI
[(match_dup 2)
- (match_dup 3)
+ (unspec:V16QI [(match_dup 3)] UNSPEC_LOADU)
(match_dup 4)]
UNSPEC_PCMPISTR))
(set (reg:CC FLAGS_REG)
(unspec:CC
[(match_dup 2)
- (match_dup 3)
+ (unspec:V16QI [(match_dup 3)] UNSPEC_LOADU)
(match_dup 4)]
UNSPEC_PCMPISTR))]
"TARGET_SSE4_2
(set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
- (set_attr "memory" "none,load")
+ (set_attr "memory" "load")
(set_attr "mode" "TI")])
(define_insn "sse4_2_pcmpistri"
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "memory" "none,load")
+ (set_attr "btver2_decode" "vector")
(set_attr "mode" "TI")])
(define_insn "sse4_2_pcmpistrm"
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "memory" "none,load")
+ (set_attr "btver2_decode" "vector")
(set_attr "mode" "TI")])
(define_insn "sse4_2_pcmpistr_cconly"
(set_attr "length_immediate" "1")
(set_attr "memory" "none,load,none,load")
(set_attr "prefix" "maybe_vex")
+ (set_attr "btver2_decode" "vector,vector,vector,vector")
(set_attr "mode" "TI")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;; XOP parallel integer multiply/add instructions.
-;; Note the XOP multiply/add instructions
-;; a[i] = b[i] * c[i] + d[i];
-;; do not allow the value being added to be a memory operation.
-(define_insn "xop_pmacsww"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (plus:V8HI
- (mult:V8HI
- (match_operand:V8HI 1 "nonimmediate_operand" "%x")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
- (match_operand:V8HI 3 "nonimmediate_operand" "x")))]
- "TARGET_XOP"
- "vpmacsww\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
-(define_insn "xop_pmacssww"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (ss_plus:V8HI
- (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%x")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
- (match_operand:V8HI 3 "nonimmediate_operand" "x")))]
- "TARGET_XOP"
- "vpmacssww\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
-(define_insn "xop_pmacsdd"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (plus:V4SI
- (mult:V4SI
- (match_operand:V4SI 1 "nonimmediate_operand" "%x")
- (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
- (match_operand:V4SI 3 "nonimmediate_operand" "x")))]
- "TARGET_XOP"
- "vpmacsdd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
+(define_code_iterator xop_plus [plus ss_plus])
-(define_insn "xop_pmacssdd"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (ss_plus:V4SI
- (mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "%x")
- (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
- (match_operand:V4SI 3 "nonimmediate_operand" "x")))]
- "TARGET_XOP"
- "vpmacssdd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
+(define_code_attr macs [(plus "macs") (ss_plus "macss")])
+(define_code_attr madcs [(plus "madcs") (ss_plus "madcss")])
-(define_insn "xop_pmacssdql"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (ss_plus:V2DI
- (mult:V2DI
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "%x")
- (parallel [(const_int 0)
- (const_int 2)])))
- (vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)])))
- (match_operand:V2DI 3 "nonimmediate_operand" "x")))]
- "TARGET_XOP"
- "vpmacssdql\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
+;; XOP parallel integer multiply/add instructions.
-(define_insn "xop_pmacssdqh"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (ss_plus:V2DI
- (mult:V2DI
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "%x")
- (parallel [(const_int 1)
- (const_int 3)])))
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 1)
- (const_int 3)]))))
- (match_operand:V2DI 3 "nonimmediate_operand" "x")))]
+(define_insn "xop_p<macs><ssemodesuffix><ssemodesuffix>"
+ [(set (match_operand:VI24_128 0 "register_operand" "=x")
+ (xop_plus:VI24_128
+ (mult:VI24_128
+ (match_operand:VI24_128 1 "nonimmediate_operand" "%x")
+ (match_operand:VI24_128 2 "nonimmediate_operand" "xm"))
+ (match_operand:VI24_128 3 "register_operand" "x")))]
"TARGET_XOP"
- "vpmacssdqh\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ "vp<macs><ssemodesuffix><ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "TI")])
-(define_insn "xop_pmacsdql"
+(define_insn "xop_p<macs>dql"
[(set (match_operand:V2DI 0 "register_operand" "=x")
- (plus:V2DI
+ (xop_plus:V2DI
(mult:V2DI
(sign_extend:V2DI
(vec_select:V2SI
(match_operand:V4SI 1 "nonimmediate_operand" "%x")
- (parallel [(const_int 0)
- (const_int 2)])))
+ (parallel [(const_int 0) (const_int 2)])))
(sign_extend:V2DI
(vec_select:V2SI
(match_operand:V4SI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)]))))
- (match_operand:V2DI 3 "nonimmediate_operand" "x")))]
+ (parallel [(const_int 0) (const_int 2)]))))
+ (match_operand:V2DI 3 "register_operand" "x")))]
"TARGET_XOP"
- "vpmacsdql\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ "vp<macs>dql\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "TI")])
-(define_insn "xop_pmacsdqh"
+(define_insn "xop_p<macs>dqh"
[(set (match_operand:V2DI 0 "register_operand" "=x")
- (plus:V2DI
+ (xop_plus:V2DI
(mult:V2DI
(sign_extend:V2DI
(vec_select:V2SI
(match_operand:V4SI 1 "nonimmediate_operand" "%x")
- (parallel [(const_int 1)
- (const_int 3)])))
+ (parallel [(const_int 1) (const_int 3)])))
(sign_extend:V2DI
(vec_select:V2SI
(match_operand:V4SI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 1)
- (const_int 3)]))))
- (match_operand:V2DI 3 "nonimmediate_operand" "x")))]
+ (parallel [(const_int 1) (const_int 3)]))))
+ (match_operand:V2DI 3 "register_operand" "x")))]
"TARGET_XOP"
- "vpmacsdqh\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ "vp<macs>dqh\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "TI")])
;; XOP parallel integer multiply/add instructions for the intrinisics
-(define_insn "xop_pmacsswd"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (ss_plus:V4SI
- (mult:V4SI
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 1 "nonimmediate_operand" "%x")
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)]))))
- (match_operand:V4SI 3 "nonimmediate_operand" "x")))]
- "TARGET_XOP"
- "vpmacsswd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
-(define_insn "xop_pmacswd"
+(define_insn "xop_p<macs>wd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
- (plus:V4SI
+ (xop_plus:V4SI
(mult:V4SI
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 1 "nonimmediate_operand" "%x")
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)])))
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)]))))
- (match_operand:V4SI 3 "nonimmediate_operand" "x")))]
- "TARGET_XOP"
- "vpmacswd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
-(define_insn "xop_pmadcsswd"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (ss_plus:V4SI
- (plus:V4SI
- (mult:V4SI
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 1 "nonimmediate_operand" "%x")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)])))
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)]))))
- (mult:V4SI
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_dup 2)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))))
- (match_operand:V4SI 3 "nonimmediate_operand" "x")))]
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)]))))
+ (match_operand:V4SI 3 "register_operand" "x")))]
"TARGET_XOP"
- "vpmadcsswd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ "vp<macs>wd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "TI")])
-(define_insn "xop_pmadcswd"
+(define_insn "xop_p<madcs>wd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
- (plus:V4SI
+ (xop_plus:V4SI
(plus:V4SI
(mult:V4SI
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 1 "nonimmediate_operand" "%x")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)])))
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)])))
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)]))))
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)]))))
(mult:V4SI
(sign_extend:V4SI
(vec_select:V4HI
(match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)])))
(sign_extend:V4SI
(vec_select:V4HI
(match_dup 2)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))))
- (match_operand:V4SI 3 "nonimmediate_operand" "x")))]
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)])))))
+ (match_operand:V4SI 3 "register_operand" "x")))]
"TARGET_XOP"
- "vpmadcswd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ "vp<madcs>wd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "TI")])
[(set_attr "type" "sse4arg")])
;; XOP horizontal add/subtract instructions
-(define_insn "xop_phaddbw"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (plus:V8HI
- (sign_extend:V8HI
- (vec_select:V8QI
- (match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)
- (const_int 8)
- (const_int 10)
- (const_int 12)
- (const_int 14)])))
- (sign_extend:V8HI
- (vec_select:V8QI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)
- (const_int 9)
- (const_int 11)
- (const_int 13)
- (const_int 15)])))))]
- "TARGET_XOP"
- "vphaddbw\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "xop_phaddbd"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (plus:V4SI
- (plus:V4SI
- (sign_extend:V4SI
- (vec_select:V4QI
- (match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 4)
- (const_int 8)
- (const_int 12)])))
- (sign_extend:V4SI
- (vec_select:V4QI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 5)
- (const_int 9)
- (const_int 13)]))))
- (plus:V4SI
- (sign_extend:V4SI
- (vec_select:V4QI
- (match_dup 1)
- (parallel [(const_int 2)
- (const_int 6)
- (const_int 10)
- (const_int 14)])))
- (sign_extend:V4SI
- (vec_select:V4QI
- (match_dup 1)
- (parallel [(const_int 3)
- (const_int 7)
- (const_int 11)
- (const_int 15)]))))))]
- "TARGET_XOP"
- "vphaddbd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "xop_phaddbq"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (plus:V2DI
- (plus:V2DI
- (plus:V2DI
- (sign_extend:V2DI
- (vec_select:V2QI
- (match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 8)])))
- (sign_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 9)]))))
- (plus:V2DI
- (sign_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 2)
- (const_int 10)])))
- (sign_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 3)
- (const_int 11)])))))
- (plus:V2DI
- (plus:V2DI
- (sign_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 4)
- (const_int 12)])))
- (sign_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 5)
- (const_int 13)]))))
- (plus:V2DI
- (sign_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 6)
- (const_int 14)])))
- (sign_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 7)
- (const_int 15)])))))))]
- "TARGET_XOP"
- "vphaddbq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "xop_phaddwd"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (plus:V4SI
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)])))
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))))]
- "TARGET_XOP"
- "vphaddwd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "xop_phaddwq"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (plus:V2DI
- (plus:V2DI
- (sign_extend:V2DI
- (vec_select:V2HI
- (match_operand:V8HI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 4)])))
- (sign_extend:V2DI
- (vec_select:V2HI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 5)]))))
- (plus:V2DI
- (sign_extend:V2DI
- (vec_select:V2HI
- (match_dup 1)
- (parallel [(const_int 2)
- (const_int 6)])))
- (sign_extend:V2DI
- (vec_select:V2HI
- (match_dup 1)
- (parallel [(const_int 3)
- (const_int 7)]))))))]
- "TARGET_XOP"
- "vphaddwq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "xop_phadddq"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (plus:V2DI
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)])))
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)])))))]
- "TARGET_XOP"
- "vphadddq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "xop_phaddubw"
+(define_insn "xop_phadd<u>bw"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(plus:V8HI
- (zero_extend:V8HI
+ (any_extend:V8HI
(vec_select:V8QI
(match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)
- (const_int 8)
- (const_int 10)
- (const_int 12)
- (const_int 14)])))
- (zero_extend:V8HI
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)
+ (const_int 8) (const_int 10)
+ (const_int 12) (const_int 14)])))
+ (any_extend:V8HI
(vec_select:V8QI
(match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)
- (const_int 9)
- (const_int 11)
- (const_int 13)
- (const_int 15)])))))]
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)
+ (const_int 9) (const_int 11)
+ (const_int 13) (const_int 15)])))))]
"TARGET_XOP"
- "vphaddubw\t{%1, %0|%0, %1}"
+ "vphadd<u>bw\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")])
-(define_insn "xop_phaddubd"
+(define_insn "xop_phadd<u>bd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(plus:V4SI
(plus:V4SI
- (zero_extend:V4SI
+ (any_extend:V4SI
(vec_select:V4QI
(match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 4)
- (const_int 8)
- (const_int 12)])))
- (zero_extend:V4SI
+ (parallel [(const_int 0) (const_int 4)
+ (const_int 8) (const_int 12)])))
+ (any_extend:V4SI
(vec_select:V4QI
(match_dup 1)
- (parallel [(const_int 1)
- (const_int 5)
- (const_int 9)
- (const_int 13)]))))
+ (parallel [(const_int 1) (const_int 5)
+ (const_int 9) (const_int 13)]))))
(plus:V4SI
- (zero_extend:V4SI
+ (any_extend:V4SI
(vec_select:V4QI
(match_dup 1)
- (parallel [(const_int 2)
- (const_int 6)
- (const_int 10)
- (const_int 14)])))
- (zero_extend:V4SI
+ (parallel [(const_int 2) (const_int 6)
+ (const_int 10) (const_int 14)])))
+ (any_extend:V4SI
(vec_select:V4QI
(match_dup 1)
- (parallel [(const_int 3)
- (const_int 7)
- (const_int 11)
- (const_int 15)]))))))]
+ (parallel [(const_int 3) (const_int 7)
+ (const_int 11) (const_int 15)]))))))]
"TARGET_XOP"
- "vphaddubd\t{%1, %0|%0, %1}"
+ "vphadd<u>bd\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")])
-(define_insn "xop_phaddubq"
+(define_insn "xop_phadd<u>bq"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(plus:V2DI
(plus:V2DI
(plus:V2DI
- (zero_extend:V2DI
+ (any_extend:V2DI
(vec_select:V2QI
(match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 8)])))
- (sign_extend:V2DI
+ (parallel [(const_int 0) (const_int 8)])))
+ (any_extend:V2DI
(vec_select:V2QI
(match_dup 1)
- (parallel [(const_int 1)
- (const_int 9)]))))
+ (parallel [(const_int 1) (const_int 9)]))))
(plus:V2DI
- (zero_extend:V2DI
+ (any_extend:V2DI
(vec_select:V2QI
(match_dup 1)
- (parallel [(const_int 2)
- (const_int 10)])))
- (zero_extend:V2DI
+ (parallel [(const_int 2) (const_int 10)])))
+ (any_extend:V2DI
(vec_select:V2QI
(match_dup 1)
- (parallel [(const_int 3)
- (const_int 11)])))))
+ (parallel [(const_int 3) (const_int 11)])))))
(plus:V2DI
(plus:V2DI
- (zero_extend:V2DI
+ (any_extend:V2DI
(vec_select:V2QI
(match_dup 1)
- (parallel [(const_int 4)
- (const_int 12)])))
- (sign_extend:V2DI
+ (parallel [(const_int 4) (const_int 12)])))
+ (any_extend:V2DI
(vec_select:V2QI
(match_dup 1)
- (parallel [(const_int 5)
- (const_int 13)]))))
+ (parallel [(const_int 5) (const_int 13)]))))
(plus:V2DI
- (zero_extend:V2DI
+ (any_extend:V2DI
(vec_select:V2QI
(match_dup 1)
- (parallel [(const_int 6)
- (const_int 14)])))
- (zero_extend:V2DI
+ (parallel [(const_int 6) (const_int 14)])))
+ (any_extend:V2DI
(vec_select:V2QI
(match_dup 1)
- (parallel [(const_int 7)
- (const_int 15)])))))))]
+ (parallel [(const_int 7) (const_int 15)])))))))]
"TARGET_XOP"
- "vphaddubq\t{%1, %0|%0, %1}"
+ "vphadd<u>bq\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")])
-(define_insn "xop_phadduwd"
+(define_insn "xop_phadd<u>wd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(plus:V4SI
- (zero_extend:V4SI
+ (any_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)])))
- (zero_extend:V4SI
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)])))
+ (any_extend:V4SI
(vec_select:V4HI
(match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))))]
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)])))))]
"TARGET_XOP"
- "vphadduwd\t{%1, %0|%0, %1}"
+ "vphadd<u>wd\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")])
-(define_insn "xop_phadduwq"
+(define_insn "xop_phadd<u>wq"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(plus:V2DI
(plus:V2DI
- (zero_extend:V2DI
+ (any_extend:V2DI
(vec_select:V2HI
(match_operand:V8HI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 4)])))
- (zero_extend:V2DI
+ (parallel [(const_int 0) (const_int 4)])))
+ (any_extend:V2DI
(vec_select:V2HI
(match_dup 1)
- (parallel [(const_int 1)
- (const_int 5)]))))
+ (parallel [(const_int 1) (const_int 5)]))))
(plus:V2DI
- (zero_extend:V2DI
+ (any_extend:V2DI
(vec_select:V2HI
(match_dup 1)
- (parallel [(const_int 2)
- (const_int 6)])))
- (zero_extend:V2DI
+ (parallel [(const_int 2) (const_int 6)])))
+ (any_extend:V2DI
(vec_select:V2HI
(match_dup 1)
- (parallel [(const_int 3)
- (const_int 7)]))))))]
+ (parallel [(const_int 3) (const_int 7)]))))))]
"TARGET_XOP"
- "vphadduwq\t{%1, %0|%0, %1}"
+ "vphadd<u>wq\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")])
-(define_insn "xop_phaddudq"
+(define_insn "xop_phadd<u>dq"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(plus:V2DI
- (zero_extend:V2DI
+ (any_extend:V2DI
(vec_select:V2SI
(match_operand:V4SI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)])))
- (zero_extend:V2DI
+ (parallel [(const_int 0) (const_int 2)])))
+ (any_extend:V2DI
(vec_select:V2SI
(match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)])))))]
+ (parallel [(const_int 1) (const_int 3)])))))]
"TARGET_XOP"
- "vphaddudq\t{%1, %0|%0, %1}"
+ "vphadd<u>dq\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")])
(define_insn "xop_phsubbw"
(sign_extend:V8HI
(vec_select:V8QI
(match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)
- (const_int 8)
- (const_int 10)
- (const_int 12)
- (const_int 14)])))
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)
+ (const_int 8) (const_int 10)
+ (const_int 12) (const_int 14)])))
(sign_extend:V8HI
(vec_select:V8QI
(match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)
- (const_int 9)
- (const_int 11)
- (const_int 13)
- (const_int 15)])))))]
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)
+ (const_int 9) (const_int 11)
+ (const_int 13) (const_int 15)])))))]
"TARGET_XOP"
"vphsubbw\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")])
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)])))
+ (parallel [(const_int 0) (const_int 2)
+ (const_int 4) (const_int 6)])))
(sign_extend:V4SI
(vec_select:V4HI
(match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))))]
+ (parallel [(const_int 1) (const_int 3)
+ (const_int 5) (const_int 7)])))))]
"TARGET_XOP"
"vphsubwd\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")])
(sign_extend:V2DI
(vec_select:V2SI
(match_operand:V4SI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)])))
+ (parallel [(const_int 0) (const_int 2)])))
(sign_extend:V2DI
(vec_select:V2SI
(match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)])))))]
+ (parallel [(const_int 1) (const_int 3)])))))]
"TARGET_XOP"
"vphsubdq\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")])
;; XOP packed rotate instructions
(define_expand "rotl<mode>3"
- [(set (match_operand:VI_128 0 "register_operand" "")
+ [(set (match_operand:VI_128 0 "register_operand")
(rotate:VI_128
- (match_operand:VI_128 1 "nonimmediate_operand" "")
+ (match_operand:VI_128 1 "nonimmediate_operand")
(match_operand:SI 2 "general_operand")))]
"TARGET_XOP"
{
})
(define_expand "rotr<mode>3"
- [(set (match_operand:VI_128 0 "register_operand" "")
+ [(set (match_operand:VI_128 0 "register_operand")
(rotatert:VI_128
- (match_operand:VI_128 1 "nonimmediate_operand" "")
+ (match_operand:VI_128 1 "nonimmediate_operand")
(match_operand:SI 2 "general_operand")))]
"TARGET_XOP"
{
(match_operand:SI 2 "const_0_to_<sserotatemax>_operand" "n")))]
"TARGET_XOP"
{
- operands[3] = GEN_INT ((<ssescalarnum> * 8) - INTVAL (operands[2]));
+ operands[3]
+ = GEN_INT (GET_MODE_BITSIZE (<ssescalarmode>mode) - INTVAL (operands[2]));
return \"vprot<ssemodesuffix>\t{%3, %1, %0|%0, %1, %3}\";
}
[(set_attr "type" "sseishft")
(set_attr "mode" "TI")])
(define_expand "vrotr<mode>3"
- [(match_operand:VI_128 0 "register_operand" "")
- (match_operand:VI_128 1 "register_operand" "")
- (match_operand:VI_128 2 "register_operand" "")]
+ [(match_operand:VI_128 0 "register_operand")
+ (match_operand:VI_128 1 "register_operand")
+ (match_operand:VI_128 2 "register_operand")]
"TARGET_XOP"
{
rtx reg = gen_reg_rtx (<MODE>mode);
})
(define_expand "vrotl<mode>3"
- [(match_operand:VI_128 0 "register_operand" "")
- (match_operand:VI_128 1 "register_operand" "")
- (match_operand:VI_128 2 "register_operand" "")]
+ [(match_operand:VI_128 0 "register_operand")
+ (match_operand:VI_128 1 "register_operand")
+ (match_operand:VI_128 2 "register_operand")]
"TARGET_XOP"
{
emit_insn (gen_xop_vrotl<mode>3 (operands[0], operands[1], operands[2]));
;; XOP packed shift instructions.
(define_expand "vlshr<mode>3"
- [(set (match_operand:VI12_128 0 "register_operand" "")
+ [(set (match_operand:VI12_128 0 "register_operand")
(lshiftrt:VI12_128
- (match_operand:VI12_128 1 "register_operand" "")
- (match_operand:VI12_128 2 "nonimmediate_operand" "")))]
+ (match_operand:VI12_128 1 "register_operand")
+ (match_operand:VI12_128 2 "nonimmediate_operand")))]
"TARGET_XOP"
{
rtx neg = gen_reg_rtx (<MODE>mode);
})
(define_expand "vlshr<mode>3"
- [(set (match_operand:VI48_128 0 "register_operand" "")
+ [(set (match_operand:VI48_128 0 "register_operand")
(lshiftrt:VI48_128
- (match_operand:VI48_128 1 "register_operand" "")
- (match_operand:VI48_128 2 "nonimmediate_operand" "")))]
+ (match_operand:VI48_128 1 "register_operand")
+ (match_operand:VI48_128 2 "nonimmediate_operand")))]
"TARGET_AVX2 || TARGET_XOP"
{
if (!TARGET_AVX2)
})
(define_expand "vlshr<mode>3"
- [(set (match_operand:VI48_256 0 "register_operand" "")
+ [(set (match_operand:VI48_256 0 "register_operand")
(lshiftrt:VI48_256
- (match_operand:VI48_256 1 "register_operand" "")
- (match_operand:VI48_256 2 "nonimmediate_operand" "")))]
+ (match_operand:VI48_256 1 "register_operand")
+ (match_operand:VI48_256 2 "nonimmediate_operand")))]
"TARGET_AVX2")
(define_expand "vashr<mode>3"
- [(set (match_operand:VI128_128 0 "register_operand" "")
+ [(set (match_operand:VI128_128 0 "register_operand")
(ashiftrt:VI128_128
- (match_operand:VI128_128 1 "register_operand" "")
- (match_operand:VI128_128 2 "nonimmediate_operand" "")))]
+ (match_operand:VI128_128 1 "register_operand")
+ (match_operand:VI128_128 2 "nonimmediate_operand")))]
"TARGET_XOP"
{
rtx neg = gen_reg_rtx (<MODE>mode);
})
(define_expand "vashrv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "")
- (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "")
- (match_operand:V4SI 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:V4SI 0 "register_operand")
+ (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand")
+ (match_operand:V4SI 2 "nonimmediate_operand")))]
"TARGET_AVX2 || TARGET_XOP"
{
if (!TARGET_AVX2)
})
(define_expand "vashrv8si3"
- [(set (match_operand:V8SI 0 "register_operand" "")
- (ashiftrt:V8SI (match_operand:V8SI 1 "register_operand" "")
- (match_operand:V8SI 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:V8SI 0 "register_operand")
+ (ashiftrt:V8SI (match_operand:V8SI 1 "register_operand")
+ (match_operand:V8SI 2 "nonimmediate_operand")))]
"TARGET_AVX2")
(define_expand "vashl<mode>3"
- [(set (match_operand:VI12_128 0 "register_operand" "")
+ [(set (match_operand:VI12_128 0 "register_operand")
(ashift:VI12_128
- (match_operand:VI12_128 1 "register_operand" "")
- (match_operand:VI12_128 2 "nonimmediate_operand" "")))]
+ (match_operand:VI12_128 1 "register_operand")
+ (match_operand:VI12_128 2 "nonimmediate_operand")))]
"TARGET_XOP"
{
emit_insn (gen_xop_sha<mode>3 (operands[0], operands[1], operands[2]));
})
(define_expand "vashl<mode>3"
- [(set (match_operand:VI48_128 0 "register_operand" "")
+ [(set (match_operand:VI48_128 0 "register_operand")
(ashift:VI48_128
- (match_operand:VI48_128 1 "register_operand" "")
- (match_operand:VI48_128 2 "nonimmediate_operand" "")))]
+ (match_operand:VI48_128 1 "register_operand")
+ (match_operand:VI48_128 2 "nonimmediate_operand")))]
"TARGET_AVX2 || TARGET_XOP"
{
if (!TARGET_AVX2)
})
(define_expand "vashl<mode>3"
- [(set (match_operand:VI48_256 0 "register_operand" "")
+ [(set (match_operand:VI48_256 0 "register_operand")
(ashift:VI48_256
- (match_operand:VI48_256 1 "register_operand" "")
- (match_operand:VI48_256 2 "nonimmediate_operand" "")))]
+ (match_operand:VI48_256 1 "register_operand")
+ (match_operand:VI48_256 2 "nonimmediate_operand")))]
"TARGET_AVX2")
(define_insn "xop_sha<mode>3"
(set_attr "prefix_extra" "2")
(set_attr "mode" "TI")])
-;; SSE2 doesn't have some shift variants, so define versions for XOP
-(define_expand "ashlv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "")
- (ashift:V16QI
- (match_operand:V16QI 1 "register_operand" "")
- (match_operand:SI 2 "nonmemory_operand" "")))]
- "TARGET_XOP"
-{
- rtx reg = gen_reg_rtx (V16QImode);
- rtx par;
- int i;
-
- par = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
- for (i = 0; i < 16; i++)
- XVECEXP (par, 0, i) = operands[2];
-
- emit_insn (gen_vec_initv16qi (reg, par));
- emit_insn (gen_xop_shav16qi3 (operands[0], operands[1], reg));
- DONE;
-})
-
-(define_expand "<shift_insn>v16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "")
- (any_shiftrt:V16QI
- (match_operand:V16QI 1 "register_operand" "")
- (match_operand:SI 2 "nonmemory_operand" "")))]
- "TARGET_XOP"
+(define_expand "<shift_insn><mode>3"
+ [(set (match_operand:VI1_AVX2 0 "register_operand")
+ (any_shift:VI1_AVX2
+ (match_operand:VI1_AVX2 1 "register_operand")
+ (match_operand:SI 2 "nonmemory_operand")))]
+ "TARGET_SSE2"
{
- rtx reg = gen_reg_rtx (V16QImode);
- rtx par;
- bool negate = false;
- rtx (*shift_insn)(rtx, rtx, rtx);
- int i;
-
- if (CONST_INT_P (operands[2]))
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- else
- negate = true;
+ if (TARGET_XOP && <MODE>mode == V16QImode)
+ {
+ bool negate = false;
+ rtx (*gen) (rtx, rtx, rtx);
+ rtx tmp, par;
+ int i;
- par = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
- for (i = 0; i < 16; i++)
- XVECEXP (par, 0, i) = operands[2];
+ if (<CODE> != ASHIFT)
+ {
+ if (CONST_INT_P (operands[2]))
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ else
+ negate = true;
+ }
+ par = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
+ for (i = 0; i < 16; i++)
+ XVECEXP (par, 0, i) = operands[2];
- emit_insn (gen_vec_initv16qi (reg, par));
+ tmp = gen_reg_rtx (V16QImode);
+ emit_insn (gen_vec_initv16qi (tmp, par));
- if (negate)
- emit_insn (gen_negv16qi2 (reg, reg));
+ if (negate)
+ emit_insn (gen_negv16qi2 (tmp, tmp));
- if (<CODE> == LSHIFTRT)
- shift_insn = gen_xop_shlv16qi3;
+ gen = (<CODE> == LSHIFTRT ? gen_xop_shlv16qi3 : gen_xop_shav16qi3);
+ emit_insn (gen (operands[0], operands[1], tmp));
+ }
else
- shift_insn = gen_xop_shav16qi3;
-
- emit_insn (shift_insn (operands[0], operands[1], reg));
+ ix86_expand_vecop_qihi (<CODE>, operands[0], operands[1], operands[2]);
DONE;
})
(define_expand "ashrv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "")
+ [(set (match_operand:V2DI 0 "register_operand")
(ashiftrt:V2DI
- (match_operand:V2DI 1 "register_operand" "")
- (match_operand:DI 2 "nonmemory_operand" "")))]
+ (match_operand:V2DI 1 "register_operand")
+ (match_operand:DI 2 "nonmemory_operand")))]
"TARGET_XOP"
{
rtx reg = gen_reg_rtx (V2DImode);
(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
+ (set_attr "btver2_decode" "double,double")
(set_attr "mode" "TI")])
(define_insn "aesenclast"
(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
+ (set_attr "btver2_decode" "double,double")
(set_attr "mode" "TI")])
(define_insn "aesdec"
(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
+ (set_attr "btver2_decode" "double,double")
(set_attr "mode" "TI")])
(define_insn "aesdeclast"
(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
+ (set_attr "btver2_decode" "double,double")
(set_attr "mode" "TI")])
(define_insn "aesimc"
(set_attr "modrm" "0")
(set_attr "memory" "none")
(set_attr "prefix" "vex")
+ (set_attr "btver2_decode" "vector")
(set_attr "mode" "OI")])
;; Clear the upper 128bits of AVX registers, equivalent to a NOP
;; if the upper 128bits are unused.
(define_insn "avx_vzeroupper"
- [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
- UNSPECV_VZEROUPPER)]
+ [(unspec_volatile [(const_int 0)] UNSPECV_VZEROUPPER)]
"TARGET_AVX"
"vzeroupper"
[(set_attr "type" "sse")
(set_attr "modrm" "0")
(set_attr "memory" "none")
(set_attr "prefix" "vex")
+ (set_attr "btver2_decode" "vector")
(set_attr "mode" "OI")])
(define_mode_attr AVXTOSSEMODE
(set_attr "prefix" "vex")
(set_attr "mode" "<sseinsnmode>")])
-(define_insn "avx2_permvarv8si"
- [(set (match_operand:V8SI 0 "register_operand" "=x")
- (unspec:V8SI
- [(match_operand:V8SI 1 "nonimmediate_operand" "xm")
- (match_operand:V8SI 2 "register_operand" "x")]
- UNSPEC_VPERMSI))]
- "TARGET_AVX2"
- "vpermd\t{%1, %2, %0|%0, %2, %1}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
- (set_attr "mode" "OI")])
-
-(define_insn "avx2_permv4df"
- [(set (match_operand:V4DF 0 "register_operand" "=x")
- (unspec:V4DF
- [(match_operand:V4DF 1 "register_operand" "xm")
- (match_operand:SI 2 "const_0_to_255_operand" "n")]
- UNSPEC_VPERMDF))]
+(define_insn "avx2_pbroadcast<mode>_1"
+ [(set (match_operand:VI_256 0 "register_operand" "=x")
+ (vec_duplicate:VI_256
+ (vec_select:<ssescalarmode>
+ (match_operand:VI_256 1 "nonimmediate_operand" "xm")
+ (parallel [(const_int 0)]))))]
"TARGET_AVX2"
- "vpermpd\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
+ "vpbroadcast<ssemodesuffix>\t{%x1, %0|%0, %x1}"
+ [(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
- (set_attr "mode" "OI")])
+ (set_attr "mode" "<sseinsnmode>")])
-(define_insn "avx2_permvarv8sf"
- [(set (match_operand:V8SF 0 "register_operand" "=x")
- (unspec:V8SF
- [(match_operand:V8SF 1 "nonimmediate_operand" "xm")
+(define_insn "avx2_permvar<mode>"
+ [(set (match_operand:VI4F_256 0 "register_operand" "=x")
+ (unspec:VI4F_256
+ [(match_operand:VI4F_256 1 "nonimmediate_operand" "xm")
(match_operand:V8SI 2 "register_operand" "x")]
- UNSPEC_VPERMSF))]
+ UNSPEC_VPERMVAR))]
"TARGET_AVX2"
- "vpermps\t{%1, %2, %0|%0, %2, %1}"
+ "vperm<ssemodesuffix>\t{%1, %2, %0|%0, %2, %1}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
-(define_expand "avx2_permv4di"
- [(match_operand:V4DI 0 "register_operand" "")
- (match_operand:V4DI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_0_to_255_operand" "")]
+(define_expand "avx2_perm<mode>"
+ [(match_operand:VI8F_256 0 "register_operand")
+ (match_operand:VI8F_256 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_0_to_255_operand")]
"TARGET_AVX2"
{
int mask = INTVAL (operands[2]);
- emit_insn (gen_avx2_permv4di_1 (operands[0], operands[1],
- GEN_INT ((mask >> 0) & 3),
- GEN_INT ((mask >> 2) & 3),
- GEN_INT ((mask >> 4) & 3),
- GEN_INT ((mask >> 6) & 3)));
+ emit_insn (gen_avx2_perm<mode>_1 (operands[0], operands[1],
+ GEN_INT ((mask >> 0) & 3),
+ GEN_INT ((mask >> 2) & 3),
+ GEN_INT ((mask >> 4) & 3),
+ GEN_INT ((mask >> 6) & 3)));
DONE;
})
-(define_insn "avx2_permv4di_1"
- [(set (match_operand:V4DI 0 "register_operand" "=x")
- (vec_select:V4DI
- (match_operand:V4DI 1 "nonimmediate_operand" "xm")
- (parallel [(match_operand 2 "const_0_to_3_operand" "")
- (match_operand 3 "const_0_to_3_operand" "")
- (match_operand 4 "const_0_to_3_operand" "")
- (match_operand 5 "const_0_to_3_operand" "")])))]
+(define_insn "avx2_perm<mode>_1"
+ [(set (match_operand:VI8F_256 0 "register_operand" "=x")
+ (vec_select:VI8F_256
+ (match_operand:VI8F_256 1 "nonimmediate_operand" "xm")
+ (parallel [(match_operand 2 "const_0_to_3_operand")
+ (match_operand 3 "const_0_to_3_operand")
+ (match_operand 4 "const_0_to_3_operand")
+ (match_operand 5 "const_0_to_3_operand")])))]
"TARGET_AVX2"
{
int mask = 0;
mask |= INTVAL (operands[4]) << 4;
mask |= INTVAL (operands[5]) << 6;
operands[2] = GEN_INT (mask);
- return "vpermq\t{%2, %1, %0|%0, %1, %2}";
+ return "vperm<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}";
}
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
- (set_attr "mode" "OI")])
+ (set_attr "mode" "<sseinsnmode>")])
(define_insn "avx2_permv2ti"
[(set (match_operand:V4DI 0 "register_operand" "=x")
[V8SI V8SF V4DI V4DF])
(define_insn "vec_dup<mode>"
- [(set (match_operand:AVX_VEC_DUP_MODE 0 "register_operand" "=x,x")
+ [(set (match_operand:AVX_VEC_DUP_MODE 0 "register_operand" "=x,x,x")
(vec_duplicate:AVX_VEC_DUP_MODE
- (match_operand:<ssescalarmode> 1 "nonimmediate_operand" "m,?x")))]
+ (match_operand:<ssescalarmode> 1 "nonimmediate_operand" "m,x,?x")))]
"TARGET_AVX"
"@
vbroadcast<ssescalarmodesuffix>\t{%1, %0|%0, %1}
+ vbroadcast<ssescalarmodesuffix>\t{%x1, %0|%0, %x1}
#"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
+ (set_attr "isa" "*,avx2,noavx2")
(set_attr "mode" "V8SF")])
(define_insn "avx2_vbroadcasti128_<mode>"
(set_attr "mode" "OI")])
(define_split
- [(set (match_operand:AVX_VEC_DUP_MODE 0 "register_operand" "")
+ [(set (match_operand:AVX_VEC_DUP_MODE 0 "register_operand")
(vec_duplicate:AVX_VEC_DUP_MODE
- (match_operand:<ssescalarmode> 1 "register_operand" "")))]
- "TARGET_AVX && reload_completed"
+ (match_operand:<ssescalarmode> 1 "register_operand")))]
+ "TARGET_AVX && !TARGET_AVX2 && reload_completed"
[(set (match_dup 2)
(vec_duplicate:<ssehalfvecmode> (match_dup 1)))
(set (match_dup 0)
[(match_operand 3 "const_int_operand" "C,n,n")])))]
"TARGET_AVX"
"#"
- "&& reload_completed"
+ "&& reload_completed && (<MODE>mode != V4DFmode || !TARGET_AVX2)"
[(set (match_dup 0) (vec_duplicate:VF_256 (match_dup 1)))]
{
rtx op0 = operands[0], op1 = operands[1];
{
int mask;
+ if (TARGET_AVX2 && elt == 0)
+ {
+ emit_insn (gen_vec_dup<mode> (op0, gen_lowpart (<ssescalarmode>mode,
+ op1)));
+ DONE;
+ }
+
/* Shuffle element we care about into all elements of the 128-bit lane.
The other lane gets shuffled too, but we don't care. */
if (<MODE>mode == V4DFmode)
})
(define_expand "avx_vpermil<mode>"
- [(set (match_operand:VF2 0 "register_operand" "")
+ [(set (match_operand:VF2 0 "register_operand")
(vec_select:VF2
- (match_operand:VF2 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_0_to_255_operand" "")))]
+ (match_operand:VF2 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_0_to_255_operand")))]
"TARGET_AVX"
{
int mask = INTVAL (operands[2]);
})
(define_expand "avx_vpermil<mode>"
- [(set (match_operand:VF1 0 "register_operand" "")
+ [(set (match_operand:VF1 0 "register_operand")
(vec_select:VF1
- (match_operand:VF1 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "const_0_to_255_operand" "")))]
+ (match_operand:VF1 1 "nonimmediate_operand")
+ (match_operand:SI 2 "const_0_to_255_operand")))]
"TARGET_AVX"
{
int mask = INTVAL (operands[2]);
(vec_select:VF
(match_operand:VF 1 "nonimmediate_operand" "xm")
(match_parallel 2 ""
- [(match_operand 3 "const_int_operand" "")])))]
+ [(match_operand 3 "const_int_operand")])))]
"TARGET_AVX
&& avx_vpermilp_parallel (operands[2], <MODE>mode)"
{
[(set_attr "type" "sselog")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
+ (set_attr "btver2_decode" "vector")
(set_attr "mode" "<MODE>")])
(define_expand "avx_vperm2f128<mode>3"
- [(set (match_operand:AVX256MODE2P 0 "register_operand" "")
+ [(set (match_operand:AVX256MODE2P 0 "register_operand")
(unspec:AVX256MODE2P
- [(match_operand:AVX256MODE2P 1 "register_operand" "")
- (match_operand:AVX256MODE2P 2 "nonimmediate_operand" "")
- (match_operand:SI 3 "const_0_to_255_operand" "")]
+ [(match_operand:AVX256MODE2P 1 "register_operand")
+ (match_operand:AVX256MODE2P 2 "nonimmediate_operand")
+ (match_operand:SI 3 "const_0_to_255_operand")]
UNSPEC_VPERMIL2F128))]
"TARGET_AVX"
{
(match_operand:AVX256MODE2P 1 "register_operand" "x")
(match_operand:AVX256MODE2P 2 "nonimmediate_operand" "xm"))
(match_parallel 3 ""
- [(match_operand 4 "const_int_operand" "")])))]
+ [(match_operand 4 "const_int_operand")])))]
"TARGET_AVX
&& avx_vperm2f128_parallel (operands[3], <MODE>mode)"
{
(set_attr "mode" "<sseinsnmode>")])
(define_expand "avx_vinsertf128<mode>"
- [(match_operand:V_256 0 "register_operand" "")
- (match_operand:V_256 1 "register_operand" "")
- (match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" "")
- (match_operand:SI 3 "const_0_to_1_operand" "")]
+ [(match_operand:V_256 0 "register_operand")
+ (match_operand:V_256 1 "register_operand")
+ (match_operand:<ssehalfvecmode> 2 "nonimmediate_operand")
+ (match_operand:SI 3 "const_0_to_1_operand")]
"TARGET_AVX"
{
rtx (*insn)(rtx, rtx, rtx);
[(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
+ (set_attr "btver2_decode" "vector")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "<avx_avx2>_maskstore<ssemodesuffix><avxsizesuffix>"
[(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
+ (set_attr "btver2_decode" "vector")
(set_attr "mode" "<sseinsnmode>")])
(define_insn_and_split "avx_<castmode><avxsizesuffix>_<castmode>"
})
(define_expand "vec_init<mode>"
- [(match_operand:V_256 0 "register_operand" "")
- (match_operand 1 "" "")]
+ [(match_operand:V_256 0 "register_operand")
+ (match_operand 1)]
"TARGET_AVX"
{
ix86_expand_vector_init (false, operands[0], operands[1]);
})
(define_expand "avx2_extracti128"
- [(match_operand:V2DI 0 "nonimmediate_operand" "")
- (match_operand:V4DI 1 "register_operand" "")
- (match_operand:SI 2 "const_0_to_1_operand" "")]
+ [(match_operand:V2DI 0 "nonimmediate_operand")
+ (match_operand:V4DI 1 "register_operand")
+ (match_operand:SI 2 "const_0_to_1_operand")]
"TARGET_AVX2"
{
rtx (*insn)(rtx, rtx);
})
(define_expand "avx2_inserti128"
- [(match_operand:V4DI 0 "register_operand" "")
- (match_operand:V4DI 1 "register_operand" "")
- (match_operand:V2DI 2 "nonimmediate_operand" "")
- (match_operand:SI 3 "const_0_to_1_operand" "")]
+ [(match_operand:V4DI 0 "register_operand")
+ (match_operand:V4DI 1 "register_operand")
+ (match_operand:V2DI 2 "nonimmediate_operand")
+ (match_operand:SI 3 "const_0_to_1_operand")]
"TARGET_AVX2"
{
rtx (*insn)(rtx, rtx, rtx);
"vcvtph2ps\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "vex")
+ (set_attr "btver2_decode" "double")
(set_attr "mode" "V8SF")])
(define_expand "vcvtps2ph"
- [(set (match_operand:V8HI 0 "register_operand" "")
+ [(set (match_operand:V8HI 0 "register_operand")
(vec_concat:V8HI
- (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "")
- (match_operand:SI 2 "const_0_to_255_operand" "")]
+ (unspec:V4HI [(match_operand:V4SF 1 "register_operand")
+ (match_operand:SI 2 "const_0_to_255_operand")]
UNSPEC_VCVTPS2PH)
(match_dup 3)))]
"TARGET_F16C"
(unspec:V4HI [(match_operand:V4SF 1 "register_operand" "x")
(match_operand:SI 2 "const_0_to_255_operand" "N")]
UNSPEC_VCVTPS2PH)
- (match_operand:V4HI 3 "const0_operand" "")))]
+ (match_operand:V4HI 3 "const0_operand")))]
"TARGET_F16C"
"vcvtps2ph\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecvt")
"vcvtps2ph\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "vex")
+ (set_attr "btver2_decode" "vector")
(set_attr "mode" "V8SF")])
;; For gather* insn patterns
(V8SI "V4SI") (V8SF "V4SF")])
(define_expand "avx2_gathersi<mode>"
- [(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "")
+ [(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand")
(unspec:VEC_GATHER_MODE
- [(match_operand:VEC_GATHER_MODE 1 "register_operand" "")
+ [(match_operand:VEC_GATHER_MODE 1 "register_operand")
(mem:<ssescalarmode>
(match_par_dup 7
- [(match_operand 2 "vsib_address_operand" "")
+ [(match_operand 2 "vsib_address_operand")
(match_operand:<VEC_GATHER_IDXSI>
- 3 "register_operand" "")
- (match_operand:SI 5 "const1248_operand " "")]))
+ 3 "register_operand")
+ (match_operand:SI 5 "const1248_operand ")]))
(mem:BLK (scratch))
- (match_operand:VEC_GATHER_MODE 4 "register_operand" "")]
+ (match_operand:VEC_GATHER_MODE 4 "register_operand")]
UNSPEC_GATHER))
- (clobber (match_scratch:VEC_GATHER_MODE 6 ""))])]
+ (clobber (match_scratch:VEC_GATHER_MODE 6))])]
"TARGET_AVX2"
{
operands[7]
(set_attr "mode" "<sseinsnmode>")])
(define_expand "avx2_gatherdi<mode>"
- [(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "")
+ [(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand")
(unspec:VEC_GATHER_MODE
- [(match_operand:<VEC_GATHER_SRCDI> 1 "register_operand" "")
+ [(match_operand:<VEC_GATHER_SRCDI> 1 "register_operand")
(mem:<ssescalarmode>
(match_par_dup 7
- [(match_operand 2 "vsib_address_operand" "")
+ [(match_operand 2 "vsib_address_operand")
(match_operand:<VEC_GATHER_IDXDI>
- 3 "register_operand" "")
- (match_operand:SI 5 "const1248_operand " "")]))
+ 3 "register_operand")
+ (match_operand:SI 5 "const1248_operand ")]))
(mem:BLK (scratch))
(match_operand:<VEC_GATHER_SRCDI>
- 4 "register_operand" "")]
+ 4 "register_operand")]
UNSPEC_GATHER))
- (clobber (match_scratch:VEC_GATHER_MODE 6 ""))])]
+ (clobber (match_scratch:VEC_GATHER_MODE 6))])]
"TARGET_AVX2"
{
operands[7]
projects / platform / upstream / gcc48.git / blobdiff