+2018-02-08 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+
+ * config/s390/s390-opts.h (enum indirect_branch): Define.
+ * config/s390/s390-protos.h (s390_return_addr_from_memory)
+ (s390_indirect_branch_via_thunk)
+ (s390_indirect_branch_via_inline_thunk): Add function prototypes.
+ (enum s390_indirect_branch_type): Define.
+ * config/s390/s390.c (struct s390_frame_layout, struct
+ machine_function): Remove.
+ (indirect_branch_prez10thunk_mask, indirect_branch_z10thunk_mask)
+ (indirect_branch_table_label_no, indirect_branch_table_name):
+ Define variables.
+ (INDIRECT_BRANCH_NUM_OPTIONS): Define macro.
+ (enum s390_indirect_branch_option): Define.
+ (s390_return_addr_from_memory): New function.
+ (s390_handle_string_attribute): New function.
+ (s390_attribute_table): Add new attribute handler.
+ (s390_execute_label): Handle UNSPEC_EXECUTE_JUMP patterns.
+ (s390_indirect_branch_via_thunk): New function.
+ (s390_indirect_branch_via_inline_thunk): New function.
+ (s390_function_ok_for_sibcall): When jumping via thunk disallow
+ sibling call optimization for non z10 compiles.
+ (s390_emit_call): Force indirect branch target to be a single
+ register. Add r1 clobber for non-z10 compiles.
+ (s390_emit_epilogue): Emit return jump via return_use expander.
+ (s390_reorg): Handle JUMP_INSNs as execute targets.
+ (s390_option_override_internal): Perform validity checks for the
+ new command line options.
+ (s390_indirect_branch_attrvalue): New function.
+ (s390_indirect_branch_settings): New function.
+ (s390_set_current_function): Invoke s390_indirect_branch_settings.
+ (s390_output_indirect_thunk_function): New function.
+ (s390_code_end): Implement target hook.
+ (s390_case_values_threshold): Implement target hook.
+ (TARGET_ASM_CODE_END, TARGET_CASE_VALUES_THRESHOLD): Define target
+ macros.
+ * config/s390/s390.h (struct s390_frame_layout)
+ (struct machine_function): Move here from s390.c.
+ (TARGET_INDIRECT_BRANCH_NOBP_RET)
+ (TARGET_INDIRECT_BRANCH_NOBP_JUMP)
+ (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK)
+ (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK)
+ (TARGET_INDIRECT_BRANCH_NOBP_CALL)
+ (TARGET_DEFAULT_INDIRECT_BRANCH_TABLE)
+ (TARGET_INDIRECT_BRANCH_THUNK_NAME_EXRL)
+ (TARGET_INDIRECT_BRANCH_THUNK_NAME_EX)
+ (TARGET_INDIRECT_BRANCH_TABLE): Define macros.
+ * config/s390/s390.md (UNSPEC_EXECUTE_JUMP)
+ (INDIRECT_BRANCH_THUNK_REGNUM): Define constants.
+ (mnemonic attribute): Add values which aren't recognized
+ automatically.
+ ("*cjump_long", "*icjump_long", "*basr", "*basr_r"): Disable
+ pattern for branch conversion. Fix mnemonic attribute.
+ ("*c<code>", "*sibcall_br", "*sibcall_value_br", "*return"): Emit
+ indirect branch via thunk if requested.
+ ("indirect_jump", "<code>"): Expand patterns for branch conversion.
+ ("*indirect_jump"): Disable for branch conversion using out of
+ line thunks.
+ ("indirect_jump_via_thunk<mode>_z10")
+ ("indirect_jump_via_thunk<mode>")
+ ("indirect_jump_via_inlinethunk<mode>_z10")
+ ("indirect_jump_via_inlinethunk<mode>", "*casesi_jump")
+ ("casesi_jump_via_thunk<mode>_z10", "casesi_jump_via_thunk<mode>")
+ ("casesi_jump_via_inlinethunk<mode>_z10")
+ ("casesi_jump_via_inlinethunk<mode>", "*basr_via_thunk<mode>_z10")
+ ("*basr_via_thunk<mode>", "*basr_r_via_thunk_z10")
+ ("*basr_r_via_thunk", "return<mode>_prez10"): New pattern.
+ ("*indirect2_jump"): Disable for branch conversion.
+ ("casesi_jump"): Turn into expander and expand patterns for branch
+ conversion.
+ ("return_use"): New expander.
+ ("*return"): Emit return via thunk and rename it to ...
+ ("*return<mode>"): ... this one.
+ * config/s390/s390.opt: Add new options and and enum for the
+ option values.
+
+2018-02-08 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * lra-constraints.c (match_reload): Unconditionally use
+ gen_lowpart_SUBREG, rather than selecting between that
+ and equivalent gen_rtx_SUBREG code.
+
+2018-02-08 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/84233
+ * tree-ssa-phiprop.c (propagate_with_phi): Use separate
+ changed flag instead of boguously re-using phi_inserted.
+
+2018-02-08 Martin Jambor <mjambor@suse.cz>
+
+ * hsa-gen.c (get_symbol_for_decl): Set program allocation for
+ static local variables.
+
+2018-02-08 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/84278
+ * tree-vect-stmts.c (vectorizable_store): When looking for
+ smaller vector types to perform grouped strided loads/stores
+ make sure the mode is supported by the target.
+ (vectorizable_load): Likewise.
+
+2018-02-08 Wilco Dijkstra <wdijkstr@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_components_for_bb):
+ Increase LDP/STP opportunities by adding adjacent callee-saves.
+
+2018-02-08 Wilco Dijkstra <wdijkstr@arm.com>
+
+ PR rtl-optimization/84068
+ PR rtl-optimization/83459
+ * haifa-sched.c (rank_for_schedule): Fix SCHED_PRESSURE_MODEL sorting.
+
+2018-02-08 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/84224
+ * gimple-ssa-warn-alloca.c (pass_walloca::execute): Remove assert.
+ * calls.c (gimple_alloca_call_p): Only return TRUE when we have
+ non-zero arguments.
+
+2018-02-07 Iain Sandoe <iain@codesourcery.com>
+
+ * config/rs6000/altivec.md (*restore_world): Remove LR use.
+ * config/rs6000/predicates.md (restore_world_operation): Adjust op
+ count, remove one USE.
+
+2018-02-07 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ * doc/install.texi (Configuration): Document the
+ --with-long-double-format={ibm,ieee} PowerPC configuration
+ options.
+
+ PR target/84154
+ * config/rs6000/rs6000.md (fix_trunc<SFDF:mode><QHI:mode>2):
+ Convert from define_expand to be define_insn_and_split. Rework
+ float/double/_Float128 conversions to QI/HI/SImode to work with
+ both ISA 2.07 (power8) or ISA 3.0 (power9). Fix regression where
+ conversions to QI/HImode types did a store and then a load to
+ truncate the value. For conversions to VSX registers, don't split
+ the insn, instead emit the code directly. Use the code iterator
+ any_fix to combine signed and unsigned conversions.
+ (fix<uns>_trunc<SFDF:mode>si2_p8): Likewise.
+ (fixuns_trunc<SFDF:mode><QHI:mode>2): Likewise.
+ (fix_trunc<IEEE128:mode><QHI:mode>2): Likewise.
+ (fix<uns>_trunc<SFDF:mode><QHI:mode>2): Likewise.
+ (fix_<mode>di2_hw): Likewise.
+ (fixuns_<mode>di2_hw): Likewise.
+ (fix_<mode>si2_hw): Likewise.
+ (fixuns_<mode>si2_hw): Likewise.
+ (fix<uns>_<IEEE128:mode><SDI:mode>2_hw): Likewise.
+ (fix<uns>_trunc<IEEE128:mode><QHI:mode>2): Likewise.
+ (fctiw<u>z_<mode>_smallint): Rename fctiw<u>z_<mode>_smallint to
+ fix<uns>_trunc<SFDF:mode>si2_p8.
+ (fix_trunc<SFDF:mode><QHI:mode>2_internal): Delete, no longer
+ used.
+ (fixuns_trunc<SFDF:mode><QHI:mode>2_internal): Likewise.
+ (fix<uns>_<mode>_mem): Likewise.
+ (fctiw<u>z_<mode>_mem): Likewise.
+ (fix<uns>_<mode>_mem): Likewise.
+ (fix<uns>_trunc<SFDF:mode><QHSI:mode>2_mem): On ISA 3.0, prevent
+ the register allocator from doing a direct move to the GPRs to do
+ a store, and instead use the ISA 3.0 store byte/half-word from
+ vector register instruction. For IEEE 128-bit floating point,
+ also optimize stores of 32-bit ints.
+ (fix<uns>_trunc<IEEE128:mode><QHSI:mode>2_mem): Likewise.
+
+2018-02-07 Alan Hayward <alan.hayward@arm.com>
+
+ * genextract.c (push_pathstr_operand): New function to support
+ [a-zA-Z].
+ (walk_rtx): Call push_pathstr_operand.
+ (print_path): Support [a-zA-Z].
+
+2018-02-07 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/84037
+ * tree-vectorizer.h (struct _loop_vec_info): Add ivexpr_map member.
+ (cse_and_gimplify_to_preheader): Declare.
+ (vect_get_place_in_interleaving_chain): Likewise.
+ * tree-vect-loop.c (_loop_vec_info::_loop_vec_info): Initialize
+ ivexpr_map.
+ (_loop_vec_info::~_loop_vec_info): Delete it.
+ (cse_and_gimplify_to_preheader): New function.
+ * tree-vect-slp.c (vect_get_place_in_interleaving_chain): Export.
+ * tree-vect-stmts.c (vectorizable_store): CSE base and steps.
+ (vectorizable_load): Likewise. For grouped stores always base
+ the IV on the first element.
+ * tree-vect-loop-manip.c (vect_loop_versioning): Unshare versioning
+ condition before gimplifying.
+
+2018-02-07 Jakub Jelinek <jakub@redhat.com>
+
+ * tree-eh.c (operation_could_trap_helper_p): Ignore honor_trapv for
+ *DIV_EXPR and *MOD_EXPR.
+
+2018-02-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/84248
+ * config/i386/i386.c (ix86_option_override_internal): Mask out
+ the CF_SET bit when checking -fcf-protection.
+
+2018-02-07 Tom de Vries <tom@codesourcery.com>
+
+ PR libgomp/84217
+ * omp-expand.c (expand_oacc_collapse_init): Ensure diff_type is large
+ enough.
+
+2018-02-07 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/84204
+ * tree-chrec.c (chrec_fold_plus_1): Remove size limiting in
+ this place.
+
+ PR tree-optimization/84205
+ * graphite-isl-ast-to-gimple.c (binary_op_to_tree): Also
+ special-case isl_ast_op_zdiv_r.
+
+ PR tree-optimization/84223
+ * graphite-scop-detection.c (gather_bbs::before_dom_children):
+ Only add conditions from within the region.
+ (gather_bbs::after_dom_children): Adjust.
+
+2018-02-07 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/84209
+ * config/avr/avr.h (GENERAL_REGNO_P, GENERAL_REG_P): New macros.
+ * config/avr/avr.md: Only post-reload split REG-REG moves if
+ either register is REGERAL_REG_P.
+
+2018-02-07 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/84235
+ * tree-ssa-scopedtables.c
+ (avail_exprs_stack::simplify_binary_operation): Fir MINUS_EXPR, punt
+ if the subtraction is performed in floating point type where NaNs are
+ honored. For *DIV_EXPR, punt for ALL_FRACT_MODE_Ps where we can't
+ build 1. Formatting fix.
+
+2018-02-06 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/84146
+ * config/i386/i386.c (rest_of_insert_endbranch): Only skip
+ NOTE_INSN_CALL_ARG_LOCATION after a call, not anything else,
+ and skip it regardless of bb boundaries. Use CALL_P macro,
+ don't test INSN_P (insn) together with CALL_P or JUMP_P check
+ unnecessarily, formatting fix.
+
+2018-02-06 Michael Collison <michael.collison@arm.com>
+
+ * config/arm/thumb2.md:
+ (*thumb2_mov_negscc): Split only if TARGET_THUMB2 && !arm_restrict_it.
+ (*thumb_mov_notscc): Ditto.
+
+2018-02-06 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ PR target/84154
+ * config/rs6000/rs6000.md (su code attribute): Use "u" for
+ unsigned_fix, not "s".
+
+2018-02-06 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
+
+ * configure.ac (gcc_fn_eh_frame_ro): New function.
+ (gcc_cv_as_cfi_directive): Check both 32 and 64-bit assembler for
+ correct .eh_frame permissions.
+ * configure: Regenerate.
+
+2018-02-06 Andrew Jenner <andrew@codeourcery.com>
+
+ * doc/invoke.texi: Add section for the PowerPC SPE backend. Remove
+ irrelevant options.
+
+2018-02-06 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
+
+ * config/rs6000/rs6000.c (rs6000_option_override_internal):
+ Display warning message for -mno-speculate-indirect-jumps.
+
+2018-02-06 Andrew Jenner <andrew@codesourcery.com>
+
+ * config/powerpcspe/powerpcspe.opt: (msimple-fpu, mfpu) Add
+ Undocumented.
+ * config/powerpcspe/sysv4.opt (mbit-align): Likewise.
+
+2018-02-06 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/84225
+ * tree-eh.c (find_trapping_overflow): Only call
+ operation_no_trapping_overflow when ANY_INTEGRAL_TYPE_P.
+
+2018-02-06 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ PR target/84145
+ * config/i386/i386.c: Reimplement the check of possible options
+ -mibt/-mshstk conbination. Change error messages.
+ * doc/invoke.texi: Fix a typo: remove extra '='.
+
+2018-02-06 Marek Polacek <polacek@redhat.com>
+
+ PR tree-optimization/84228
+ * tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Skip debug statements.
+
+2018-02-06 Tamar Christina <tamar.christina@arm.com>
+
+ PR target/82641
+ * config/arm/arm.c (arm_print_asm_arch_directives): Record already
+ emitted arch directives.
+ * config/arm/arm-c.c (arm_cpu_builtins): Undefine __ARM_ARCH and
+ __ARM_FEATURE_COPROC before changing architectures.
+
+2018-02-06 Richard Biener <rguenther@suse.de>
+
+ * config/i386/i386.c (print_reg): Fix typo.
+ (ix86_loop_unroll_adjust): Do not unroll beyond the original nunroll.
+
+2018-02-06 Eric Botcazou <ebotcazou@adacore.com>
+
+ * configure: Regenerate.
+
+2018-02-05 Martin Sebor <msebor@redhat.com>
+
+ PR tree-optimization/83369
+ * tree-ssa-ccp.c (pass_post_ipa_warn::execute): Use %G to print
+ inlining context.
+
+2018-02-05 Martin Liska <mliska@suse.cz>
+
+ * doc/invoke.texi: Cherry-pick upstream r323995.
+
+2018-02-05 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * ira.c (ira_init_register_move_cost): Adjust comment.
+
+2018-02-05 Martin Liska <mliska@suse.cz>
+
+ PR gcov-profile/84137
+ * doc/gcov.texi: Fix typo in documentation.
+
+2018-02-05 Martin Liska <mliska@suse.cz>
+
+ PR gcov-profile/83879
+ * doc/gcov.texi: Document necessity of --dynamic-list-data when
+ using dlopen functionality.
+
+2018-02-05 Olga Makhotina <olga.makhotina@intel.com>
+
+ * config/i386/avx512dqintrin.h (_mm_mask_range_sd, _mm_maskz_range_sd,
+ _mm_mask_range_round_sd, _mm_maskz_range_round_sd, _mm_mask_range_ss,
+ _mm_maskz_range_ss, _mm_mask_range_round_ss,
+ _mm_maskz_range_round_ss): New intrinsics.
+ (__builtin_ia32_rangesd128_round)
+ (__builtin_ia32_rangess128_round): Remove.
+ (__builtin_ia32_rangesd128_mask_round,
+ __builtin_ia32_rangess128_mask_round): New builtins.
+ * config/i386/i386-builtin.def (__builtin_ia32_rangesd128_round,
+ __builtin_ia32_rangess128_round): Remove.
+ (__builtin_ia32_rangesd128_mask_round,
+ __builtin_ia32_rangess128_mask_round): New builtins.
+ * config/i386/sse.md (ranges<mode><round_saeonly_name>): Renamed to ...
+ (ranges<mode><mask_scalar_name><round_saeonly_scalar_name>): ... this.
+ ((match_operand:VF_128 2 "<round_saeonly_nimm_predicate>"
+ "<round_saeonly_constraint>")): Changed to ...
+ ((match_operand:VF_128 2 "<round_saeonly_scalar_nimm_predicate>"
+ "<round_saeonly_scalar_constraint>")): ... this.
+ ("vrange<ssescalarmodesuffix>\t{%3, <round_saeonly_op4>%2, %1, %0|
+ %0, %1, %2<round_saeonly_op4>, %3}"): Changed to ...
+ ("vrange<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2,
+ %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1,
+ %2<round_saeonly_scalar_mask_op4>, %3}"): ... this.
+
+2018-02-02 Andrew Jenner <andrew@codesourcery.com>
+
+ * config/powerpcspe/powerpcspe.opt: Add Undocumented to irrelevant
+ options.
+ * config/powerpcspe/powerpcspe-tables.opt (rs6000_cpu_opt_value):
+ Remove all values except native, 8540 and 8548.
+
+2018-02-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/i386/i386.c (ix86_output_function_return): Pass
+ INVALID_REGNUM, instead of -1, as invalid register number to
+ indirect_thunk_name and output_indirect_thunk.
+
+2018-02-02 Julia Koval <julia.koval@intel.com>
+
+ * config.gcc: Add -march=icelake.
+ * config/i386/driver-i386.c (host_detect_local_cpu): Detect icelake.
+ * config/i386/i386-c.c (ix86_target_macros_internal): Handle icelake.
+ * config/i386/i386.c (processor_costs): Add m_ICELAKE.
+ (PTA_ICELAKE, PTA_AVX512VNNI, PTA_GFNI, PTA_VAES, PTA_AVX512VBMI2,
+ PTA_VPCLMULQDQ, PTA_RDPID, PTA_AVX512BITALG): New.
+ (processor_target_table): Add icelake.
+ (ix86_option_override_internal): Handle new PTAs.
+ (get_builtin_code_for_version): Handle icelake.
+ (M_INTEL_COREI7_ICELAKE): New.
+ (fold_builtin_cpu): Handle icelake.
+ * config/i386/i386.h (TARGET_ICELAKE, PROCESSOR_ICELAKE): New.
+ * doc/invoke.texi: Add -march=icelake.
+
+2018-02-02 Julia Koval <julia.koval@intel.com>
+
+ * config/i386/i386.c (ix86_option_override_internal): Change flags type
+ to wide_int_bitmask.
+ * wide-int-bitmask.h: New.
+
+2018-02-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ PR target/84066
+ * config/i386/i386.md: Replace Pmode with word_mode in
+ builtin_setjmp_setup and builtin_longjmp to support x32.
+
+2018-02-01 Peter Bergner <bergner@vnet.ibm.com>
+
+ PR target/56010
+ PR target/83743
+ * config/rs6000/driver-rs6000.c: #include "diagnostic.h".
+ #include "opts.h".
+ (rs6000_supported_cpu_names): New static variable.
+ (linux_cpu_translation_table): Likewise.
+ (elf_platform) <cpu>: Define new static variable and use it.
+ Translate kernel AT_PLATFORM name to canonical name if needed.
+ Error if platform name is unknown.
+
+2018-02-01 Aldy Hernandez <aldyh@redhat.com>
+
+ PR target/84089
+ * config/pa/predicates.md (base14_operand): Handle E_VOIDmode.
+
+2018-02-01 Jeff Law <law@redhat.com>
+
+ PR target/84128
+ * config/i386/i386.c (release_scratch_register_on_entry): Add new
+ OFFSET and RELEASE_VIA_POP arguments. Use SP+OFFSET to restore
+ the scratch if RELEASE_VIA_POP is false.
+ (ix86_adjust_stack_and_probe_stack_clash): Un-constify SIZE.
+ If we have to save a temporary register, decrement SIZE appropriately.
+ Pass new arguments to release_scratch_register_on_entry.
+ (ix86_adjust_stack_and_probe): Likewise.
+ (ix86_emit_probe_stack_range): Pass new arguments to
+ release_scratch_register_on_entry.
+
+2018-02-01 Uros Bizjak <ubizjak@gmail.com>
+
+ PR rtl-optimization/84157
+ * combine.c (change_zero_ext): Use REG_P predicate in
+ front of HARD_REGISTER_P predicate.
+
+2018-02-01 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr.c (avr_option_override): Move disabling of
+ -fdelete-null-pointer-checks to...
+ * common/config/avr/avr-common.c (avr_option_optimization_table):
+ ...here.
+
+2018-02-01 Richard Sandiford <richard.sandiford@linaro.org>
+
+ PR tree-optimization/81635
+ * tree-data-ref.c (split_constant_offset_1): For types that
+ wrap on overflow, try to use range info to prove that wrapping
+ cannot occur.
+
+2018-02-01 Renlin Li <renlin.li@arm.com>
+
+ PR target/83370
+ * config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle
+ TAILCALL_ADDR_REGS.
+ (aarch64_register_move_cost): Likewise.
+ * config/aarch64/aarch64.h (reg_class): Rename CALLER_SAVE_REGS to
+ TAILCALL_ADDR_REGS.
+ (REG_CLASS_NAMES): Likewise.
+ (REG_CLASS_CONTENTS): Rename CALLER_SAVE_REGS to
+ TAILCALL_ADDR_REGS. Remove IP registers.
+ * config/aarch64/aarch64.md (Ucs): Update register constraint.
+
+2018-02-01 Richard Biener <rguenther@suse.de>
+
+ * domwalk.h (dom_walker::dom_walker): Add additional constructor
+ for specifying RPO order and allow NULL for that.
+ * domwalk.c (dom_walker::dom_walker): Likewise.
+ (dom_walker::walk): Handle NULL RPO order.
+ * tree-into-ssa.c (rewrite_dom_walker): Do not walk dom children
+ in RPO order.
+ (rewrite_update_dom_walker): Likewise.
+ (mark_def_dom_walker): Likewise.
+
+2018-02-01 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * config/aarch64/aarch64-protos.h (aarch64_split_sve_subreg_move)
+ (aarch64_maybe_expand_sve_subreg_move): Declare.
+ * config/aarch64/aarch64.md (UNSPEC_REV_SUBREG): New unspec.
+ * config/aarch64/predicates.md (aarch64_any_register_operand): New
+ predicate.
+ * config/aarch64/aarch64-sve.md (mov<mode>): Optimize subreg moves
+ that are semantically a reverse operation.
+ (*aarch64_sve_mov<mode>_subreg_be): New pattern.
+ * config/aarch64/aarch64.c (aarch64_maybe_expand_sve_subreg_move):
+ (aarch64_replace_reg_mode, aarch64_split_sve_subreg_move): New
+ functions.
+ (aarch64_can_change_mode_class): For big-endian, forbid changes
+ between two SVE modes if they have different element sizes.
+
+2018-02-01 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * config/aarch64/aarch64.c (aarch64_expand_sve_const_vector): Prefer
+ the TImode handling for big-endian targets.
+
+2018-02-01 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * config/aarch64/aarch64-sve.md (sve_ld1rq): Replace with...
+ (*sve_ld1rq<Vesize>): ... this new pattern. Handle all element sizes,
+ not just bytes.
+ * config/aarch64/aarch64.c (aarch64_expand_sve_widened_duplicate):
+ Remove BSWAP handing for big-endian targets and use the form of
+ LD1RQ appropariate for the mode.
+
+2018-02-01 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * config/aarch64/aarch64.c (aarch64_simd_valid_immediate): Handle
+ all CONST_VECTOR_DUPLICATE_P vectors, not just those with a single
+ duplicated element.
+
+2018-02-01 Richard Sandiford <richard.sandiford@linaro.org>
+
+ PR tearget/83845
+ * config/aarch64/aarch64.c (aarch64_secondary_reload): Tighten
+ check for operands that need to go through aarch64_sve_reload_be.
+
+2018-02-01 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/81661
+ PR tree-optimization/84117
+ * tree-eh.h (rewrite_to_non_trapping_overflow): Declare.
+ * tree-eh.c: Include gimplify.h.
+ (find_trapping_overflow, replace_trapping_overflow,
+ rewrite_to_non_trapping_overflow): New functions.
+ * tree-vect-loop.c: Include tree-eh.h.
+ (vect_get_loop_niters): Use rewrite_to_non_trapping_overflow.
+ * tree-data-ref.c: Include tree-eh.h.
+ (get_segment_min_max): Use rewrite_to_non_trapping_overflow.
+
+2018-01-31 Uros Bizjak <ubizjak@gmail.com>
+
+ PR rtl-optimization/84123
+ * combine.c (change_zero_ext): Check if hard register satisfies
+ can_change_dest_mode before calling gen_lowpart_SUBREG.
+
+2018-01-31 Vladimir Makarov <vmakarov@redhat.com>
+
+ PR target/82444
+ * ira.c (ira_init_register_move_cost): Remove assert.
+
+2018-01-31 Eric Botcazou <ebotcazou@adacore.com>
+
+ PR rtl-optimization/84071
+ * doc/tm.texi.in (WORD_REGISTER_OPERATIONS): Add explicit case.
+ * doc/tm.texi: Regenerate.
+
+2018-01-31 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/84132
+ * tree-data-ref.c (analyze_miv_subscript): Properly
+ check whether evolution_function_is_affine_multivariate_p
+ before calling gcd_of_steps_may_divide_p.
+
+2018-01-31 Julia Koval <julia.koval@intel.com>
+
+ PR target/83618
+ * config/i386/i386.c (ix86_expand_builtin): Handle IX86_BUILTIN_RDPID.
+ * config/i386/i386.md (rdpid_rex64) New.
+ (rdpid): Make 32bit only.
+
+2018-01-29 Aldy Hernandez <aldyh@redhat.com>
+
+ PR lto/84105
+ * tree-pretty-print.c (dump_generic_node): Handle a TYPE_NAME with
+ an IDENTIFIER_NODE for FUNCTION_TYPE's.
+
+2018-01-31 Eric Botcazou <ebotcazou@adacore.com>
+
+ Revert
+ 2018-01-12 Eric Botcazou <ebotcazou@adacore.com>
+
+ * config/sparc/sparc.md (vxworks_load_got): Set the GOT register.
+
+2018-01-31 Eric Botcazou <ebotcazou@adacore.com>
+
+ PR rtl-optimization/84071
+ * combine.c (record_dead_and_set_regs_1): Record the source unmodified
+ for a paradoxical SUBREG on a WORD_REGISTER_OPERATIONS target.
+
+2018-01-31 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/arc/arc.c (arc_handle_aux_attribute): New function.
+ (arc_attribute_table): Add 'aux' attribute.
+ (arc_in_small_data_p): Consider aux like variables.
+ (arc_is_aux_reg_p): New function.
+ (arc_asm_output_aligned_decl_local): Ignore 'aux' like variables.
+ (arc_get_aux_arg): New function.
+ (prepare_move_operands): Handle aux-register access.
+ (arc_handle_aux_attribute): New function.
+ * doc/extend.texi (ARC Variable attributes): Add subsection.
+
+2018-01-31 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/arc/arc-protos.h (arc_is_uncached_mem_p): Function proto.
+ * config/arc/arc.c (arc_handle_uncached_attribute): New function.
+ (arc_attribute_table): Add 'uncached' attribute.
+ (arc_print_operand): Print '.di' flag for uncached memory
+ accesses.
+ (arc_in_small_data_p): Do not consider for small data the uncached
+ types.
+ (arc_is_uncached_mem_p): New function.
+ * config/arc/predicates.md (compact_store_memory_operand): Check
+ for uncached memory accesses.
+ (nonvol_nonimm_operand): Likewise.
+ * gcc/doc/extend.texi (ARC Type Attribute): New subsection.
+
+2018-01-31 Jakub Jelinek <jakub@redhat.com>
+
+ PR c/84100
+ * common.opt (falign-functions=, falign-jumps=, falign-labels=,
+ falign-loops=): Add Optimization flag.
+
+2018-01-30 Jeff Law <law@redhat.com>
+
+ PR target/84064
+ * i386.c (ix86_adjust_stack_and_probe_stack_clash): New argument
+ INT_REGISTERS_SAVED. Check it prior to calling
+ get_scratch_register_on_entry.
+ (ix86_adjust_stack_and_probe): Similarly.
+ (ix86_emit_probe_stack_range): Similarly.
+ (ix86_expand_prologue): Corresponding changes.
+
2018-01-30 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
PR target/40411
* config/m68k/m68k.c (m68k_promote_function_mode): New function.
(TARGET_PROMOTE_FUNCTION_MODE): New macro.
-2017-01-08 Jeff Law <law@redhat.com>
+2018-01-24 Jeff Law <law@redhat.com>
PR target/83994
* i386.c (get_probe_interval): Move to earlier point.
* doc/sourcebuild.texi (arm_fp16fml_neon_ok, arm_fp16fml_neon):
Document new effective target and option set.
-2017-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+2018-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm-cpus.in (armv8_4): New feature.
(ARMv8_4a): New fgroup.
of first and second elements in UNSPEC_VPERMR vector.
(altivec_expand_vec_perm_le): Likewise.
-2017-01-08 Jeff Law <law@redhat.com>
+2018-01-08 Jeff Law <law@redhat.com>
PR rtl-optimizatin/81308
* tree-switch-conversion.c (cfg_altered): New file scoped static.
range_int_cst_p rather than !symbolic_range_p before calling
extract_range_from_multiplicative_op_1.
-2017-01-04 Jeff Law <law@redhat.com>
+2018-01-04 Jeff Law <law@redhat.com>
* tree-ssa-math-opts.c (execute_cse_reciprocals_1): Remove
redundant test in assertion.
* expmed.c (make_tree): Build VECTOR_CSTs directly from the
CONST_VECTOR encoding.
-2017-01-03 Jakub Jelinek <jakub@redhat.com>
+2018-01-03 Jakub Jelinek <jakub@redhat.com>
Jeff Law <law@redhat.com>
PR target/83641
(sprintf_dom_walker::compute_format_length): Same.
(try_substitute_return_value): Same.
-2017-01-03 Jeff Law <law@redhat.com>
+2018-01-03 Jeff Law <law@redhat.com>
PR middle-end/83654
* explow.c (anti_adjust_stack_and_probe_stack_clash): Test a
projects / platform / upstream / gcc.git / blobdiff