+2016-05-19 Martin Liska <mliska@suse.cz>
+
+ * tree-ssa-reassoc.c (eliminate_duplicate_pair): Truncate
+ an auto_vec instead of re-creating it.
+
+2016-05-19 Martin Liska <mliska@suse.cz>
+
+ * tree-ssa-loop-prefetch.c (determine_loop_nest_reuse): Use
+ auto_vec instead of vec.
+
+2016-05-19 Martin Liska <mliska@suse.cz>
+
+ * lto-section-in.c (lto_get_section_data): Call
+ lto_check_version with additional argument.
+ * lto-streamer.c (lto_check_version): Add new argument.
+ * lto-streamer.h (lto_check_version): Likewise.
+
+2016-05-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/arm/arm.c (arm_new_rtx_costs, SIGN_EXTEND case):
+ Don't add cost of inner memory when handling sign-extended
+ loads.
+
+2016-05-19 Ilya Enkovich <ilya.enkovich@intel.com>
+
+ PR rtl-optimization/71148
+ * cse.c (cse_main): Free dominance info.
+ (rest_of_handle_cse): Don't free dominance info.
+ (rest_of_handle_cse2): Likewise.
+ (rest_of_handle_cse_after_global_opts): Likewise.
+
+2016-05-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ PR target/71056
+ * config/arm/arm-builtins.c (arm_builtin_vectorized_function): Return
+ NULL_TREE early if NEON is not available. Remove now redundant check
+ in ARM_CHECK_BUILTIN_MODE.
+
+2016-05-19 Maxim Ostapenko <m.ostapenko@samsung.com>
+
+ PR sanitizer/64354
+ * cppbuiltin.c (define_builtin_macros_for_compilation_flags): Add new
+ builtin __SANITIZE_THREAD__ macros for fsanitize=thread switch.
+ * doc/cpp.texi: Document new macros.
+
+2016-05-19 Bin Cheng <bin.cheng@arm.com>
+
+ PR tree-optimization/69848
+ * tree-vect-loop.c (vectorizable_reduction): Don't factor
+ comparison expr out of VEC_COND_EXPR for COND_REDUCTION.
+
+2016-05-19 Segher Boessenkool <segher@kernel.crashing.org>
+
+ * function.c (thread_prologue_and_epilogue_insn): Move the
+ "goto epilogue_done" one block later.
+
+2016-05-19 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/70729
+ * passes.def: Move LIM pass before PRE. Remove no longer
+ required copyprop and move first DCE out of the loop pipeline.
+
+2016-05-18 David Malcolm <dmalcolm@redhat.com>
+
+ PR driver/69265
+ * Makefile.in (GCC_OBJS): Move spellcheck.o to...
+ (OBJS-libcommon-target): ...here.
+ * opts-common.c: Include spellcheck.h.
+ (cmdline_handle_error): Build a vec of valid options and use it
+ to suggest provide hints for misspelled arguments.
+
+2016-05-18 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/71100
+ * cgraph.c (cgraph_edge::redirect_call_stmt_to_callee): Don't drop
+ lhs if it has TREE_ADDRESSABLE type.
+
+2016-05-18 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/71145
+ * config/alpha/alpha.md (trap): Add (use (reg:DI 29)).
+ (*exception_receiver_1): Return "#" for TARGET_EXPLICIT_RELOCS.
+
+2016-05-18 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/69708
+ * ipa-cp.c (ipa_get_jf_pass_through_result): Allow non-ip constant
+ input for NOP_EXPR pass-through functions.
+ * ipa-prop.c (ipa_compute_jump_functions_for_edge): Allow
+ aggregate global constant VAR_DECLs in constant jump functions.
+
+2016-05-18 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/69708
+ * ipa-prop.c (parm_preserved_before_stmt_p): Return true for loads
+ from TREE_READONLY parameters.
+
+2016-05-18 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/69708
+ * cgraph.h (cgraph_indirect_call_info): New field
+ guaranteed_unmodified.
+ * ipa-cp.c (ipa_get_indirect_edge_target_1): Also pass parameter value
+ to ipa_find_agg_cst_for_param, check guaranteed_unmodified when
+ appropriate.
+ * ipa-inline-analysis.c (evaluate_conditions_for_known_args): Also
+ pass the parameter value to ipa_find_agg_cst_for_param.
+ * ipa-prop.c (ipa_load_from_parm_agg): New parameter
+ guaranteed_unmodified, store AA results there instead of bailing out
+ if present.
+ (ipa_note_param_call): Also initialize guaranteed_unmodified flag.
+ (ipa_analyze_indirect_call_uses): Also set guaranteed_unmodified flag.
+ (find_constructor_constant_at_offset): New function.
+ (ipa_find_agg_cst_from_init): Likewise.
+ (ipa_find_agg_cst_for_param): Also seearch for aggregate values in
+ static initializers of contants, report back through a new paameter
+ from_global_constant if that was the case.
+ (try_make_edge_direct_simple_call): Also pass parameter value to
+ ipa_find_agg_cst_for_param, check guaranteed_unmodified when
+ appropriate.
+ (ipa_write_indirect_edge_info): Stream new flag guaranteed_unmodified.
+ (ipa_read_indirect_edge_info): Likewise.
+ * ipa-prop.h (ipa_find_agg_cst_for_param): Update declaration.
+ (ipa_load_from_parm_agg): Likewise.
+
+2016-05-18 Jiong Wang <jiong.wang@arm.com>
+
+ PR rtl-optimization/71150
+ * lra-constraint (process_addr_reg): Guard "in_class_p" with REG_P
+ check.
+
+2016-05-18 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ PR target/70915
+ * config/rs6000/constraints.md (wE constraint): New constraint
+ for a vector constant that can be loaded with XXSPLTIB.
+ (wM constraint): New constraint for a vector constant of a 1's.
+ (wS constraint): New constraint for a vector constant that can be
+ loaded with XXSPLTIB and a vector sign extend instruction.
+ * config/rs6000/predicates.md (xxspltib_constant_split): New
+ predicates for wE/wS constraints.
+ (xxspltib_constant_nosplit): Likewise.
+ (easy_vector_constant): Add support for constants that can be
+ loaded via XXSPLTIB.
+ (all_ones_constant): New predicate for vector constant with all
+ 1's set.
+ (splat_input_operand): Add support for ISA 3.0 word splat operations.
+ * config/rs6000/rs6000.c (xxspltib_constant_p): New function to
+ return if a constant can be loaded with the ISA 3.0 XXSPLTIB
+ instruction and possibly with a sign extension.
+ (output_vec_const_move): Add support for XXSPLTIB. If we are
+ loading up 0/-1 into Altivec registers, prefer using VSPLTISW
+ instead of XXLXOR/XXLORC.
+ (rs6000_expand_vector_init): Add support for ISA 3.0 word splat
+ operations.
+ (rs6000_legitimize_reload_address): Likewise.
+ (rs6000_output_move_128bit): Use output_vec_const_move to emit
+ constants.
+ * config/rs6000/vsx.md (VSX_M): Add TImode (if -mvsx-timode) and
+ combine VSX_M and VSX_M2 into one iterator.
+ (VSX_M2): Likewise.
+ (VSINT_84): New iterators for loading constants with XXSPLTIB.
+ (VSINT_842): Likewise.
+ (UNSPEC_VSX_SIGN_EXTEND): New UNSPEC.
+ (xxspltib_v16qi): New insns to load up constants with the ISA 3.0
+ XXSPLTIB instruction.
+ (xxspltib_<mode>_nosplit): Likewise.
+ (xxspltib_<mode>_split): New insn to load up constants with
+ XXSPLTIB and a sign extend instruction.
+ (vsx_mov<mode>): Replace single move that handled all vector types
+ with separate 32-bit and 64-bit moves. Combine the movti_<bit>
+ moves (when -mvsx-timode is in effect) into the main vector
+ moves. Eliminate separate moves for <VSr> <VSa>, where the
+ preferred register class (<VSr>) is listed first, and the
+ secondary register class (<VSa>) is listed second with a '?' to
+ discourage use. Prefer loading 0/-1 in any VSX register for ISA
+ 3.0, and Altivec registers for ISA 2.06/2.07 (PR target/70915) so
+ that if the register was involved in a slow operation, the
+ clear/set operation does not wait for the slow operation to
+ finish. Adjust the length attributes for 32-bit mode. Use
+ rs6000_output_move_128bit and drop the use of the string
+ instructions for 32-bit movti when -mvsx-timode is in effect. Use
+ spacing so that the alternatives and attributes don't generate
+ long lines, and put things in columns, so that it is easier to
+ match up the operands and attributes with the insn alternatives.
+ (vsx_mov<mode>_64bit): Likewise.
+ (vsx_mov<mode>_32bit): Likewise.
+ (vsx_movti_64bit): Fold movti into normal vector moves.
+ (vsx_movti_32bit): Likewise.
+ (vsx_splat_<mode>, V4SI/V4SF modes): Add support for ISA 3.0 word
+ splat instructions.
+ (vsx_splat_v4si_internal): Likewise.
+ (vsx_splat_v4sf_internal): Likewise.
+ (vector fusion peepholes): Use VSX_M instead of VSX_M2.
+ (vsx_sign_extend_qi_<mode>): New ISA 3.0 instructions to sign
+ extend vector elements.
+ (vsx_sign_extend_hi_<mode>): Likewise.
+ (vsx_sign_extend_si_v2di): Likewise.
+ * config/rs6000/rs6000-protos.h (xxspltib_constant_p): Add
+ declaration.
+ * doc/md.texi (PowerPC constraints): Document the wE, wM, and wS
+ constraints. Add trailing period to wL documentation.
+
+2016-05-18 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR middle-end/71020
+ * tree-dfa.h (replace_abnormal_ssa_names): Declare.
+ * tree-dfa.c (replace_abnormal_ssa_names): New function.
+ * tree-call-cdce.c: Include tree-dfa.h.
+ (can_guard_call_p): New function, extracted from...
+ (can_use_internal_fn): ...here.
+ (shrink_wrap_one_built_in_call_with_conds): Remove failure path
+ and return void.
+ (shrink_wrap_one_built_in_call): Likewise.
+ (use_internal_fn): Likewise.
+ (shrink_wrap_conditional_dead_built_in_calls): Update accordingly
+ and return void. Call replace_abnormal_ssa_names.
+ (pass_call_cdce::execute): Check can_guard_call_p during the
+ initial walk. Assume shrink_wrap_conditional_dead_built_in_calls
+ will always change something.
+
+2016-05-18 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/70646
+ * ipa-prop.c (determine_locally_known_aggregate_parts): Bail out early
+ if parameter PARAM_IPA_MAX_AGG_ITEMS is zero.
+
+2016-05-18 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/70646
+ * ipa-inline.h (condition): New field size.
+ * ipa-inline-analysis.c (add_condition): New parameter SIZE, use it
+ for comaprison and store it into the new condition.
+ (evaluate_conditions_for_known_args): Use condition size to check
+ access sizes for all but CHANGED conditions.
+ (unmodified_parm_1): New parameter size_p, store access size into it.
+ (unmodified_parm): Likewise.
+ (unmodified_parm_or_parm_agg_item): Likewise.
+ (eliminated_by_inlining_prob): Pass NULL to unmodified_parm as size_p.
+ (set_cond_stmt_execution_predicate): Extract access sizes and store
+ them to conditions.
+ (set_switch_stmt_execution_predicate): Likewise.
+ (will_be_nonconstant_expr_predicate): Likewise.
+ (will_be_nonconstant_predicate): Likewise.
+ (inline_read_section): Stream condition size.
+ (inline_write_summary): Likewise.
+
+2016-05-18 Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-loop-im.c (determine_max_movement): Properly add
+ condition cost to PHI cost instead of total_cost.
+
2016-05-18 Martin Liska <mliska@suse.cz>
PR fortran/70856
2016-05-18 Kirill Yukhin <kirill.yukhin@intel.com>
- * gcc/config/i386/sse.md (define_insn "*andnot<mode>3"): Extend static
+ * gcc/config/i386/sse.md (define_insn "*andnot<mode>3"): Extend static
array to 128 chars.
(define_insn "*andnottf3"): Ditto.
(define_insn "*<code><mode>3"/any_logic): Ditto.
2016-05-18 Petr Murzin <petr.murzin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
- * config/i386/sse.md (define_insn "srcp14<mode>"): Use proper operand
+ * config/i386/sse.md (define_insn "srcp14<mode>"): Use proper operand
modifiers.
(define_insn "rsqrt14<mode>"): Ditto.
(define_insn "<mask_codefor>avx512dq_cvtps2qqv2di<mask_name>"): Ditto.
2016-05-17 Kugan Vivekanandarajah <kuganv@linaro.org>
- * config/aarch64/aarch64.c (all_extensions): Removed unused static variable.
+ * config/aarch64/aarch64.c (all_extensions): Removed unused
+ static variable.
2016-05-17 Nathan Sidwell <nathan@acm.org>
2016-05-17 Jiong Wang <jiong.wang@arm.com>
- * config/aarch64/aarch64-simd.md (*aarch64_mul3_elt_to_128df): Extend to
- all supported modes. Rename to "*aarch64_mul3_elt_from_dup".
+ * config/aarch64/aarch64-simd.md (*aarch64_mul3_elt_to_128df): Extend
+ to all supported modes. Rename to "*aarch64_mul3_elt_from_dup".
2016-05-17 Jiong Wang <jiong.wang@arm.com>
2016-05-17 Gerald Pfeifer <gerald@pfeifer.com>
* wide-int.h: Change fixed_wide_int_storage from class to struct.
-
+
2016-05-17 Richard Biener <rguenther@suse.de>
PR tree-optimization/71132
2016-05-16 Wilco Dijkstra <wdijkstr@arm.com>
- * doc/invoke.texi (AArch64 Options): Various updates.
+ * doc/invoke.texi (AArch64 Options): Various updates.
2016-05-16 Jan Hubicka <hubicka@ucw.cz>
2016-05-13 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
- PR target/53440
- * config/arm/arm.c (arm32_output_mi_thunk): New.
- (arm_output_mi_thunk): Rename to arm_thumb1_mi_thunk. Rework
- to split Thumb1 vs TARGET_32BIT functionality.
- (arm_thumb1_mi_thunk): New.
+ PR target/53440
+ * config/arm/arm.c (arm32_output_mi_thunk): New.
+ (arm_output_mi_thunk): Rename to arm_thumb1_mi_thunk. Rework
+ to split Thumb1 vs TARGET_32BIT functionality.
+ (arm_thumb1_mi_thunk): New.
2016-05-13 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2016-05-04 Aaron Sawdey <acsawdey@linux.vnet.ibm.com>
- * config/rs6000/rs6000.c (rs6000_reassociation_width): Add
- function for TARGET_SCHED_REASSOCIATION_WIDTH to enable
- parallel reassociation for power8 and forward.
+ * config/rs6000/rs6000.c (rs6000_reassociation_width): Add
+ function for TARGET_SCHED_REASSOCIATION_WIDTH to enable
+ parallel reassociation for power8 and forward.
2016-05-09 Uros Bizjak <ubizjak@gmail.com>
projects / platform / upstream / gcc.git / blobdiff