arm.opt (masm-syntax-unified): New option.
[platform/upstream/gcc.git] / gcc / ChangeLog
index e254dc2..2aa7278 100644 (file)
@@ -1,3 +1,136 @@
+2014-11-07  Terry Guo  <terry.guo@arm.com>
+
+       * config/arm/arm.opt (masm-syntax-unified): New option.
+       * doc/invoke.texi (-masm-syntax-unified): Document new option.
+       * config/arm/arm.h (TARGET_UNIFIED_ASM): Also include thumb1.
+       (ASM_APP_ON): Redefined.
+       * config/arm/arm.c (arm_option_override): Thumb2 inline assembly
+       code always use UAL syntax.
+       (arm_output_mi_thunk): Use UAL syntax for Thumb1 target.
+       * config/arm/thumb1.md: Likewise.
+
+2014-11-06  John David Anglin  <danglin@gcc.gnu.org>
+
+       * config/pa/pa.md (trap): New insn.  Add "trap" to attribute type.
+       Don't allow trap insn in in_branch_delay, in_nullified_branch_delay
+       or in_call_delay.
+       
+2014-11-06  Steve Ellcey  <sellcey@imgtec.com>
+
+       * config.gcc (mips*-mti-linux*): Remove gnu_ld and gas assignments.
+       Set default_mips_arch and default_mips_abi instead of tm_defines.
+       (mips*-*-linux*): Set default_mips_arch and default_mips_abi instead
+       of tm_defines.
+       (mips*-*-*): Check with_arch and with_abi.  Set tm_defines.
+       * config/mips/mips.h (STANDARD_STARTFILE_PREFIX_1): Set default
+       based on MIPS_ABI_DEFAULT.
+       (STANDARD_STARTFILE_PREFIX_2): Ditto.
+
+2014-11-06  Joseph Myers  <joseph@codesourcery.com>
+
+       * doc/invoke.texi (-std=c99, -std=c11): Don't refer to corner
+       cases of extended identifiers.
+
+2014-11-06  Eric Botcazou  <ebotcazou@adacore.com>
+
+       * tree-cfgcleanup.c (fixup_noreturn_call): Do not perform DCE here.
+
+2014-11-06  DJ Delorie  <dj@redhat.com>
+
+       * config/m32c/cond.md (movqicc_<code>_<mode>): Remove mode of
+       conditional.
+       (movhicc_<code>_<mode>): Likewise.
+       * config/m32c/m32c.c (encode_pattern_1): Specialise PSImode
+       subregs.
+       (m32c_eh_return_data_regno): Change to using memregs to avoid
+       tying up all the compute regs.
+       (m32c_legitimate_address_p) Subregs are not valid addresses.
+
+2014-11-06  Bernd Schmidt  <bernds@codesourcery.com>
+
+       * target.def (call_args, end_call_args): New hooks.
+       * hooks.c (hook_void_rtx_tree): New empty function.
+       * hooks.h (hook_void_rtx_tree): Declare.
+       * doc/tm.texi.in (TARGET_CALL_ARGS, TARGET_END_CALL_ARGS): Add.
+       * doc/tm.texi: Regenerate.
+       * calls.c (expand_call): Slightly rearrange the code.  Use the two new
+       hooks.
+       (expand_library_call_value_1): Use the two new hooks.
+
+       * expr.c (use_reg_mode): Just return for pseudo registers.
+
+       * combine.c (try_combine): Don't allow a call as one of the source
+       insns.
+
+       * target.def (decl_end): New hook.
+       * varasm.c (assemble_variable_contents, assemble_constant_contents):
+       Use it.
+       * doc/tm.texi.in (TARGET_ASM_DECL_END): Add.
+       * doc/tm.texi: Regenerate.
+
+2014-11-06  Renlin Li  <renlin.li@arm.com>
+
+       * config/aarch64/aarch64.c (aarch64_architecture_version): New.
+       (processor): New architecture_version field.
+       (aarch64_override_options): Initialize aarch64_architecture_version.
+       * config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_ARCH,
+       __ARM_ARCH_PROFILE, aarch64_arch_name macro.
+
+2014-11-06  James Greenhalgh  <james.greenhalgh@arm.com>
+
+       * params.def (sra-max-scalarization-size-Ospeed): New.
+       (sra-max-scalarization-size-Osize): Likewise.
+       * doc/invoke.texi (sra-max-scalarization-size-Ospeed): Document.
+       (sra-max-scalarization-size-Osize): Likewise.
+       * toplev.c (process_options): Set default values for new
+       parameters.
+       * tree-sra.c (analyze_all_variable_accesses): Use new parameters.
+       * targhooks.c (get_move_ratio): Remove static designator.
+       * target.h (get_move_ratio): Declare.
+
+2014-11-06  Marek Polacek  <polacek@redhat.com>
+
+       * sanopt.c (sanopt_optimize_walker): Limit removal of the checks.
+       Remove vector limit.
+
+2014-11-06  Richard Biener  <rguenther@suse.de>
+
+       * match.pd: Implement bitwise binary and unary simplifications
+       from tree-ssa-forwprop.c.
+       * fold-const.c (fold_unary_loc): Remove them here.
+       (fold_binary_loc): Likewise.
+       * tree-ssa-forwprop.c (simplify_not_neg_expr): Remove.
+       (truth_valued_ssa_name): Likewise.
+       (lookup_logical_inverted_value): Likewise.
+       (simplify_bitwise_binary_1): Likewise.
+       (hoist_conversion_for_bitop_p): Likewise.
+       (simplify_bitwise_binary_boolean): Likewise.
+       (simplify_bitwise_binary): Likewise.
+       (pass_forwprop::execute): Remove calls to simplify_not_neg_expr
+       and simplify_bitwise_binary.
+       * genmatch.c (dt_node::append_true_op): Use safe_as_a for parent.
+       (decision_tree::insert): Also insert non-expressions.
+
+2014-11-06  Hale Wang  <hale.wang@arm.com>
+
+       * config/arm/arm-cores.def: Add support for
+       -mcpu=cortex-m0.small-multiply,cortex-m0plus.small-multiply,
+       cortex-m1.small-multiply.
+       * config/arm/arm-tables.opt: Regenerate.
+       * config/arm/arm-tune.md: Regenerate.
+       * config/arm/arm.c: Update the rtx-costs for MUL.
+       * config/arm/bpabi.h: Handle
+       -mcpu=cortex-m0.small-multiply,cortex-m0plus.small-multiply,
+       cortex-m1.small-multiply.
+       * doc/invoke.texi: Document
+       -mcpu=cortex-m0.small-multiply,cortex-m0plus.small-multiply,
+       cortex-m1.small-multiply.
+
+2014-11-06  Hale Wang  <hale.wang@arm.com>
+
+       * config/arm/arm.c: Add cortex-m7 tune.
+       * config/arm/arm-cores.def: Use cortex-m7 tune.
+
 2014-11-05  Uros Bizjak  <ubizjak@gmail.com>
 
        PR target/63538