include/

[external/binutils.git] / gas / testsuite / gas / ppc / test1xcoff32.d

diff --git a/gas/testsuite/gas/ppc/test1xcoff32.d b/gas/testsuite/gas/ppc/test1xcoff32.d
index 6bbea53..56de4d4 100644 (file)
--- a/gas/testsuite/gas/ppc/test1xcoff32.d
+++ b/gas/testsuite/gas/ppc/test1xcoff32.d
@@ -10,7 +10,7 @@ start address 0x0+0000
 
 Sections:
 Idx Name +Size +VMA +LMA +File off +Algn
-  0 \.text +00000068  0+0000  0+0000  000000a8  2\*\*3
+  0 \.text +00000068  0+0000  0+0000  000000a8  2\*\*2
  +CONTENTS, ALLOC, LOAD, RELOC, CODE
   1 \.data +00000028  0+0068  0+0068  00000110  2\*\*3
  +CONTENTS, ALLOC, LOAD, RELOC, DATA
@@ -64,50 +64,50 @@ Disassembly of section \.text:
    4:  00 be ef ed     \.long 0xbeefed
 
 0+0008 <reference_csect_relative_symbols>:
-   8:  80 63 00 00     l       r3,0\(r3\)
-   c:  80 63 00 04     l       r3,4\(r3\)
-  10:  80 63 00 04     l       r3,4\(r3\)
-  14:  80 63 00 00     l       r3,0\(r3\)
+   8:  80 63 00 00     l       r3,0\(r3\)
+   c:  80 63 00 04     l       r3,4\(r3\)
+  10:  80 63 00 04     l       r3,4\(r3\)
+  14:  80 63 00 00     l       r3,0\(r3\)
 
 0+0018 <dubious_references_to_default_RW_csect>:
-  18:  80 63 00 00     l       r3,0\(r3\)
-  1c:  80 63 00 04     l       r3,4\(r3\)
-  20:  80 63 00 04     l       r3,4\(r3\)
-  24:  80 63 00 08     l       r3,8\(r3\)
+  18:  80 63 00 00     l       r3,0\(r3\)
+  1c:  80 63 00 04     l       r3,4\(r3\)
+  20:  80 63 00 04     l       r3,4\(r3\)
+  24:  80 63 00 08     l       r3,8\(r3\)
 
 0+0028 <reference_via_toc>:
-  28:  80 62 00 0c     l       r3,12\(r2\)
+  28:  80 62 00 00     l       r3,0\(r2\)
                        2a: R_TOC       ignored0\+0xf+ff8c
-  2c:  80 62 00 10     l       r3,16\(r2\)
+  2c:  80 62 00 04     l       r3,4\(r2\)
                        2e: R_TOC       ignored1\+0xf+ff88
-  30:  80 62 00 14     l       r3,20\(r2\)
+  30:  80 62 00 08     l       r3,8\(r2\)
                        32: R_TOC       ignored2\+0xf+ff84
-  34:  80 62 00 18     l       r3,24\(r2\)
+  34:  80 62 00 0c     l       r3,12\(r2\)
                        36: R_TOC       ignored3\+0xf+ff80
-  38:  80 62 00 1c     l       r3,28\(r2\)
+  38:  80 62 00 10     l       r3,16\(r2\)
                        3a: R_TOC       ignored4\+0xf+ff7c
-  3c:  80 62 00 20     l       r3,32\(r2\)
+  3c:  80 62 00 14     l       r3,20\(r2\)
                        3e: R_TOC       ignored5\+0xf+ff78
 
 0+0040 <subtract_symbols>:
-  40:  38 60 00 04     lil     r3,4
-  44:  38 60 ff fc     lil     r3,-4
-  48:  38 60 00 04     lil     r3,4
-  4c:  38 60 ff fc     lil     r3,-4
-  50:  38 60 ff fc     lil     r3,-4
-  54:  38 60 00 04     lil     r3,4
-  58:  80 64 00 04     l       r3,4\(r4\)
+  40:  38 60 00 04     lil     r3,4
+  44:  38 60 ff fc     lil     r3,-4
+  48:  38 60 00 04     lil     r3,4
+  4c:  38 60 ff fc     lil     r3,-4
+  50:  38 60 ff fc     lil     r3,-4
+  54:  38 60 00 04     lil     r3,4
+  58:  80 64 00 04     l       r3,4\(r4\)
 
 0+005c <load_addresses>:
-  5c:  38 60 00 00     lil     r3,0
-  60:  38 60 00 04     lil     r3,4
-  64:  38 62 00 24     cal     r3,36\(r2\)
+  5c:  38 60 00 00     lil     r3,0
+  60:  38 60 00 04     lil     r3,4
+  64:  38 62 00 18     cal     r3,24\(r2\)
                        66: R_TOC       ignored6\+0xf+ff74
 Disassembly of section \.data:
 
 0+0068 <TOC-0xc>:
-  68:  de ad be ef     stfdu   f21,-16657\(r13\)
-  6c:  ca fe ba be     lfd     f23,-17730\(r30\)
+  68:  de ad be ef     stfdu   f21,-16657\(r13\)
+  6c:  ca fe ba be     lfd     f23,-17730\(r30\)
   70:  00 00 ba ad     \.long 0xbaad
 
 0+0074 <TOC>: