Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcn

[platform/upstream/binutils.git] / gas / testsuite / gas / i386 / x86-64-mpx.d

diff --git a/gas/testsuite/gas/i386/x86-64-mpx.d b/gas/testsuite/gas/i386/x86-64-mpx.d
index cef040c..b798649 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-mpx.d
+++ b/gas/testsuite/gas/i386/x86-64-mpx.d
@@ -6,7 +6,7 @@
 
 Disassembly of section .text:
 
-0+ <foo-0x434>:
+0+ <start>:
 [      ]*[a-f0-9]+:    f3 41 0f 1b 0b          bndmk  \(%r11\),%bnd1
 [      ]*[a-f0-9]+:    f3 0f 1b 08             bndmk  \(%rax\),%bnd1
 [      ]*[a-f0-9]+:    f3 0f 1b 0c 25 99 03 00 00      bndmk  0x399,%bnd1
@@ -38,9 +38,8 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    66 0f 1a d0             bndmov %bnd0,%bnd2
 [      ]*[a-f0-9]+:    f3 41 0f 1a 0b          bndcl  \(%r11\),%bnd1
 [      ]*[a-f0-9]+:    f3 0f 1a 08             bndcl  \(%rax\),%bnd1
-[      ]*[a-f0-9]+:    f3 49 0f 1a cb          bndcl  %r11,%bnd1
-[      ]*[a-f0-9]+:    f3 48 0f 1a c9          bndcl  %rcx,%bnd1
-[      ]*[a-f0-9]+:    f3 0f 1a c8             bndcl  %eax,%bnd1
+[      ]*[a-f0-9]+:    f3 41 0f 1a cb          bndcl  %r11,%bnd1
+[      ]*[a-f0-9]+:    f3 0f 1a c9             bndcl  %rcx,%bnd1
 [      ]*[a-f0-9]+:    f3 0f 1a 0c 25 99 03 00 00      bndcl  0x399,%bnd1
 [      ]*[a-f0-9]+:    f3 41 0f 1a 51 03       bndcl  0x3\(%r9\),%bnd2
 [      ]*[a-f0-9]+:    f3 0f 1a 50 03          bndcl  0x3\(%rax\),%bnd2
@@ -50,9 +49,8 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    f3 42 0f 1a 4c 0b 03    bndcl  0x3\(%rbx,%r9,1\),%bnd1
 [      ]*[a-f0-9]+:    f2 41 0f 1a 0b          bndcu  \(%r11\),%bnd1
 [      ]*[a-f0-9]+:    f2 0f 1a 08             bndcu  \(%rax\),%bnd1
-[      ]*[a-f0-9]+:    f2 49 0f 1a cb          bndcu  %r11,%bnd1
-[      ]*[a-f0-9]+:    f2 48 0f 1a c9          bndcu  %rcx,%bnd1
-[      ]*[a-f0-9]+:    f2 0f 1a c8             bndcu  %eax,%bnd1
+[      ]*[a-f0-9]+:    f2 41 0f 1a cb          bndcu  %r11,%bnd1
+[      ]*[a-f0-9]+:    f2 0f 1a c9             bndcu  %rcx,%bnd1
 [      ]*[a-f0-9]+:    f2 0f 1a 0c 25 99 03 00 00      bndcu  0x399,%bnd1
 [      ]*[a-f0-9]+:    f2 41 0f 1a 51 03       bndcu  0x3\(%r9\),%bnd2
 [      ]*[a-f0-9]+:    f2 0f 1a 50 03          bndcu  0x3\(%rax\),%bnd2
@@ -62,9 +60,8 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    f2 42 0f 1a 4c 0b 03    bndcu  0x3\(%rbx,%r9,1\),%bnd1
 [      ]*[a-f0-9]+:    f2 41 0f 1b 0b          bndcn  \(%r11\),%bnd1
 [      ]*[a-f0-9]+:    f2 0f 1b 08             bndcn  \(%rax\),%bnd1
-[      ]*[a-f0-9]+:    f2 49 0f 1b cb          bndcn  %r11,%bnd1
-[      ]*[a-f0-9]+:    f2 48 0f 1b c9          bndcn  %rcx,%bnd1
-[      ]*[a-f0-9]+:    f2 0f 1b c8             bndcn  %eax,%bnd1
+[      ]*[a-f0-9]+:    f2 41 0f 1b cb          bndcn  %r11,%bnd1
+[      ]*[a-f0-9]+:    f2 0f 1b c9             bndcn  %rcx,%bnd1
 [      ]*[a-f0-9]+:    f2 0f 1b 0c 25 99 03 00 00      bndcn  0x399,%bnd1
 [      ]*[a-f0-9]+:    f2 41 0f 1b 51 03       bndcn  0x3\(%r9\),%bnd2
 [      ]*[a-f0-9]+:    f2 0f 1b 50 03          bndcn  0x3\(%rax\),%bnd2
@@ -88,11 +85,11 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    0f 1a 14 1d 03 00 00 00         bndldx 0x3\(,%rbx,1\),%bnd2
 [      ]*[a-f0-9]+:    42 0f 1a 14 25 03 00 00 00      bndldx 0x3\(,%r12,1\),%bnd2
 [      ]*[a-f0-9]+:    0f 1a 0a                bndldx \(%rdx\),%bnd1
-[      ]*[a-f0-9]+:    f2 e8 34 02 00 00       bnd callq 434 <foo>
+[      ]*[a-f0-9]+:    f2 e8 25 02 00 00       bnd callq 416 <foo>
 [      ]*[a-f0-9]+:    f2 ff 10                bnd callq \*\(%rax\)
 [      ]*[a-f0-9]+:    f2 41 ff 13             bnd callq \*\(%r11\)
-[      ]*[a-f0-9]+:    f2 0f 84 26 02 00 00    bnd je 434 <foo>
-[      ]*[a-f0-9]+:    f2 e9 20 02 00 00       bnd jmpq 434 <foo>
+[      ]*[a-f0-9]+:    f2 0f 84 17 02 00 00    bnd je 416 <foo>
+[      ]*[a-f0-9]+:    f2 e9 11 02 00 00       bnd jmpq 416 <foo>
 [      ]*[a-f0-9]+:    f2 ff 21                bnd jmpq \*\(%rcx\)
 [      ]*[a-f0-9]+:    f2 41 ff 24 24          bnd jmpq \*\(%r12\)
 [      ]*[a-f0-9]+:    f2 c3                   bnd retq 
@@ -127,9 +124,8 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    66 0f 1a d0             bndmov %bnd0,%bnd2
 [      ]*[a-f0-9]+:    f3 41 0f 1a 0b          bndcl  \(%r11\),%bnd1
 [      ]*[a-f0-9]+:    f3 0f 1a 08             bndcl  \(%rax\),%bnd1
-[      ]*[a-f0-9]+:    f3 49 0f 1a cb          bndcl  %r11,%bnd1
-[      ]*[a-f0-9]+:    f3 48 0f 1a c9          bndcl  %rcx,%bnd1
-[      ]*[a-f0-9]+:    f3 0f 1a c8             bndcl  %eax,%bnd1
+[      ]*[a-f0-9]+:    f3 41 0f 1a cb          bndcl  %r11,%bnd1
+[      ]*[a-f0-9]+:    f3 0f 1a c9             bndcl  %rcx,%bnd1
 [      ]*[a-f0-9]+:    f3 0f 1a 0c 25 99 03 00 00      bndcl  0x399,%bnd1
 [      ]*[a-f0-9]+:    f3 41 0f 1a 49 03       bndcl  0x3\(%r9\),%bnd1
 [      ]*[a-f0-9]+:    f3 0f 1a 48 03          bndcl  0x3\(%rax\),%bnd1
@@ -139,9 +135,8 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    f3 42 0f 1a 4c 0b 03    bndcl  0x3\(%rbx,%r9,1\),%bnd1
 [      ]*[a-f0-9]+:    f2 41 0f 1a 0b          bndcu  \(%r11\),%bnd1
 [      ]*[a-f0-9]+:    f2 0f 1a 08             bndcu  \(%rax\),%bnd1
-[      ]*[a-f0-9]+:    f2 49 0f 1a cb          bndcu  %r11,%bnd1
-[      ]*[a-f0-9]+:    f2 48 0f 1a c9          bndcu  %rcx,%bnd1
-[      ]*[a-f0-9]+:    f2 0f 1a c8             bndcu  %eax,%bnd1
+[      ]*[a-f0-9]+:    f2 41 0f 1a cb          bndcu  %r11,%bnd1
+[      ]*[a-f0-9]+:    f2 0f 1a c9             bndcu  %rcx,%bnd1
 [      ]*[a-f0-9]+:    f2 0f 1a 0c 25 99 03 00 00      bndcu  0x399,%bnd1
 [      ]*[a-f0-9]+:    f2 41 0f 1a 49 03       bndcu  0x3\(%r9\),%bnd1
 [      ]*[a-f0-9]+:    f2 0f 1a 48 03          bndcu  0x3\(%rax\),%bnd1
@@ -151,9 +146,8 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    f2 42 0f 1a 4c 0b 03    bndcu  0x3\(%rbx,%r9,1\),%bnd1
 [      ]*[a-f0-9]+:    f2 41 0f 1b 0b          bndcn  \(%r11\),%bnd1
 [      ]*[a-f0-9]+:    f2 0f 1b 08             bndcn  \(%rax\),%bnd1
-[      ]*[a-f0-9]+:    f2 49 0f 1b cb          bndcn  %r11,%bnd1
-[      ]*[a-f0-9]+:    f2 48 0f 1b c9          bndcn  %rcx,%bnd1
-[      ]*[a-f0-9]+:    f2 0f 1b c8             bndcn  %eax,%bnd1
+[      ]*[a-f0-9]+:    f2 41 0f 1b cb          bndcn  %r11,%bnd1
+[      ]*[a-f0-9]+:    f2 0f 1b c9             bndcn  %rcx,%bnd1
 [      ]*[a-f0-9]+:    f2 0f 1b 0c 25 99 03 00 00      bndcn  0x399,%bnd1
 [      ]*[a-f0-9]+:    f2 41 0f 1b 49 03       bndcn  0x3\(%r9\),%bnd1
 [      ]*[a-f0-9]+:    f2 0f 1b 48 03          bndcn  0x3\(%rax\),%bnd1
@@ -177,15 +171,15 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    0f 1a 14 1d 03 00 00 00         bndldx 0x3\(,%rbx,1\),%bnd2
 [      ]*[a-f0-9]+:    42 0f 1a 14 25 03 00 00 00      bndldx 0x3\(,%r12,1\),%bnd2
 [      ]*[a-f0-9]+:    0f 1a 0a                bndldx \(%rdx\),%bnd1
-[      ]*[a-f0-9]+:    f2 e8 16 00 00 00       bnd callq 434 <foo>
+[      ]*[a-f0-9]+:    f2 e8 16 00 00 00       bnd callq 416 <foo>
 [      ]*[a-f0-9]+:    f2 ff d0                bnd callq \*%rax
 [      ]*[a-f0-9]+:    f2 41 ff d3             bnd callq \*%r11
-[      ]*[a-f0-9]+:    f2 74 0c                bnd je 434 <foo>
-[      ]*[a-f0-9]+:    f2 eb 09                bnd jmp 434 <foo>
+[      ]*[a-f0-9]+:    f2 74 0c                bnd je 416 <foo>
+[      ]*[a-f0-9]+:    f2 eb 09                bnd jmp 416 <foo>
 [      ]*[a-f0-9]+:    f2 ff e1                bnd jmpq \*%rcx
 [      ]*[a-f0-9]+:    f2 41 ff e4             bnd jmpq \*%r12
 [      ]*[a-f0-9]+:    f2 c3                   bnd retq 
 
-0+434 <foo>:
+[a-f0-9]+ <foo>:
 [      ]*[a-f0-9]+:    f2 c3                   bnd retq 
 #pass