* doc/c-i386.texi (i386-Mnemonics): Fix typo.

[platform/upstream/binutils.git] / gas / doc / c-mips.texi

diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 1fbe180..1375230 100644 (file)
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -1,4 +1,5 @@
-@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000
+@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
+@c 2002, 2003, 2004
 @c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
@@ -28,6 +29,8 @@ Assembly Language Programming'' in the same work.
 * MIPS autoextend::    Directives for extending MIPS 16 bit instructions
 * MIPS insn::          Directive to mark data as an instruction
 * MIPS option stack::  Directives to save and restore options
+* MIPS ASE instruction generation overrides:: Directives to control
+                       generation of MIPS ASE instructions
 @end menu
 
 @node MIPS Opts
@@ -63,14 +66,19 @@ to select big-endian output, and @samp{-EL} for little-endian.
 @itemx -mips4
 @itemx -mips5
 @itemx -mips32
+@itemx -mips32r2
 @itemx -mips64
+@itemx -mips64r2
 Generate code for a particular MIPS Instruction Set Architecture level.
 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
 @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
-@sc{r10000} processors.  @samp{-mips5}, @samp{-mips32}, and
-@samp{-mips64} correspond to generic @sc{MIPS V}, @sc{MIPS32}, and
-@sc{MIPS64} ISA processors, respectively.  You can also switch
+@sc{r10000} processors.  @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2},
+@samp{-mips64}, and @samp{-mips64r2}
+correspond to generic
+@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64},
+and @sc{MIPS64 Release 2}
+ISA processors, respectively.  You can also switch
 instruction sets during the assembly; see @ref{MIPS ISA, Directives to
 override the ISA level}.
 
@@ -103,11 +111,23 @@ Generate code for the MIPS-3D Application Specific Extension.
 This tells the assembler to accept MIPS-3D instructions.
 @samp{-no-mips3d} turns off this option.
 
+@item -mdmx
+@itemx -no-mdmx
+Generate code for the MDMX Application Specific Extension.
+This tells the assembler to accept MDMX instructions.
+@samp{-no-mdmx} turns off this option.
+
 @item -mfix7000
-@itemx -no-mfix7000
+@itemx -mno-fix7000
 Cause nops to be inserted if the read of the destination register
 of an mfhi or mflo instruction occurs in the following two instructions.
 
+@item -mfix-vr4120
+@itemx -no-mfix-vr4120
+Insert nops to work around certain VR4120 errata.  This option is
+intended to be used on GCC-generated code: it is not designed to catch
+all problems in hand-written assembler code.
+
 @item -m4010
 @itemx -no-m4010
 Generate code for the LSI @sc{r4010} chip.  This tells the assembler to
@@ -144,6 +164,9 @@ understood.  Valid @var{cpu} value are:
 4010,
 4100,
 4111,
+vr4120,
+vr4130,
+vr4181,
 4300,
 4400,
 4600,
@@ -154,9 +177,12 @@ rm5230,
 rm5231,
 rm5261,
 rm5721,
+vr5400,
+vr5500,
 6000,
 rm7000,
 8000,
+rm9000,
 10000,
 12000,
 mips32-4k,
@@ -167,12 +193,9 @@ sb1
 Schedule and tune for a particular MIPS cpu.  Valid @var{cpu} values are
 identical to @samp{-march=@var{cpu}}.
 
-@item -mcpu=@var{cpu}
-Generate code and schedule for a particular MIPS cpu.  This is exactly
-equivalent to @samp{-march=@var{cpu}} and @samp{-mtune=@var{cpu}}.  Valid
-@var{cpu} values are identical to @samp{-march=@var{cpu}}.
-Use of this option is discouraged.
-
+@item -mabi=@var{abi}
+Record which ABI the source code uses.  The recognized arguments
+are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
 
 @cindex @code{-nocpp} ignored (MIPS)
 @item -nocpp
@@ -211,9 +234,10 @@ are only supported at Instruction Set Architecture level 2 and higher.
 Generate code to take a break exception rather than a trap exception when an
 error is detected.  This is the default.
 
-@item -n
-When this option is used, @code{@value{AS}} will issue a warning every
-time it generates a nop instruction from a macro.
+@item -mpdr
+@itemx -mno-pdr
+Control generation of @code{.pdr} sections.  Off by default on IRIX, on
+elsewhere.
 @end table
 
 @node MIPS Object
@@ -270,8 +294,9 @@ assembly language programmers!
 @kindex @code{.set mips@var{n}}
 @sc{gnu} @code{@value{AS}} supports an additional directive to change
 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
-mips@var{n}}.  @var{n} should be a number from 0 to 5, or 32 or 64.
-The values 1 to 5, 32, and 64 make the assembler accept instructions
+mips@var{n}}.  @var{n} should be a number from 0 to 5, or 32, 32r2, 64
+or 64r2.
+The values other than 0 make the assembler accept instructions
 for the corresponding @sc{isa} level, from that point on in the
 assembly.  @code{.set mips@var{n}} affects not only which instructions
 are permitted, but also how certain macros are expanded.  @code{.set
@@ -341,4 +366,12 @@ from the MIPS-3D Application Specific Extension from that point on
 in the assembly.  The @code{.set nomips3d} directive prevents MIPS-3D
 instructions from being accepted.
 
+@cindex MIPS MDMX instruction generation override
+@kindex @code{.set mdmx}
+@kindex @code{.set nomdmx}
+The directive @code{.set mdmx} makes the assembler accept instructions
+from the MDMX Application Specific Extension from that point on
+in the assembly.  The @code{.set nomdmx} directive prevents MDMX
+instructions from being accepted.
+
 Traditional @sc{mips} assemblers do not support these directives.