* config/tc-arc.c (md_pseudo_table <dwarf2_directive_file>): Cast.

[external/binutils.git] / gas / config / tc-sh.c

diff --git a/gas/config/tc-sh.c b/gas/config/tc-sh.c
index e62a6f9..4ae4c03 100644 (file)
--- a/gas/config/tc-sh.c
+++ b/gas/config/tc-sh.c
@@ -136,7 +136,7 @@ const pseudo_typeS md_pseudo_table[] =
   {"4byte", s_uacons, 4},
   {"8byte", s_uacons, 8},
 #ifdef BFD_ASSEMBLER
-  {"file", dwarf2_directive_file, 0 },
+  {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0 },
   {"loc", dwarf2_directive_loc, 0 },
 #endif
 #ifdef HAVE_SH64
@@ -1589,27 +1589,6 @@ get_specific (opcode, operands)
          sh_operand_info *user = operands + n;
          sh_arg_type arg = this_try->arg[n];
 
-         /* If this is a parallel insn check to see if both
-            parts have the same destination register.  */
-         if ((n == 2) && (this_try->nibbles[0] == PPI))
-           {
-             static boolean bIsPPI = false;
-             static int nLastDestReg;
-
-             if (!bIsPPI)
-               {
-                 bIsPPI = true;
-                 nLastDestReg = user->reg;
-               }
-             else /* Second insn.  */
-               {
-                 if (nLastDestReg == user->reg)
-                   as_warn (_("destination register is same for parallel insns"));
-
-                 bIsPPI = false;
-               }
-           }
-
          switch (arg)
            {
            case A_DISP_PC:
@@ -2280,6 +2259,15 @@ assemble_ppi (op_end, opcode)
                default:
                  as_bad (_("bad padd / psub pmuls output operand"));
                }
+               /* Generate warning if the destination register for padd / psub
+                  and pmuls is the same ( only for A0 or A1 ).
+                  If the last nibble is 1010 then A0 is used in both
+                  padd / psub and pmuls. If it is 1111 then A1 is used
+                  as destination register in both padd / psub and pmuls.  */
+
+               if ((((field_b | reg_efg) & 0x000F) == 0x000A)
+                   || (((field_b | reg_efg) & 0x000F) == 0x000F))
+                 as_warn (_("destination register is same for parallel insns"));
            }
          field_b += 0x4000 + reg_efg;
          break;