RISC-V: Compress 3-operand beq/bne against x0.

[external/binutils.git] / gas / config / tc-riscv.c

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 9931615..99b007f 100644 (file)
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -586,6 +586,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
          case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
          case 'w': break; /* RS1S, constrained to equal RD */
          case 'x': break; /* RS2S, constrained to equal RD */
+         case 'z': break; /* RS2S, contrained to be x0 */
          case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
          case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
          case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
@@ -1472,6 +1473,11 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
                      || regno != X_SP)
                    break;
                  continue;
+               case 'z': /* RS2, contrained to equal x0.  */
+                 if (!reg_lookup (&s, RCLASS_GPR, &regno)
+                     || regno != 0)
+                   break;
+                 continue;
                case '>':
                  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
                      || imm_expr->X_op != O_constant