|| mips_opts.arch == CPU_R10000 \
|| mips_opts.arch == CPU_R12000 \
|| mips_opts.arch == CPU_RM7000 \
- || mips_opts.arch == CPU_SB1 \
|| mips_opts.arch == CPU_VR5500 \
)
level I. */
#define gpr_interlocks \
(mips_opts.isa != ISA_MIPS1 \
- || mips_opts.arch == CPU_VR5400 \
- || mips_opts.arch == CPU_VR5500 \
|| mips_opts.arch == CPU_R3900)
/* Whether the processor uses hardware interlocks to avoid delays
&& mips_opts.isa != ISA_MIPS2 \
&& mips_opts.isa != ISA_MIPS3) \
|| mips_opts.arch == CPU_R4300 \
- || mips_opts.arch == CPU_VR5400 \
- || mips_opts.arch == CPU_VR5500 \
- || mips_opts.arch == CPU_SB1 \
)
/* Whether the processor uses hardware interlocks to protect reads
macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
}
+static inline void
+load_delay_nop (void)
+{
+ if (!gpr_interlocks)
+ macro_build (NULL, "nop", "");
+}
+
/* Load an address into a register. */
static void
ep->X_add_number = 0;
macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
BFD_RELOC_MIPS_GOT16, mips_gp_register);
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
relax_start (ep->X_add_symbol);
relax_switch ();
macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
}
macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
BFD_RELOC_MIPS_GOT16, mips_gp_register);
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
BFD_RELOC_LO16);
relax_end ();
/* We're going to put in an addu instruction using
tempreg, so we may as well insert the nop right
now. */
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
}
relax_switch ();
macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
tempreg, tempreg, BFD_RELOC_LO16);
relax_end ();
&& offset_expr.X_add_number < 0x8000)
{
load_got_offset (tempreg, &offset_expr);
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
add_got_offset (tempreg, &offset_expr);
}
else
not using a base register. */
if (breg == treg)
{
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
treg, AT, breg);
breg = 0;
/* We're going to put in an addu instruction using
tempreg, so we may as well insert the nop right
now. */
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
}
}
else if (expr1.X_add_number >= -0x8000
&& expr1.X_add_number < 0x8000)
{
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
tempreg, tempreg, BFD_RELOC_LO16);
}
else
{
assert (tempreg == AT);
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
treg, AT, breg);
dreg = treg;
if (expr1.X_add_number >= -0x8000
&& expr1.X_add_number < 0x8000)
{
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
tempreg, tempreg, BFD_RELOC_LO16);
/* FIXME: If add_number is 0, and there was no base
/* We must add in the base register now, as in the
external symbol case. */
assert (tempreg == AT);
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
treg, AT, breg);
tempreg = treg;
macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
mips_gp_register);
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
relax_switch ();
}
else
macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
PIC_CALL_REG);
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
relax_switch ();
if (gpdelay)
macro_build (NULL, "nop", "");
macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
mips_gp_register);
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
relax_end ();
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
lw_reloc_type, mips_gp_register);
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
relax_start (offset_expr.X_add_symbol);
relax_switch ();
macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
macro_build (NULL, "nop", "");
macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
BFD_RELOC_MIPS_GOT16, mips_gp_register);
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
tempreg, BFD_RELOC_LO16);
relax_end ();
|| expr1.X_add_number >= 0x8000 - 4)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
load_got_offset (AT, &offset_expr);
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
if (breg != 0)
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
AT, AT, mips_gp_register);
macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
AT, BFD_RELOC_MIPS_GOT_LO16, AT);
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
if (breg != 0)
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
/* Itbl support may require additional care here. */
macro_build (NULL, "nop", "");
macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
BFD_RELOC_MIPS_GOT16, mips_gp_register);
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
if (breg != 0)
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
/* Itbl support may require additional care here. */
if (treg == tempreg)
return;
/* Protect second load's delay slot. */
- if (!gpr_interlocks)
- macro_build (NULL, "nop", "");
+ load_delay_nop ();
move_register (treg, tempreg);
break;