shouldn't assume or require it to). */
static int warn_unmatched_high = 0;
-/* start-sanitize-cygnus */
/* Non-zero if -m32rx has been specified, in which case support for the
extended M32RX instruction set should be enabled. */
static int enable_m32rx = 0;
/* Non-zero if insns can be made parallel. */
static int optimize;
-/* end-sanitize-cygnus */
/* stuff for .scomm symbols. */
static segT sbss_section;
static struct m32r_hi_fixup * m32r_hi_fixup_list;
\f
-/* start-sanitize-cygnus */
static void
allow_m32rx (on)
int on;
bfd_set_arch_mach (stdoutput, TARGET_ARCH,
enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
}
-/* end-sanitize-cygnus */
\f
-#define M32R_SHORTOPTS ""
-/* start-sanitize-cygnus */
-#undef M32R_SHORTOPTS
#define M32R_SHORTOPTS "O"
-/* end-sanitize-cygnus */
const char * md_shortopts = M32R_SHORTOPTS;
struct option md_longopts[] =
{
-/* start-sanitize-cygnus */
#define OPTION_M32RX (OPTION_MD_BASE)
{"m32rx", no_argument, NULL, OPTION_M32RX},
#define OPTION_WARN_PARALLEL (OPTION_MD_BASE + 1)
{"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
#define OPTION_SPECIAL (OPTION_MD_BASE + 3)
{"hidden", no_argument, NULL, OPTION_SPECIAL},
-/* end-sanitize-cygnus */
/* Sigh. I guess all warnings must now have both variants. */
#define OPTION_WARN_UNMATCHED (OPTION_MD_BASE + 4)
- {"warn-unmatched-high", OPTION_WARN_UNMATCHED},
- {"Wuh", OPTION_WARN_UNMATCHED},
+ {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED},
+ {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED},
#define OPTION_NO_WARN_UNMATCHED (OPTION_MD_BASE + 5)
- {"no-warn-unmatched-high", OPTION_WARN_UNMATCHED},
- {"Wnuh", OPTION_WARN_UNMATCHED},
+ {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
+ {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
#if 0 /* not supported yet */
#define OPTION_RELAX (OPTION_MD_BASE + 6)
#define OPTION_CPU_DESC (OPTION_MD_BASE + 7)
{"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
#endif
-
{NULL, no_argument, NULL, 0}
};
size_t md_longopts_size = sizeof (md_longopts);
{
switch (c)
{
-/* start-sanitize-cygnus */
case 'O':
optimize = 1;
break;
enable_special = 1;
else
{
- extern char * myname;
-
/* Pretend that we do not recognise this option. */
- fprintf (stderr, _("%s: unrecognised option: -hidden\n"), myname);
+ as_bad (_("Unrecognised option: -hidden"));
return 0;
}
break;
-/* end-sanitize-cygnus */
case OPTION_WARN_UNMATCHED:
warn_unmatched_high = 1;
default:
return 0;
}
+
return 1;
}
{
fprintf (stream, _(" M32R specific command line options:\n"));
-/* start-sanitize-cygnus */
fprintf (stream, _("\
-m32rx support the extended m32rx instruction set\n"));
fprintf (stream, _("\
-Wp synonym for -warn-explicit-parallel-conflicts\n"));
fprintf (stream, _("\
-Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
-/* end-sanitize-cygnus */
fprintf (stream, _("\
-warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
{ "fillinsn", fill_insn, 0 },
{ "scomm", m32r_scomm, 0 },
{ "debugsym", debug_sym, 0 },
-/* start-sanitize-cygnus */
/* Not documented as so far there is no need for them.... */
{ "m32r", allow_m32rx, 0 },
{ "m32rx", allow_m32rx, 1 },
-/* end-sanitize-cygnus */
{ NULL, NULL, 0 }
};
{
/* Only do this if the fill pattern wasn't specified. */
if (fill == NULL
- && (now_seg->flags & SEC_CODE) != 0
+ && subseg_text_p (now_seg)
/* Only do this special handling if aligning to at least a
4 byte boundary. */
&& n > 1
link->symbol = symbolP;
link->next = debug_sym_link;
debug_sym_link = link;
- symbolP->local = 1;
+ symbol_get_obj (symbolP)->local = 1;
}
*end_name = delim;
/* Initialize the `cgen' interface. */
/* Set the machine number and endian. */
- gas_cgen_cpu_desc = m32r_cgen_cpu_open (0 /* mach number */,
- target_big_endian ?
- CGEN_ENDIAN_BIG
- : CGEN_ENDIAN_LITTLE);
+ gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
+ CGEN_CPU_OPEN_ENDIAN,
+ CGEN_ENDIAN_BIG,
+ CGEN_CPU_OPEN_END);
m32r_cgen_init_asm (gas_cgen_cpu_desc);
/* The operand instance table is used during optimization to determine
scom_symbol.name = ".scommon";
scom_symbol.section = & scom_section;
-/* start-sanitize-cygnus */
allow_m32rx (enable_m32rx);
-/* end-sanitize-cygnus */
}
-/* start-sanitize-cygnus */
-
#define OPERAND_IS_COND_BIT(operand, indices, index) \
- ((operand)->hw->type == HW_H_COND \
- || ((operand)->hw->type == HW_H_PSW) \
- || ((operand)->hw->type == HW_H_CR \
+ ((operand)->hw_type == HW_H_COND \
+ || ((operand)->hw_type == HW_H_PSW) \
+ || ((operand)->hw_type == HW_H_CR \
&& (indices [index] == 0 || indices [index] == 1)))
/* Returns true if an output of instruction 'a' is referenced by an operand
== (check_outputs
? CGEN_OPINST_OUTPUT
: CGEN_OPINST_INPUT))
- && (b_operands->hw == a_operands->hw)
+ && (b_operands->hw_type == a_operands->hw_type)
&& (a->indices [a_index] == b->indices [b_index]))
return 1;
}
prev_subseg = now_subseg;
}
-/* end-sanitize-cygnus */
-
-
void
md_assemble (str)
char * str;
/* Initialize GAS's cgen interface for a new instruction. */
gas_cgen_init_parse ();
-/* start-sanitize-cygnus */
/* Look for a parallel instruction seperator. */
if ((str2 = strstr (str, "||")) != NULL)
{
assemble_two_insns (str, str2, 0);
return;
}
-/* end-sanitize-cygnus */
insn.debug_sym_link = debug_sym_link;
debug_sym_link = (sym_linkS *)0;
return;
}
-/* start-sanitize-cygnus */
if (! enable_special
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
{
as_bad (_("instruction '%s' is for the M32RX only"), str);
return;
}
-/* end-sanitize-cygnus */
if (CGEN_INSN_BITSIZE (insn.insn) == 32)
{
else
{
int on_32bit_boundary_p;
-/* start-sanitize-cygnus */
int swap = false;
-/* end-sanitize-cygnus */
if (CGEN_INSN_BITSIZE (insn.insn) != 16)
abort();
insn.orig_insn = insn.insn;
-/* start-sanitize-cygnus */
+
/* If the previous insn was relaxable, then it may be expanded
to fill the current 16 bit slot. Emit a NOP here to occupy
this slot, so that we can start at optimizing at a 32 bit
if (insn.insn == NULL)
as_fatal (_("internal error: lookup/get operands failed"));
}
-/* end-sanitize-cygnus */
/* Compute whether we're on a 32 bit boundary or not.
prev_insn.insn is NULL when we're on a 32 bit boundary. */
on_32bit_boundary_p = prev_insn.insn == NULL;
-/* start-sanitize-cygnus */
/* Look to see if this instruction can be combined with the
previous instruction to make one, parallel, 32 bit instruction.
If the previous instruction (potentially) changed the flow of
else if (can_make_parallel (& insn, & prev_insn) == NULL)
swap = true;
}
-/* end-sanitize-cygnus */
expand_debug_syms (insn.debug_sym_link, 1);
insn.fixups[i] = fi.fixups[i];
}
-/* start-sanitize-cygnus */
if (swap)
{
int i,tmp;
for (i = 0; i < insn.num_fixups; ++i)
insn.fixups[i]->fx_where -= 2;
}
-/* end-sanitize-cygnus */
/* Keep track of whether we've seen a pair of 16 bit insns.
prev_insn.insn is NULL when we're on a 32 bit boundary. */
return;
}
- if (symbolP->local)
+ if (symbol_get_obj (symbolP)->local)
{
segT old_sec = now_seg;
int old_subsec = now_subseg;
frag_align (align2, 0, 0);
if (S_GET_SEGMENT (symbolP) == sbss_section)
- symbolP->sy_frag->fr_symbol = 0;
+ symbol_get_frag (symbolP)->fr_symbol = 0;
- symbolP->sy_frag = frag_now;
+ symbol_set_frag (symbolP, frag_now);
pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
(char *) 0);
{
/* Address we want to reach in file space. */
target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
- target_address += fragP->fr_symbol->sy_frag->fr_address;
+ target_address += symbol_get_frag (fragP->fr_symbol)->fr_address;
addend = (target_address - (opcode_address & -4)) >> 2;
}
4 /*length*/,
/* FIXME: quick hack */
#if 0
- CGEN_OPERAND_ENTRY (gas_cgen_cpu_desc,
- fragP->fr_cgen.opindex),
+ cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
+ fragP->fr_cgen.opindex),
#else
- CGEN_OPERAND_ENTRY (gas_cgen_cpu_desc,
- M32R_OPERAND_DISP24),
+ cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
+ M32R_OPERAND_DISP24),
#endif
fragP->fr_cgen.opinfo,
fragP->fr_symbol, fragP->fr_offset);
const CGEN_OPERAND * operand;
fixS * fixP;
{
- switch (CGEN_OPERAND_TYPE (gas_cgen_cpu_desc, operand))
+ switch (operand->type)
{
case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
case M32R_OPERAND_SLO16 :
case M32R_OPERAND_ULO16 :
/* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
- if (fixP->tc_fix_data.opinfo != 0)
- return fixP->tc_fix_data.opinfo;
+ if (fixP->fx_cgen.opinfo != 0)
+ return fixP->fx_cgen.opinfo;
break;
default : /* avoid -Wall warning */
break;
fixS * fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
operand, opinfo, exp);
- switch (CGEN_OPERAND_TYPE (gas_cgen_cpu_desc, operand))
+ switch (operand->type)
{
case M32R_OPERAND_HI16 :
/* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
- if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
- || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
- m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
+ if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO
+ || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
+ m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg);
break;
default : /* avoid -Wall warning */
break;
/* Return BFD reloc type from opinfo field in a fixS.
It's tricky using fx_r_type in m32r_frob_file because the values
are BFD_RELOC_UNUSED + operand number. */
-#define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
+#define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
/* Sort any unmatched HI16 relocs so that they immediately precede
the corresponding LO16 reloc. This is called before md_apply_fix and
projects / external / binutils.git / blobdiff