#include "as.h"
#include "subsegs.h"
#include "symcat.h"
-#include "cgen-opc.h"
+#include "opcodes/m32r-desc.h"
+#include "opcodes/m32r-opc.h"
#include "cgen.h"
/* Linked list of symbols that are debugging symbols to be defined as the
shouldn't assume or require it to). */
static int warn_unmatched_high = 0;
-/* start-sanitize-m32rx */
/* Non-zero if -m32rx has been specified, in which case support for the
extended M32RX instruction set should be enabled. */
static int enable_m32rx = 0;
/* Non-zero if insns can be made parallel. */
static int optimize;
-/* end-sanitize-m32rx */
/* stuff for .scomm symbols. */
static segT sbss_section;
static struct m32r_hi_fixup * m32r_hi_fixup_list;
\f
-/* start-sanitize-m32rx */
static void
allow_m32rx (on)
int on;
bfd_set_arch_mach (stdoutput, TARGET_ARCH,
enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
}
-/* end-sanitize-m32rx */
\f
-#define M32R_SHORTOPTS ""
-/* start-sanitize-m32rx */
-#undef M32R_SHORTOPTS
#define M32R_SHORTOPTS "O"
-/* end-sanitize-m32rx */
const char * md_shortopts = M32R_SHORTOPTS;
struct option md_longopts[] =
{
-/* start-sanitize-m32rx */
#define OPTION_M32RX (OPTION_MD_BASE)
{"m32rx", no_argument, NULL, OPTION_M32RX},
#define OPTION_WARN_PARALLEL (OPTION_MD_BASE + 1)
{"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
#define OPTION_SPECIAL (OPTION_MD_BASE + 3)
{"hidden", no_argument, NULL, OPTION_SPECIAL},
-/* end-sanitize-m32rx */
/* Sigh. I guess all warnings must now have both variants. */
#define OPTION_WARN_UNMATCHED (OPTION_MD_BASE + 4)
- {"warn-unmatched-high", OPTION_WARN_UNMATCHED},
- {"Wuh", OPTION_WARN_UNMATCHED},
+ {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED},
+ {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED},
#define OPTION_NO_WARN_UNMATCHED (OPTION_MD_BASE + 5)
- {"no-warn-unmatched-high", OPTION_WARN_UNMATCHED},
- {"Wnuh", OPTION_WARN_UNMATCHED},
+ {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
+ {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
#if 0 /* not supported yet */
#define OPTION_RELAX (OPTION_MD_BASE + 6)
#define OPTION_CPU_DESC (OPTION_MD_BASE + 7)
{"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
#endif
-
{NULL, no_argument, NULL, 0}
};
size_t md_longopts_size = sizeof (md_longopts);
{
switch (c)
{
-/* start-sanitize-m32rx */
case 'O':
optimize = 1;
break;
enable_special = 1;
else
{
- extern char * myname;
-
/* Pretend that we do not recognise this option. */
- fprintf (stderr, _("%s: unrecognised option: -hidden\n"), myname);
+ as_bad (_("Unrecognised option: -hidden"));
return 0;
}
break;
-/* end-sanitize-m32rx */
case OPTION_WARN_UNMATCHED:
warn_unmatched_high = 1;
default:
return 0;
}
+
return 1;
}
{
fprintf (stream, _(" M32R specific command line options:\n"));
-/* start-sanitize-m32rx */
fprintf (stream, _("\
-m32rx support the extended m32rx instruction set\n"));
fprintf (stream, _("\
-Wp synonym for -warn-explicit-parallel-conflicts\n"));
fprintf (stream, _("\
-Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
-/* end-sanitize-m32rx */
fprintf (stream, _("\
-warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
{ "fillinsn", fill_insn, 0 },
{ "scomm", m32r_scomm, 0 },
{ "debugsym", debug_sym, 0 },
-/* start-sanitize-m32rx */
/* Not documented as so far there is no need for them.... */
{ "m32r", allow_m32rx, 0 },
{ "m32rx", allow_m32rx, 1 },
-/* end-sanitize-m32rx */
{ NULL, NULL, 0 }
};
{
/* Only do this if the fill pattern wasn't specified. */
if (fill == NULL
- && (now_seg->flags & SEC_CODE) != 0
+ && subseg_text_p (now_seg)
/* Only do this special handling if aligning to at least a
4 byte boundary. */
&& n > 1
link->symbol = symbolP;
link->next = debug_sym_link;
debug_sym_link = link;
- symbolP->local = 1;
+ symbol_get_obj (symbolP)->local = 1;
}
*end_name = delim;
/* Initialize the `cgen' interface. */
/* Set the machine number and endian. */
- gas_cgen_opcode_desc = m32r_cgen_opcode_open (0 /* mach number */,
- target_big_endian ?
- CGEN_ENDIAN_BIG
- : CGEN_ENDIAN_LITTLE);
- m32r_cgen_init_asm (gas_cgen_opcode_desc);
+ gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
+ CGEN_CPU_OPEN_ENDIAN,
+ CGEN_ENDIAN_BIG,
+ CGEN_CPU_OPEN_END);
+ m32r_cgen_init_asm (gas_cgen_cpu_desc);
+
+ /* The operand instance table is used during optimization to determine
+ which insns can be executed in parallel. It is also used to give
+ warnings regarding operand interference in parallel insns. */
+ m32r_cgen_init_opinst_table (gas_cgen_cpu_desc);
/* This is a callback from cgen to gas to parse operands. */
- cgen_set_parse_operand_fn (gas_cgen_opcode_desc, gas_cgen_parse_operand);
+ cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
#if 0 /* not supported yet */
/* If a runtime cpu description file was provided, parse it. */
{
const char * errmsg;
- errmsg = cgen_read_cpu_file (gas_cgen_opcode_desc, m32r_cpu_desc);
+ errmsg = cgen_read_cpu_file (gas_cgen_cpu_desc, m32r_cpu_desc);
if (errmsg != NULL)
as_bad ("%s: %s", m32r_cpu_desc, errmsg);
}
scom_symbol.name = ".scommon";
scom_symbol.section = & scom_section;
-/* start-sanitize-m32rx */
allow_m32rx (enable_m32rx);
-/* end-sanitize-m32rx */
}
-/* start-sanitize-m32rx */
-
-#define OPERAND_IS_COND_BIT(operand, indices, index) \
- (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_COND \
- || (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_PSW) \
- || (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_CR \
- && (indices [index] == 0 || indices [index] == 1)))
+#define OPERAND_IS_COND_BIT(operand, indices, index) \
+ ((operand)->hw_type == HW_H_COND \
+ || ((operand)->hw_type == HW_H_PSW) \
+ || ((operand)->hw_type == HW_H_CR \
+ && (indices [index] == 0 || indices [index] == 1)))
/* Returns true if an output of instruction 'a' is referenced by an operand
of instruction 'b'. If 'check_outputs' is true then b's outputs are
m32r_insn * b;
const int check_outputs;
{
- const CGEN_OPERAND_INSTANCE * a_operands = CGEN_INSN_OPERANDS (a->insn);
- const CGEN_OPERAND_INSTANCE * b_ops = CGEN_INSN_OPERANDS (b->insn);
- int a_index;
+ const CGEN_OPINST * a_operands = CGEN_INSN_OPERANDS (a->insn);
+ const CGEN_OPINST * b_ops = CGEN_INSN_OPERANDS (b->insn);
+ int a_index;
/* If at least one of the instructions takes no operands, then there is
nothing to check. There really are instructions without operands,
/* Scan the operand list of 'a' looking for an output operand. */
for (a_index = 0;
- CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END;
+ a_operands->type != CGEN_OPINST_END;
a_index ++, a_operands ++)
{
- if (CGEN_OPERAND_INSTANCE_TYPE (a_operands) == CGEN_OPERAND_INSTANCE_OUTPUT)
+ if (a_operands->type == CGEN_OPINST_OUTPUT)
{
int b_index;
- const CGEN_OPERAND_INSTANCE * b_operands = b_ops;
+ const CGEN_OPINST * b_operands = b_ops;
/* Special Case:
The Condition bit 'C' is a shadow of the CBR register (control
/* Scan operand list of 'b' looking for another reference to the
condition bit, which goes in the right direction. */
for (b_index = 0;
- CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END;
+ b_operands->type != CGEN_OPINST_END;
b_index ++, b_operands ++)
{
- if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) ==
- (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT))
+ if ((b_operands->type
+ == (check_outputs
+ ? CGEN_OPINST_OUTPUT
+ : CGEN_OPINST_INPUT))
&& OPERAND_IS_COND_BIT (b_operands, b->indices, b_index))
return 1;
}
references the same hardware element, and which goes in the
right direction. */
for (b_index = 0;
- CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END;
+ b_operands->type != CGEN_OPINST_END;
b_index ++, b_operands ++)
{
- if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) ==
- (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT))
- && (CGEN_OPERAND_INSTANCE_HW (b_operands) == CGEN_OPERAND_INSTANCE_HW (a_operands))
+ if ((b_operands->type
+ == (check_outputs
+ ? CGEN_OPINST_OUTPUT
+ : CGEN_OPINST_INPUT))
+ && (b_operands->hw_type == a_operands->hw_type)
&& (a->indices [a_index] == b->indices [b_index]))
return 1;
}
m32r_insn * a;
{
#if 0 /* Once PC operands are working.... */
- const CGEN_OPERAND_INSTANCE * a_operands == CGEN_INSN_OPERANDS (a->insn);
+ const CGEN_OPINST * a_operands == CGEN_INSN_OPERANDS (gas_cgen_cpu_desc,
+ a->insn);
if (a_operands == NULL)
return 0;
- while (CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END)
+ while (a_operands->type != CGEN_OPINST_END)
{
- if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands) != NULL
- && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands)) == M32R_OPERAND_PC)
+ if (a_operands->operand != NULL
+ && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc, a_operands->operand) == M32R_OPERAND_PC)
return 1;
a_operands ++;
}
#else
- if (CGEN_INSN_ATTR (a->insn, CGEN_INSN_UNCOND_CTI)
- || CGEN_INSN_ATTR (a->insn, CGEN_INSN_COND_CTI))
+ if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI)
+ || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI))
return 1;
#endif
return 0;
if (first_writes_to_seconds_operands (a, b, true))
return _("Instructions write to the same destination register.");
- a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE);
- b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE);
+ a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE);
+ b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE);
/* Make sure that the instructions use the correct execution pipelines. */
if ( a_pipe == PIPE_NONE
#if CGEN_INT_INSN_P
*buffer |= 0x8000;
#else
- buffer [CGEN_OPCODE_ENDIAN (gas_cgen_opcode_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
+ buffer [CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
|= 0x80;
#endif
}
target_make_parallel (buffer)
char *buffer;
{
- buffer [CGEN_OPCODE_ENDIAN (gas_cgen_opcode_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
+ buffer [CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
|= 0x80;
}
* str2 = 0; /* Seperate the two instructions. */
- /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
- so that the parallel instruction will start on a 32 bit boundary.
+ /* Make sure the two insns begin on a 32 bit boundary.
This is also done for the serial case (foo -> bar), relaxing doesn't
- affect insns written like this. */
- if (prev_insn.insn)
- fill_insn (0);
+ affect insns written like this.
+ Note that we must always do this as we can't assume anything about
+ whether we're currently on a 32 bit boundary or not. Relaxing may
+ change this. */
+ fill_insn (0);
first.debug_sym_link = debug_sym_link;
debug_sym_link = (sym_linkS *)0;
/* Parse the first instruction. */
if (! (first.insn = m32r_cgen_assemble_insn
- (gas_cgen_opcode_desc, str, & first.fields, first.buffer, & errmsg)))
+ (gas_cgen_cpu_desc, str, & first.fields, first.buffer, & errmsg)))
{
as_bad (errmsg);
return;
return;
}
else if (! enable_special
- && CGEN_INSN_ATTR (first.insn, CGEN_INSN_SPECIAL))
+ && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
{
/* xgettext:c-format */
as_bad (_("unknown instruction '%s'"), str);
}
else if (! enable_m32rx
/* FIXME: Need standard macro to perform this test. */
- && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
+ && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
{
/* xgettext:c-format */
as_bad (_("instruction '%s' is for the M32RX only"), str);
}
/* Check to see if this is an allowable parallel insn. */
- if (parallel_p && CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
+ if (parallel_p && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
{
/* xgettext:c-format */
as_bad (_("instruction '%s' cannot be executed in parallel."), str);
version (eg relaxability). When aliases behave differently this
may have to change. */
first.orig_insn = first.insn;
- first.insn = m32r_cgen_lookup_get_insn_operands
- (gas_cgen_opcode_desc, NULL, INSN_VALUE (first.buffer), 16,
- first.indices);
+ {
+ CGEN_FIELDS tmp_fields;
+ first.insn = cgen_lookup_get_insn_operands
+ (gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16,
+ first.indices, &tmp_fields);
+ }
if (first.insn == NULL)
as_fatal (_("internal error: lookup/get operands failed"));
/* Parse the second instruction. */
if (! (second.insn = m32r_cgen_assemble_insn
- (gas_cgen_opcode_desc, str, & second.fields, second.buffer, & errmsg)))
+ (gas_cgen_cpu_desc, str, & second.fields, second.buffer, & errmsg)))
{
as_bad (errmsg);
return;
return;
}
else if (! enable_special
- && CGEN_INSN_ATTR (second.insn, CGEN_INSN_SPECIAL))
+ && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
{
/* xgettext:c-format */
as_bad (_("unknown instruction '%s'"), str);
return;
}
else if (! enable_m32rx
- && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
+ && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
{
/* xgettext:c-format */
as_bad (_("instruction '%s' is for the M32RX only"), str);
}
/* Check to see if this is an allowable parallel insn. */
- if (parallel_p && CGEN_INSN_ATTR (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
+ if (parallel_p && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
{
/* xgettext:c-format */
as_bad (_("instruction '%s' cannot be executed in parallel."), str);
/* Get the indices of the operands of the instruction. */
second.orig_insn = second.insn;
- second.insn = m32r_cgen_lookup_get_insn_operands
- (gas_cgen_opcode_desc, NULL, INSN_VALUE (second.buffer), 16,
- second.indices);
+ {
+ CGEN_FIELDS tmp_fields;
+ second.insn = cgen_lookup_get_insn_operands
+ (gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16,
+ second.indices, &tmp_fields);
+ }
if (second.insn == NULL)
as_fatal (_("internal error: lookup/get operands failed"));
prev_subseg = now_subseg;
}
-/* end-sanitize-m32rx */
-
-
void
md_assemble (str)
char * str;
/* Initialize GAS's cgen interface for a new instruction. */
gas_cgen_init_parse ();
-/* start-sanitize-m32rx */
/* Look for a parallel instruction seperator. */
if ((str2 = strstr (str, "||")) != NULL)
{
assemble_two_insns (str, str2, 0);
return;
}
-/* end-sanitize-m32rx */
insn.debug_sym_link = debug_sym_link;
debug_sym_link = (sym_linkS *)0;
insn.insn = m32r_cgen_assemble_insn
- (gas_cgen_opcode_desc, str, & insn.fields, insn.buffer, & errmsg);
+ (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
if (!insn.insn)
{
return;
}
-/* start-sanitize-m32rx */
if (! enable_special
- && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_SPECIAL))
+ && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
{
/* xgettext:c-format */
as_bad (_("unknown instruction '%s'"), str);
return;
}
else if (! enable_m32rx
- && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
+ && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
{
/* xgettext:c-format */
as_bad (_("instruction '%s' is for the M32RX only"), str);
return;
}
-/* end-sanitize-m32rx */
if (CGEN_INSN_BITSIZE (insn.insn) == 32)
{
else
{
int on_32bit_boundary_p;
-/* start-sanitize-m32rx */
int swap = false;
-/* end-sanitize-m32rx */
if (CGEN_INSN_BITSIZE (insn.insn) != 16)
abort();
insn.orig_insn = insn.insn;
-/* start-sanitize-m32rx */
+
/* If the previous insn was relaxable, then it may be expanded
to fill the current 16 bit slot. Emit a NOP here to occupy
this slot, so that we can start at optimizing at a 32 bit
{
/* Get the indices of the operands of the instruction.
FIXME: See assemble_parallel for notes on orig_insn. */
- insn.insn = m32r_cgen_lookup_get_insn_operands
- (gas_cgen_opcode_desc, NULL, INSN_VALUE (insn.buffer),
- 16, insn.indices);
+ {
+ CGEN_FIELDS tmp_fields;
+ insn.insn = cgen_lookup_get_insn_operands
+ (gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL,
+ 16, insn.indices, &tmp_fields);
+ }
if (insn.insn == NULL)
as_fatal (_("internal error: lookup/get operands failed"));
}
-/* end-sanitize-m32rx */
/* Compute whether we're on a 32 bit boundary or not.
prev_insn.insn is NULL when we're on a 32 bit boundary. */
on_32bit_boundary_p = prev_insn.insn == NULL;
-/* start-sanitize-m32rx */
/* Look to see if this instruction can be combined with the
previous instruction to make one, parallel, 32 bit instruction.
If the previous instruction (potentially) changed the flow of
if ( ! on_32bit_boundary_p
&& enable_m32rx
&& optimize
- && CGEN_INSN_ATTR (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
+ && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
&& ! writes_to_pc (& prev_insn)
&& ! first_writes_to_seconds_operands (& prev_insn, &insn, false)
)
else if (can_make_parallel (& insn, & prev_insn) == NULL)
swap = true;
}
-/* end-sanitize-m32rx */
expand_debug_syms (insn.debug_sym_link, 1);
insn.fixups[i] = fi.fixups[i];
}
-/* start-sanitize-m32rx */
if (swap)
{
int i,tmp;
for (i = 0; i < insn.num_fixups; ++i)
insn.fixups[i]->fx_where -= 2;
}
-/* end-sanitize-m32rx */
/* Keep track of whether we've seen a pair of 16 bit insns.
prev_insn.insn is NULL when we're on a 32 bit boundary. */
/* If the insn needs the following one to be on a 32 bit boundary
(e.g. subroutine calls), fill this insn's slot. */
if (on_32bit_boundary_p
- && CGEN_INSN_ATTR (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0)
+ && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0)
fill_insn (0);
/* If this is a relaxable insn (can be replaced with a larger version)
mark the fact so that we can emit an alignment directive for a
following 32 bit insn if we see one. */
- if (CGEN_INSN_ATTR (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0)
+ if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0)
seen_relaxable_p = 1;
}
return;
}
- if (symbolP->local)
+ if (symbol_get_obj (symbolP)->local)
{
segT old_sec = now_seg;
int old_subsec = now_subseg;
frag_align (align2, 0, 0);
if (S_GET_SEGMENT (symbolP) == sbss_section)
- symbolP->sy_frag->fr_symbol = 0;
+ symbol_get_frag (symbolP)->fr_symbol = 0;
- symbolP->sy_frag = frag_now;
+ symbol_set_frag (symbolP, frag_now);
pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
(char *) 0);
if ((strcmp (CGEN_INSN_MNEMONIC (insn),
CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
== 0)
- && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
+ && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX))
break;
}
if (i == 4)
{
/* Address we want to reach in file space. */
target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
- target_address += fragP->fr_symbol->sy_frag->fr_address;
+ target_address += symbol_get_frag (fragP->fr_symbol)->fr_address;
addend = (target_address - (opcode_address & -4)) >> 2;
}
4 /*length*/,
/* FIXME: quick hack */
#if 0
- CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
+ cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
+ fragP->fr_cgen.opindex),
#else
- CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
+ cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
+ M32R_OPERAND_DISP24),
#endif
fragP->fr_cgen.opinfo,
fragP->fr_symbol, fragP->fr_offset);
const CGEN_OPERAND * operand;
fixS * fixP;
{
- switch (CGEN_OPERAND_TYPE (operand))
+ switch (operand->type)
{
case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
case M32R_OPERAND_SLO16 :
case M32R_OPERAND_ULO16 :
/* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
- if (fixP->tc_fix_data.opinfo != 0)
- return fixP->tc_fix_data.opinfo;
+ if (fixP->fx_cgen.opinfo != 0)
+ return fixP->fx_cgen.opinfo;
break;
default : /* avoid -Wall warning */
break;
fixS * fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
operand, opinfo, exp);
- switch (CGEN_OPERAND_TYPE (operand))
+ switch (operand->type)
{
case M32R_OPERAND_HI16 :
/* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
- if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
- || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
- m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
+ if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO
+ || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
+ m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg);
break;
default : /* avoid -Wall warning */
break;
/* Return BFD reloc type from opinfo field in a fixS.
It's tricky using fx_r_type in m32r_frob_file because the values
are BFD_RELOC_UNUSED + operand number. */
-#define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
+#define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
/* Sort any unmatched HI16 relocs so that they immediately precede
the corresponding LO16 reloc. This is called before md_apply_fix and
projects / external / binutils.git / blobdiff