import gdb-2000-02-02 snapshot

[external/binutils.git] / gas / config / tc-arm.c

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index fa61988..86e3600 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -57,7 +57,7 @@
 /* Architectures are the sum of the base and extensions */
 #define ARM_ARCH_V4    (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
 #define ARM_ARCH_V4T   (ARM_ARCH_V4 | ARM_THUMB)
-#define ARM_ARCH_V5    (ARM_ARCH_V4 | ARM_EXT_V5 )
+#define ARM_ARCH_V5    (ARM_ARCH_V4 | ARM_EXT_V5)
 #define ARM_ARCH_V5T   (ARM_ARCH_V5 | ARM_THUMB)
 
 /* Some useful combinations:  */
@@ -139,10 +139,11 @@ CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
 symbolS * GOT_symbol;          /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
 #endif
 
-CONST int md_reloc_size = 8;           /* Size of relocation record */
-
-static int thumb_mode = 0;      /* non-zero if assembling thumb instructions */
+CONST int md_reloc_size = 8;   /* Size of relocation record */
 
+static int thumb_mode = 0;      /* 0: assemble for ARM, 1: assemble for Thumb,
+                                  2: assemble for Thumb even though target cpu
+                                  does not support thumb instructions */
 typedef struct arm_fix
 {
   int thumb_mode;
@@ -856,20 +857,22 @@ struct reg_entry
 #define REG_LR  14
 #define REG_SP  13
 
-/* These are the standard names;  Users can add aliases with .req */
+/* These are the standard names.  Users can add aliases with .req */
 static CONST struct reg_entry reg_table[] =
 {
-  /* Processor Register Numbers */
+  /* Processor Register Numbers.  */
   {"r0", 0},    {"r1", 1},      {"r2", 2},      {"r3", 3},
   {"r4", 4},    {"r5", 5},      {"r6", 6},      {"r7", 7},
   {"r8", 8},    {"r9", 9},      {"r10", 10},    {"r11", 11},
   {"r12", 12},  {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
-  /* APCS conventions */
+  /* APCS conventions.  */
   {"a1", 0},   {"a2", 1},    {"a3", 2},     {"a4", 3},
   {"v1", 4},   {"v2", 5},    {"v3", 6},     {"v4", 7},     {"v5", 8},
   {"v6", 9},   {"sb", 9},    {"v7", 10},    {"sl", 10},
   {"fp", 11},  {"ip", 12},   {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
-  /* FP Registers */
+  /* ATPCS additions to APCS conventions.  */
+  {"wr", 7},    {"v8", 11},
+  /* FP Registers.  */
   {"f0", 16},   {"f1", 17},   {"f2", 18},   {"f3", 19},
   {"f4", 20},   {"f5", 21},   {"f6", 22},   {"f7", 23},
   {"c0", 32},   {"c1", 33},   {"c2", 34},   {"c3", 35},
@@ -880,6 +883,13 @@ static CONST struct reg_entry reg_table[] =
   {"cr4", 36},  {"cr5", 37},  {"cr6", 38},  {"cr7", 39},
   {"cr8", 40},  {"cr9", 41},  {"cr10", 42}, {"cr11", 43},
   {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
+  /* ATPCS additions to float register names.  */
+  {"s0",16},   {"s1",17},      {"s2",18},      {"s3",19},
+  {"s4",20},   {"s5",21},      {"s6",22},      {"s7",23},
+  {"d0",16},   {"d1",17},      {"d2",18},      {"d3",19},
+  {"d4",20},   {"d5",21},      {"d6",22},      {"d7",23},
+  /* FIXME: At some point we need to add VFP register names.  */
+  /* Array terminator.  */
   {NULL, 0}
 };
 
@@ -1260,7 +1270,7 @@ s_force_thumb (ignore)
      
   if (! thumb_mode)
     {
-      thumb_mode = 1;
+      thumb_mode = 2;
       
       record_alignment (now_seg, 1);
     }
@@ -1382,7 +1392,11 @@ arm_s_text (ignore)
   if (now_seg != text_section)
     s_ltorg (0);
   
+#ifdef OBJ_ELF
+  obj_elf_text (ignore);
+#else
   s_text (ignore);
+#endif
 }
 
 static void
@@ -1397,7 +1411,11 @@ arm_s_data (ignore)
   else if (now_seg != data_section)
     s_ltorg (0);
   
+#ifdef OBJ_ELF
+  obj_elf_data (ignore);
+#else
   s_data (ignore);
+#endif
 }
 
 #ifdef OBJ_ELF
@@ -6068,7 +6086,7 @@ md_assemble (str)
       if (opcode)
        {
          /* Check that this instruction is supported for this CPU.  */
-         if ((opcode->variants & cpu_variant) == 0)
+         if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0)
             {
                as_bad (_("selected processor does not support this opcode"));
                return;
@@ -6114,7 +6132,7 @@ md_assemble (str)
                  if (opcode->comp_suffix)
                    {
                       if (*opcode->comp_suffix != '\0')
-                        as_bad (_("Opcode `%s' must have suffix from <%s>\n"),
+                        as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
                             str, opcode->comp_suffix);
                       else
                         /* Not a conditional instruction. */
@@ -6155,7 +6173,6 @@ _("Warning: Use of the 'nv' conditional is deprecated\n"));
              else
                cond_code = COND_ALWAYS;
 
-
              /* Apply the conditional, or complain it's not allowed. */
              if (opcode->comp_suffix && *opcode->comp_suffix == '\0')
                {
@@ -6399,7 +6416,8 @@ md_parse_option (c, arg)
             }
           else if (streq (str, "thumb-interwork"))
             {
-              cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB | ARM_ARCH_V4;
+             if ((cpu_variant & ARM_THUMB) == 0)
+               cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T;
 #if defined OBJ_COFF || defined OBJ_ELF
               support_interwork = true;
 #endif
@@ -6521,6 +6539,7 @@ md_parse_option (c, arg)
                case 70:
                case 700:
                case 710:
+               case 720:
                case 7100:
                case 7500:
                  break;
@@ -6633,7 +6652,6 @@ md_parse_option (c, arg)
                    default:  as_bad (_("Invalid architecture variant -m%s"), arg); break;
                    }
                  break;
-
                  
                default:
                  as_bad (_("Invalid architecture variant -m%s"), arg);
@@ -6670,7 +6688,7 @@ md_show_usage (fp)
 _("\
  ARM Specific Assembler Options:\n\
   -m[arm][<processor name>] select processor variant\n\
-  -m[arm]v[2|2a|3|3m|4|4t|5]select architecture variant\n\
+  -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
   -mthumb                   only allow Thumb instructions\n\
   -mthumb-interwork         mark the assembled code as supporting interworking\n\
   -mall                     allow any instruction\n\
@@ -6879,12 +6897,14 @@ arm_adjust_symtab ()
     {
       if (ARM_IS_THUMB (sym))
         {
+         elf_sym = elf_symbol (symbol_get_bfdsym (sym));
+         bind = ELF_ST_BIND (elf_sym);
+         
+         /* If it's a .thumb_func, declare it as so, else tag label as .code 16.  */
          if (THUMB_IS_FUNC (sym))
-           {
-             elf_sym = elf_symbol (symbol_get_bfdsym (sym));
-             bind = ELF_ST_BIND (elf_sym);
-             elf_sym->internal_elf_sym.st_info = ELF_ST_INFO (bind, STT_ARM_TFUNC);
-            }
+           elf_sym->internal_elf_sym.st_info = ELF_ST_INFO (bind, STT_ARM_TFUNC);
+         else
+           elf_sym->internal_elf_sym.st_info = ELF_ST_INFO (bind, STT_ARM_16BIT);
          }
      }
 #endif