-*- text -*-
+* For MIPS, Add -m[no-]fix-loongson3-llsc option to fix (or not) Loongson3 LLSC
+ Errata. Add a --enable-mips-fix-loongson3-llsc=[yes|no] configure time option
+ to set the default behavior. Set the default if the configure option is not used
+ to "no".
+
+Changes in 2.32:
+
+* Add -mvexwig=[0|1] option to x86 assembler to control encoding of
+ VEX.W-ignored (WIG) VEX instructions.
+
+* Add -mx86-used-note=[yes|no] option to generate (or not) x86 GNU property
+ notes. Add a --enable-x86-used-note configure time option to set the
+ default behavior. Set the default if the configure option is not used
+ to "no".
+
+* Add support for the MIPS Loongson EXTensions R2 (EXT2) instructions.
+
+* Add support for the MIPS Loongson EXTensions (EXT) instructions.
+
+* Add support for the MIPS Loongson Content Address Memory (CAM) ASE.
+
+* Add support for the C-SKY processor series.
+
+* Add support for the MIPS Loongson MultiMedia extensions Instructions (MMI)
+ ASE.
+
+Changes in 2.31:
+
+* The ADR and ADRL pseudo-instructions supported by the ARM assembler
+ now only set the bottom bit of the address of thumb function symbols
+ if the -mthumb-interwork command line option is active.
+
+* Add support for the MIPS Global INValidate (GINV) ASE.
+
+* Add support for the MIPS Cyclic Redudancy Check (CRC) ASE.
+
+* Add support for the Freescale S12Z architecture.
+
+* Add --generate-missing-build-notes=[yes|no] option to create (or not) GNU
+ Build Attribute notes if none are present in the input sources. Add a
+ --enable-generate-build-notes=[yes|no] configure time option to set the
+ default behaviour. Set the default if the configure option is not used
+ to "no".
+
+* Remove -mold-gcc command-line option for x86 targets.
+
+* Add -O[2|s] command-line options to x86 assembler to enable alternate
+ shorter instruction encoding.
+
+* Add support for .nops directive. It is currently supported only for
+ x86 targets.
+
+Changes in 2.30:
+
+* Add support for loaction views in DWARF debug line information.
+
+Changes in 2.29:
+
+* Add support for ELF SHF_GNU_MBIND.
+
+* Add support for the WebAssembly file format and wasm32 ELF conversion.
+
+* PowerPC gas now checks that the correct register class is used in
+ instructions. For instance, "addi %f4,%cr3,%r31" warns three times
+ that the registers are invalid.
+
+* Add support for the Texas Instruments PRU processor.
+
+* Support for the ARMv8-R architecture and Cortex-R52 processor has been
+ added to the ARM port.
+
+Changes in 2.28:
+
+* Add support for the RISC-V architecture.
+
+* Add support for the ARM Cortex-M23 and Cortex-M33 processors.
+
+Changes in 2.27:
+
+* Default to --enable-compressed-debug-sections=gas for Linux/x86 targets.
+
+* Add --no-pad-sections to stop the assembler from padding the end of output
+ sections up to their alignment boundary.
+
+* Support for the ARMv8-M architecture has been added to the ARM port. Support
+ for the ARMv8-M Security and DSP Extensions has also been added to the ARM
+ port.
+
+* ARC backend accepts .extInstruction, .extCondCode, .extAuxRegister, and
+ .extCoreRegister pseudo-ops that allow an user to define custom
+ instructions, conditional codes, auxiliary and core registers.
+
+* Add a configure option --enable-elf-stt-common to decide whether ELF
+ assembler should generate common symbols with the STT_COMMON type by
+ default. Default to no.
+
+* New command-line option --elf-stt-common= for ELF targets to control
+ whether to generate common symbols with the STT_COMMON type.
+
+* Add ability to set section flags and types via numeric values for ELF
+ based targets.
+
+* Add a configure option --enable-x86-relax-relocations to decide whether
+ x86 assembler should generate relax relocations by default. Default to
+ yes, except for x86 Solaris targets older than Solaris 12.
+
+* New command-line option -mrelax-relocations= for x86 target to control
+ whether to generate relax relocations.
+
+* New command-line option -mfence-as-lock-add=yes for x86 target to encode
+ lfence, mfence and sfence as "lock addl $0x0, (%[re]sp)".
+
+* Add assembly-time relaxation option for ARC cpus.
+
+* Add --with-cpu=TYPE configure option for ARC gas. This allows the default
+ cpu type to be adjusted at configure time.
+
Changes in 2.26:
+* Add a configure option --enable-compressed-debug-sections={all,gas} to
+ decide whether DWARF debug sections should be compressed by default.
+
+* Add support for the ARC EM/HS, and ARC600/700 architectures. Remove
+ assembler support for Argonaut RISC architectures.
+
+* Symbol and label names can now be enclosed in double quotes (") which allows
+ them to contain characters that are not part of valid symbol names in high
+ level languages.
+
+* Added the correctly spelled -march=armv6kz, for ARMv6KZ support. The
+ previous spelling, -march=armv6zk, is still accepted.
+
* Support for the ARMv8.1 architecture has been added to the Aarch64 port.
Support for the individual ARMv8.1 Adv.SIMD, LOR and PAN architecture
extensions has also been added to the Aarch64 port.
* Replace support for openrisc and or32 with support for or1k.
* Enhanced the ARM port to accept the assembler output from the CodeComposer
- Studio tool. Support is enabled via the new command line option -mccs.
+ Studio tool. Support is enabled via the new command-line option -mccs.
* Add support for the Andes NDS32.
* Add support for the Texas Instruments MSP430X processor.
-* Add -gdwarf-sections command line option to enable per-code-section
+* Add -gdwarf-sections command-line option to enable per-code-section
generation of DWARF .debug_line sections.
* Add support for Altera Nios II.
* Add support for the Renesas RX processor.
-* New command line option, --compress-debug-sections, which requests
+* New command-line option, --compress-debug-sections, which requests
compression of DWARF debug information sections in the relocatable output
file. Compressed debug sections are supported by readelf, objdump, and
gold, but not currently by Gnu ld.
* New pseudo op .cfi_val_encoded_addr, to record constant addresses in unwind
tables without runtime relocation.
-* New command line option, -h-tick-hex, for sh, m32c, and h8/300 targets, which
+* New command-line option, -h-tick-hex, for sh, m32c, and h8/300 targets, which
adds compatibility with H'00 style hex constants.
-* New command line option, -msse-check=[none|error|warning], for x86
+* New command-line option, -msse-check=[none|error|warning], for x86
targets.
-* New sub-option added to the assembler's -a command line switch to
+* New sub-option added to the assembler's -a command-line switch to
generate a listing output. The 'g' sub-option will insert into the listing
various information about the assembly, such as assembler version, the
- command line options used, and a time stamp.
+ command-line options used, and a time stamp.
-* New command line option -msse2avx for x86 target to encode SSE
+* New command-line option -msse2avx for x86 target to encode SSE
instructions with VEX prefix.
* Add Intel XSAVE, EPT, MOVBE, AES, PCLMUL, AVX/FMA support for x86 target.
-* New command line options, -march=CPU[,+EXTENSION...], -mtune=CPU,
+* New command-line options, -march=CPU[,+EXTENSION...], -mtune=CPU,
-mmnemonic=[att|intel], -msyntax=[att|intel], -mindex-reg,
-mnaked-reg and -mold-gcc, for x86 targets.
* Add support for the "@<file>" syntax to the command line, so that extra
switches can be read from <file>.
-* The SH target supports a new command line switch --enable-reg-prefix which,
+* The SH target supports a new command-line switch --enable-reg-prefix which,
if enabled, will allow register names to be optionally prefixed with a $
character. This allows register names to be distinguished from label names.
for the VAX target in order to be more compatible with the VAX MACRO
assembler.
-* New command line option -mtune=[itanium1|itanium2] for IA64 targets.
+* New command-line option -mtune=[itanium1|itanium2] for IA64 targets.
Changes in 2.16:
* Redefinition of macros now results in an error.
-* New command line option -mhint.b=[ok|warning|error] for IA64 targets.
+* New command-line option -mhint.b=[ok|warning|error] for IA64 targets.
-* New command line option -munwind-check=[warning|error] for IA64
+* New command-line option -munwind-check=[warning|error] for IA64
targets.
* The IA64 port now uses automatic dependency violation removal as its default
* Added support for generating unwind tables for ARM ELF targets.
-* Add a -g command line option to generate debug information in the target's
+* Add a -g command-line option to generate debug information in the target's
preferred debug format.
* Support for the crx-elf target added.
* Support for ColdFire EMAC instructions added and Motorola syntax for MAC/EMAC
instrucitons.
-* New command line option -mno-shared for MIPS ELF targets.
+* New command-line option -mno-shared for MIPS ELF targets.
-* New command line option --alternate and pseudo-ops .altmacro and .noaltmacro
+* New command-line option --alternate and pseudo-ops .altmacro and .noaltmacro
added to enter (and leave) alternate macro syntax mode.
Changes in 2.15:
but still works for compatability.
* The MIPS assembler no longer issues a warning by default when it
- generates a nop instruction from a macro. The new command line option
+ generates a nop instruction from a macro. The new command-line option
-n will turn on the warning.
Changes in 2.11:
* x86 gas has a new .arch pseudo op to specify the target CPU architecture.
-* x86 gas -q command line option quietens warnings about register size changes
+* x86 gas -q command-line option quietens warnings about register size changes
due to suffix, indirect jmp/call without `*', stand-alone prefixes, and
translating various deprecated floating point instructions.
of new CPUs and formats, lots of bugs fixed.
\f
-Copyright (C) 2012-2015 Free Software Foundation, Inc.
+Copyright (C) 2012-2019 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright