Merge tag 'u-boot-rockchip-20200501' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / drivers / watchdog / mtk_wdt.c

diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index a7d4c7a..b3c597e 100644 (file)
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <dm.h>
+#include <hang.h>
 #include <wdt.h>
 #include <asm/io.h>
 
@@ -70,9 +71,12 @@ static int mtk_wdt_expire_now(struct udevice *dev, ulong flags)
        return 0;
 }
 
-static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout_ms)
+static void mtk_wdt_set_timeout(struct udevice *dev, u64 timeout_ms)
 {
        struct mtk_wdt_priv *priv = dev_get_priv(dev);
+       u64 timeout_us;
+       u32 timeout_cc;
+       u32 length;
 
        /*
         * One WDT_LENGTH count is 512 ticks of the wdt clock
@@ -88,21 +92,25 @@ static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout_ms)
         *  The MediaTek docs lack details to know if this is the case here.
         *  So we enforce a minimum of 1 to guarantee operation.
         */
-       if(timeout_ms > 15984) timeout_ms = 15984;
-       u64 timeout_us = timeout_ms * 1000;
-       u32 timeout_cc = (u32) ( (15624 + timeout_us) / 15625 );
-       if(timeout_cc == 0) timeout_cc = 1;
-       u32 length = WDT_LENGTH_TIMEOUT(timeout_cc) | WDT_LENGTH_KEY;
+       if (timeout_ms > 15984)
+               timeout_ms = 15984;
+
+       timeout_us = timeout_ms * 1000;
+       timeout_cc = (15624 + timeout_us) / 15625;
+       if (timeout_cc == 0)
+               timeout_cc = 1;
+
+       length = WDT_LENGTH_TIMEOUT(timeout_cc) | WDT_LENGTH_KEY;
        writel(length, priv->base + MTK_WDT_LENGTH);
 }
 
-static int mtk_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+static int mtk_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
 {
        struct mtk_wdt_priv *priv = dev_get_priv(dev);
 
-       mtk_wdt_set_timeout(dev, timeout);
+       mtk_wdt_set_timeout(dev, timeout_ms);
 
-        mtk_wdt_reset(dev);
+       mtk_wdt_reset(dev);
 
        /* Enable watchdog reset signal */
        setbits_le32(priv->base + MTK_WDT_MODE,
@@ -135,6 +143,7 @@ static const struct wdt_ops mtk_wdt_ops = {
 
 static const struct udevice_id mtk_wdt_ids[] = {
        { .compatible = "mediatek,wdt"},
+       { .compatible = "mediatek,mt6589-wdt"},
        {}
 };