+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2011-2013, NVIDIA Corporation.
- *
- * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <fdtdec.h>
#include <malloc.h>
#include <panel.h>
+#include <syscon.h>
#include <video_bridge.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include "displayport.h"
#include "sor.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define DEBUG_SOR 0
#define APBDEV_PMC_DPD_SAMPLE 0x20
static int tegra_dc_sor_power_up(struct udevice *dev, int is_lvds)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
+ u32 reg;
int ret;
if (sor->power_is_up)
return 0;
+ /*
+ * If for some reason it is already powered up, don't do it again.
+ * This can happen if U-Boot is the secondary boot loader.
+ */
+ reg = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
+ if (reg & DP_PADCTL_PD_TXD_0_NO)
+ return 0;
+
/* Set link bw */
tegra_dc_sor_set_link_bandwidth(dev, is_lvds ?
CLK_CNTRL_DP_LINK_SPEED_LVDS :
#if DEBUG_SOR
static void dump_sor_reg(struct tegra_dc_sor_data *sor)
{
-#define DUMP_REG(a) printk(BIOS_INFO, "%-32s %03x %08x\n", \
+#define DUMP_REG(a) printk(BIOS_INFO, \
+ "%-32s %03x %08x\n", \
#a, a, tegra_sor_readl(sor, a));
DUMP_REG(SUPER_STATE0);
const struct display_timing *timing)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
- const void *blob = gd->fdt_blob;
struct dc_ctlr *disp_ctrl;
u32 reg_val;
- int node;
/* Use the first display controller */
debug("%s\n", __func__);
- node = dev_of_offset(dc_dev);
- disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
+ disp_ctrl = (struct dc_ctlr *)dev_read_addr(dc_dev);
tegra_dc_sor_enable_dc(disp_ctrl);
tegra_dc_sor_config_panel(sor, 0, link_cfg, timing);
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
int dc_reg_ctx[DC_REG_SAVE_SPACE];
- const void *blob = gd->fdt_blob;
struct dc_ctlr *disp_ctrl;
unsigned long dc_int_mask;
- int node;
int ret;
debug("%s\n", __func__);
/* Use the first display controller */
- node = dev_of_offset(dc_dev);
- disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
+ disp_ctrl = (struct dc_ctlr *)dev_read_addr(dev);
/* Sleep mode */
tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
static int tegra_sor_ofdata_to_platdata(struct udevice *dev)
{
struct tegra_dc_sor_data *priv = dev_get_priv(dev);
- const void *blob = gd->fdt_blob;
- int node;
int ret;
- priv->base = (void *)fdtdec_get_addr(blob, dev_of_offset(dev), "reg");
+ priv->base = (void *)dev_read_addr(dev);
- node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_PMC);
- if (node < 0) {
- debug("%s: Cannot find PMC\n", __func__);
- return -ENOENT;
- }
- priv->pmc_base = (void *)fdtdec_get_addr(blob, node, "reg");
+ priv->pmc_base = (void *)syscon_get_first_range(TEGRA_SYSCON_PMC);
+ if (IS_ERR(priv->pmc_base))
+ return PTR_ERR(priv->pmc_base);
ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "nvidia,panel",
&priv->panel);