*/
#include <common.h>
-#include <displayport.h>
+#include <display.h>
#include <dm.h>
#include <div64.h>
#include <errno.h>
-#include <fdtdec.h>
+#include <video_bridge.h>
#include <asm/io.h>
#include <asm/arch-tegra/dc.h>
-#include "displayport.h"
+#include "display.h"
#include "edid.h"
#include "sor.h"
+#include "displayport.h"
DECLARE_GLOBAL_DATA_PTR;
ulong base;
};
+/**
+ * struct tegra_dp_priv - private displayport driver info
+ *
+ * @dc_dev: Display controller device that is sending the video feed
+ */
struct tegra_dp_priv {
+ struct udevice *sor;
+ struct udevice *dc_dev;
struct dpaux_ctlr *regs;
- struct tegra_dc_sor_data *sor;
u8 revision;
int enabled;
};
return 0;
}
-static int tegra_dc_dp_set_assr(struct tegra_dp_priv *dp,
- struct tegra_dc_sor_data *sor, int ena)
+static int tegra_dc_dp_set_assr(struct tegra_dp_priv *priv,
+ struct udevice *sor, int ena)
{
int ret;
DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_ENABLE :
DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_DISABLE;
- ret = tegra_dc_dp_dpcd_write(dp, DP_EDP_CONFIGURATION_SET,
+ ret = tegra_dc_dp_dpcd_write(priv, DP_EDP_CONFIGURATION_SET,
dpcd_data);
if (ret)
return ret;
}
static int tegra_dp_set_link_bandwidth(struct tegra_dp_priv *dp,
- struct tegra_dc_sor_data *sor,
+ struct udevice *sor,
u8 link_bw)
{
tegra_dc_sor_set_link_bandwidth(sor, link_bw);
static int tegra_dp_set_lane_count(struct tegra_dp_priv *dp,
const struct tegra_dp_link_config *link_cfg,
- struct tegra_dc_sor_data *sor)
+ struct udevice *sor)
{
u8 dpcd_data;
int ret;
static int tegra_dp_lt_config(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4],
u32 pc[4], const struct tegra_dp_link_config *cfg)
{
- struct tegra_dc_sor_data *sor = dp->sor;
+ struct udevice *sor = dp->sor;
u32 n_lanes = cfg->lane_count;
u8 pc_supported = cfg->tps3_supported;
u32 cnt;
const struct display_timing *timing,
struct tegra_dp_link_config *cfg)
{
- struct tegra_dc_sor_data *sor = dp->sor;
+ struct udevice *sor = dp->sor;
int err;
u32 pe[4], vs[4], pc[4];
*/
static int tegra_dc_dp_fast_link_training(struct tegra_dp_priv *dp,
const struct tegra_dp_link_config *link_cfg,
- struct tegra_dc_sor_data *sor)
+ struct udevice *sor)
{
u8 link_bw;
u8 lane_count;
static int tegra_dp_do_link_training(struct tegra_dp_priv *dp,
struct tegra_dp_link_config *link_cfg,
const struct display_timing *timing,
- struct tegra_dc_sor_data *sor)
+ struct udevice *sor)
{
u8 link_bw;
u8 lane_count;
static int tegra_dc_dp_explore_link_cfg(struct tegra_dp_priv *dp,
struct tegra_dp_link_config *link_cfg,
- struct tegra_dc_sor_data *sor,
+ struct udevice *sor,
const struct display_timing *timing)
{
struct tegra_dp_link_config temp_cfg;
printf("DP: Out of sync after %d retries\n", max_retry);
return -EIO;
}
- ret = tegra_dc_sor_detach(dp->sor);
+ ret = tegra_dc_sor_detach(dp->dc_dev, dp->sor);
if (ret)
return ret;
if (tegra_dc_dp_explore_link_cfg(dp, link_cfg, dp->sor,
}
tegra_dc_sor_set_power_state(dp->sor, 1);
- tegra_dc_sor_attach(dp->sor, link_cfg, timing);
+ tegra_dc_sor_attach(dp->dc_dev, dp->sor, link_cfg, timing);
/* Increase delay_frame for next try in case the sink is
skipping more frames */
{
struct tegra_dp_priv *priv = dev_get_priv(dev);
struct tegra_dp_link_config slink_cfg, *link_cfg = &slink_cfg;
- struct tegra_dc_sor_data *sor;
+ struct udevice *sor;
int data;
int retry;
int ret;
return -ENOLINK;
}
- ret = tegra_dc_sor_init(&sor);
- if (ret)
+ ret = uclass_first_device(UCLASS_VIDEO_BRIDGE, &sor);
+ if (ret || !sor) {
+ debug("dp: failed to find SOR device: ret=%d\n", ret);
return ret;
+ }
priv->sor = sor;
ret = tegra_dc_sor_enable_dp(sor, link_cfg);
if (ret)
}
tegra_dc_sor_set_power_state(sor, 1);
- ret = tegra_dc_sor_attach(sor, link_cfg, timing);
+ ret = tegra_dc_sor_attach(priv->dc_dev, sor, link_cfg, timing);
if (ret && ret != -EEXIST)
return ret;
/* Power down the unused lanes to save power - a few hundred mW */
tegra_dc_sor_power_down_unused_lanes(sor, link_cfg);
+ ret = video_bridge_set_backlight(sor, 80);
+ if (ret) {
+ debug("dp: failed to set backlight\n");
+ return ret;
+ }
+
priv->enabled = true;
error_enable:
return 0;
{
struct tegra_dp_plat *plat = dev_get_platdata(dev);
- plat->base = dev_get_addr(dev);
+ plat->base = dev_read_addr(dev);
return 0;
}
buf_size, &aux_stat);
}
-static const struct dm_display_port_ops dp_tegra_ops = {
+static const struct dm_display_ops dp_tegra_ops = {
.read_edid = tegra_dp_read_edid,
.enable = tegra_dp_enable,
};
{
struct tegra_dp_plat *plat = dev_get_platdata(dev);
struct tegra_dp_priv *priv = dev_get_priv(dev);
+ struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
priv->regs = (struct dpaux_ctlr *)plat->base;
priv->enabled = false;
+ /* Remember the display controller that is sending us video */
+ priv->dc_dev = disp_uc_plat->src_dev;
+
return 0;
}
U_BOOT_DRIVER(dp_tegra) = {
.name = "dpaux_tegra",
- .id = UCLASS_DISPLAY_PORT,
+ .id = UCLASS_DISPLAY,
.of_match = tegra_dp_ids,
.ofdata_to_platdata = tegra_dp_ofdata_to_platdata,
.probe = dp_tegra_probe,