{
struct rk_edp_priv *priv = dev_get_priv(dev);
- priv->regs = (struct rk3288_edp *)dev_get_addr(dev);
+ priv->regs = (struct rk3288_edp *)devfdt_get_addr(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
return 0;
}
-int rk_edp_probe(struct udevice *dev)
+static int rk_edp_remove(struct udevice *dev)
+{
+ struct rk_edp_priv *priv = dev_get_priv(dev);
+ struct rk3288_edp *regs = priv->regs;
+
+ setbits_le32(®s->video_ctl_1, VIDEO_MUTE);
+ clrbits_le32(®s->video_ctl_1, VIDEO_EN);
+ clrbits_le32(®s->sys_ctl_3, F_HPD | HPD_CTRL);
+ setbits_le32(®s->func_en_1, SW_FUNC_EN_N);
+
+ return 0;
+}
+
+static int rk_edp_probe(struct udevice *dev)
{
struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
struct rk_edp_priv *priv = dev_get_priv(dev);
struct rk3288_edp *regs = priv->regs;
- struct udevice *clk;
- int periph;
+ struct clk clk;
int ret;
ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
ret = clk_get_by_index(dev, 1, &clk);
if (ret >= 0) {
- periph = ret;
- ret = clk_set_periph_rate(clk, periph, 0);
+ ret = clk_set_rate(&clk, 0);
+ clk_free(&clk);
}
if (ret) {
debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
if (ret >= 0) {
- periph = ret;
- ret = clk_set_periph_rate(clk, periph, 192000000);
+ ret = clk_set_rate(&clk, 192000000);
+ clk_free(&clk);
}
if (ret < 0) {
debug("%s: Failed to set clock in source device '%s': ret=%d\n",
.ops = &dp_rockchip_ops,
.ofdata_to_platdata = rk_edp_ofdata_to_platdata,
.probe = rk_edp_probe,
+ .remove = rk_edp_remove,
.priv_auto_alloc_size = sizeof(struct rk_edp_priv),
};