+// SPDX-License-Identifier: GPL-2.0
/*
* EHCI HCD (Host Controller Driver) for USB.
*
* Copyright (C) 2013,2014 Renesas Electronics Corporation
* Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- *
- * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/ehci-rmobile.h>
+#include <linux/delay.h>
#include "ehci.h"
#if defined(CONFIG_R8A7740)
-static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
+static u32 usb_base_address[] = {
0xC6700000
};
#elif defined(CONFIG_R8A7790)
-static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
+static u32 usb_base_address[] = {
0xEE080000, /* USB0 (EHCI) */
0xEE0A0000, /* USB1 */
0xEE0C0000, /* USB2 */
};
-#elif defined(CONFIG_R8A7791)
-static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
- 0xEE080000, /* USB0 (EHCI) */
- 0xEE0C0000, /* USB1 */
-};
-#elif defined(CONFIG_R8A7793)
-static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
- 0xEE080000, /* USB0 (EHCI) */
- 0xEE0C0000, /* USB1 */
-};
-#elif defined(CONFIG_R8A7794)
-static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
+#elif defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
+ defined(CONFIG_R8A7794)
+static u32 usb_base_address[] = {
0xEE080000, /* USB0 (EHCI) */
0xEE0C0000, /* USB1 */
};
if (!i)
printf("error : ehci(%d) reset failed.\n", index);
- if (index == (CONFIG_USB_MAX_CONTROLLER_COUNT - 1))
+ if (index == (ARRAY_SIZE(usb_base_address) - 1))
setbits_le32(SMSTPCR7, SMSTPCR703);
return 0;
/* AHB-PCI Bridge Communication Registers */
writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr);
- writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH,
+ writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH,
&ahbcom_pci->pciahb_win1_ctr);
writel(0xf0000000 | PCIAHB_WIN_PREFETCH,
&ahbcom_pci->pciahb_win2_ctr);
writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI,
&ahbcom_pci->ahbpci_win1_ctr);
writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead);
- writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead);
+ writel(CFG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead);
writel(0xf0000000, &ahbconf_pci->win2_basead);
writel(SERREN | PERREN | MASTEREN | MEMEN,
&ahbconf_pci->cmnd_sts);