ehci-mxc: Make i.MX25 EHCI configurable

[platform/kernel/u-boot.git] / drivers / usb / host / ehci-mxc.c

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index e21f2c5..846aa3b 100644 (file)
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -28,10 +28,21 @@
 
 #define USBCTRL_OTGBASE_OFFSET 0x600
 
-#define MX25_USB_CTRL_IP_PUE_DOWN_BIT  (1<<6)
-#define MX25_USB_CTRL_HSTD_BIT         (1<<5)
-#define MX25_USB_CTRL_USBTE_BIT                (1<<4)
-#define MX25_USB_CTRL_OCPOL_OTG_BIT    (1<<3)
+#define MX25_OTG_SIC_SHIFT     29
+#define MX25_OTG_SIC_MASK      (0x3 << MX25_OTG_SIC_SHIFT)
+#define MX25_OTG_PM_BIT                (1 << 24)
+#define MX25_OTG_PP_BIT                (1 << 11)
+#define MX25_OTG_OCPOL_BIT     (1 << 3)
+
+#define MX25_H1_SIC_SHIFT      21
+#define MX25_H1_SIC_MASK       (0x3 << MX25_H1_SIC_SHIFT)
+#define MX25_H1_PP_BIT         (1 << 18)
+#define MX25_H1_PM_BIT         (1 << 8)
+#define MX25_H1_IPPUE_UP_BIT   (1 << 7)
+#define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
+#define MX25_H1_TLL_BIT                (1 << 5)
+#define MX25_H1_USBTE_BIT      (1 << 4)
+#define MX25_H1_OCPOL_BIT      (1 << 2)
 
 #define MX31_OTG_SIC_SHIFT     29
 #define MX31_OTG_SIC_MASK      (0x3 << MX31_OTG_SIC_SHIFT)
@@ -51,12 +62,57 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
 {
        unsigned int v;
 
-#if defined(CONFIG_MX25)
-       v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
-               MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
-#elif defined(CONFIG_MX31)
        v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+#if defined(CONFIG_MX25)
+       switch (port) {
+       case 0: /* OTG port */
+               v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
+                               MX25_OTG_OCPOL_BIT);
+               v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
+
+               if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                       v |= MX25_OTG_PM_BIT;
+
+               if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+                       v |= MX25_OTG_PP_BIT;
+
+               if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+                       v |= MX25_OTG_OCPOL_BIT;
+
+               break;
+       case 1: /* H1 port */
+               v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
+                               MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
+                               MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT |
+                               MX25_H1_IPPUE_UP_BIT);
+               v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
+
+               if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                       v |= MX25_H1_PM_BIT;
+
+               if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+                       v |= MX25_H1_PP_BIT;
+
+               if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+                       v |= MX25_H1_OCPOL_BIT;
+
+               if (!(flags & MXC_EHCI_TTL_ENABLED))
+                       v |= MX25_H1_TLL_BIT;
+
+               if (flags & MXC_EHCI_INTERNAL_PHY)
+                       v |= MX25_H1_USBTE_BIT;
+
+               if (flags & MXC_EHCI_IPPUE_DOWN)
+                       v |= MX25_H1_IPPUE_DOWN_BIT;
 
+               if (flags & MXC_EHCI_IPPUE_UP)
+                       v |= MX25_H1_IPPUE_UP_BIT;
+
+               break;
+       default:
+               return -EINVAL;
+       }
+#elif defined(CONFIG_MX31)
        switch (port) {
        case 0: /* OTG port */
                v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);