#define UCMD_RESET (1 << 1) /* controller reset */
/* If this is not defined, assume MX6/MX7/MX8M SoC default */
-#ifndef CONFIG_MXC_USB_PORTSC
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#ifndef CFG_MXC_USB_PORTSC
+#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#endif
/* Base address for this IP block is 0x02184800 */
return 0;
setbits_le32(&ehci->usbmode, CM_HOST);
- writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
+ writel(CFG_MXC_USB_PORTSC, &ehci->portsc);
setbits_le32(&ehci->portsc, USB_EN);
mdelay(10);
case USBPHY_INTERFACE_MODE_HSIC:
return PORT_PTS_HSIC;
default:
- return CONFIG_MXC_USB_PORTSC;
+ return CFG_MXC_USB_PORTSC;
}
}
mdelay(10);
#if defined(CONFIG_PHY)
- ret = ehci_setup_phy(dev, &priv->phy, 0);
+ ret = generic_setup_phy(dev, &priv->phy, 0);
if (ret)
goto err_regulator;
#endif
err_phy:
#if defined(CONFIG_PHY)
- ehci_shutdown_phy(dev, &priv->phy);
+ generic_shutdown_phy(&priv->phy);
err_regulator:
#endif
#if CONFIG_IS_ENABLED(DM_REGULATOR)
ehci_deregister(dev);
#if defined(CONFIG_PHY)
- ehci_shutdown_phy(dev, &priv->phy);
+ generic_shutdown_phy(&priv->phy);
#endif
#if CONFIG_IS_ENABLED(DM_REGULATOR)