drivers : usb: fsl: Implement usb Erratum A007798 workaround

[platform/kernel/u-boot.git] / drivers / usb / host / ehci-fsl.c

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 3fd9e13..8f55464 100644 (file)
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -14,9 +14,12 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 #include <hwconfig.h>
+#include <fsl_usb.h>
 
 #include "ehci.h"
 
+static void set_txfifothresh(struct usb_ehci *, u32);
+
 /* Check USB PHY clock valid */
 static int usb_phy_clk_valid(struct usb_ehci *ehci)
 {
@@ -47,6 +50,15 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
        usb_phy[0] = '\0';
 #endif
+       if (has_erratum_a007075()) {
+               /*
+                * A 5ms delay is needed after applying soft-reset to the
+                * controller to let external ULPI phy come out of reset.
+                * This delay needs to be added before re-initializing
+                * the controller after soft-resetting completes
+                */
+               mdelay(5);
+       }
        memset(current_usb_controller, '\0', 5);
        snprintf(current_usb_controller, 4, "usb%d", index+1);
 
@@ -92,15 +104,20 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
        if (!strncmp(phy_type, "utmi", 4)) {
 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
-               setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
-               setbits_be32(&ehci->control, UTMI_PHY_EN);
+               clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+                               PHY_CLK_SEL_UTMI);
+               clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+                               UTMI_PHY_EN);
                udelay(1000); /* delay required for PHY Clk to appear */
 #endif
                out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
-               setbits_be32(&ehci->control, USB_EN);
+               clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+                               USB_EN);
        } else {
-               setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
-               clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
+               clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+                               PHY_CLK_SEL_ULPI);
+               clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
+                               CONTROL_REGISTER_W1C_MASK, USB_EN);
                udelay(1000); /* delay required for PHY Clk to appear */
                if (!usb_phy_clk_valid(ehci))
                        return -EINVAL;
@@ -113,6 +130,9 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
        in_le32(&ehci->usbmode);
 
+       if (has_erratum_a007798())
+               set_txfifothresh(ehci, TXFIFOTHRESH);
+
        return 0;
 }
 
@@ -124,3 +144,17 @@ int ehci_hcd_stop(int index)
 {
        return 0;
 }
+
+/*
+ * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
+ * to counter DDR latencies in writing data into Tx buffer.
+ * This prevents Tx buffer from getting underrun
+ */
+static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
+{
+       u32 cmd;
+       cmd = ehci_readl(&ehci->txfilltuning);
+       cmd &= ~TXFIFO_THRESH_MASK;
+       cmd |= TXFIFO_THRESH(txfifo_thresh);
+       ehci_writel(&ehci->txfilltuning, cmd);
+}